A High Performance and Low Power Triple-Node-Upset Self-Recoverable Latch Design

Round 1

Reviewer 1 Report

This manuscript  presents a high performance and low power triple-node-upset self-recoverable latch. The subject addressed is of interest, and the proposed solution has some merit. However, there are many shortcuts that need to be addressed. Please, see my detailed comments below.

1. Evaluation of robustness should be performed in more detail. Critical charge should be evaluated, since the behaviour of the proposed latch might also depend on the duration of the generated glitches. Moreover, the concept of windows of vulnerability should be introduced in the evaluation. In this regard, please, see and cite "Omana et al. "Latch Susceptibility to Transient Faults and New Hardening Approach", IEEE Transactions on Computers ( Volume: 56, Issue: 9, September 2007), Page(s): 1255 - 1268.

2. Additionally, the concept of critical (susceptible) area should be introduced. Indeed, as Authors know, an energetic particle strike can induce a voltage glitch only if it impact a critical area of the latch which in an inverter is represented by the drain junction that is reversely biased. In this regard, please, see and cite "Omana et al., "High-Performance Robust Latches", IEEE Transactions on Computers ( Volume: 59, Issue: 11, November 2010), pp. 1455 - 1465.

3. Please, also discuss the possible impact of leakage affecting high-impedance node.

4. Simulation setup should be clarified, in order to better explain how delay and power have been evaluated.

Author Response

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Author Response File: Author Response.pdf

Reviewer 2 Report

- How does the proposed solution compare to layout-specific approaches where redundant nodes are spaced sufficiently far apart, such as the LEAP DICE as a layout optimization of the DICE architecture. Now the circuit is tolerant to node upsets which are anyway far apart and will not be upset together. Considering layout specific could save in the number of transistors needed and thus in power consumption and area

-For what technology do the proposed area power and delay improvements apply (hspice simulations) and how would they be technology dependent?

- There is some confusion in the text between self-recovery (noun), self-recover (verb) and self-recoverable (adjective)

- It would be useful to also compare the area power and delay number with a common non-fault tolerant D latch

- "The fast path technique is used between the inputs and outputs to reduce the delay."  Please explain or include a reference of the fast path technique

- What happens in case of SET on the clock?

- The time constants for the double exponential functions are technology dependent. Again, what technology is used here?

- In current fault injection simulations the injections are away from the clock edges. What if they are close to the clock edge?

- Could you comment on whether the comparison between the simulations of the different circuits is fair when all W/L ratios are the same. Maybe by optimizing the ratios for each circuit the comparison may look different.

 

Author Response

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Author Response File: Author Response.pdf

Reviewer 3 Report

This is a good paper on circuit alternatives to minimize the effects of TNU.

Although the authors present some significant results, all simulations were performed by HSPICE, using the PTM 32 nm process, applying a double exponential current source model to simulate the transient pulses generated by energetic particle impacts. This means that the authors did not evaluate the circuit from a technological point of view, what may limit the validity of the results. All results were obtained from a single technology and using only SPICE models.

Some important works were published considering Technology CAD simulations associated with circuit simulations and experimental data, leading to a more complete and conclusive analysis.

Authors should consider performing TCAD simulations and mixed simulations, or at least mentioning TCAD simulations performed in previous works, especially for stacked devices. Some of these works simulate the charge sharing phenomenon.

Author Response

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Author Response File: Author Response.pdf

Round 2

Reviewer 1 Report

I am happy with the revised manuscript.

Reviewer 2 Report

The authors have responded to the previous questions but it is not clearly indicated if and how this was also addressed in the manuscript. This should be added clearly for all previous points.

Additionally:

With respect to point 1 the authors should comment about the likelihood of MNUs other than through charge sharing. In my opinion this only happens at every high fluxes which are not likely in practical applications. This discussion should be added to the paper together with the comparison with layout based solutions as LEAP DICE

With respect to point 2 and point 7 the authos still do not mention the feature size (minimum gate length) of the technology. This should be included as well as a discussion how the comparison would change for different technologies as well as the time constants of the double exponential

Point 4 I would still insist on including a non-hardened D-latch for comparison as then readers can estimate the expected consumption in reference to a standard cell approach.

For the remaining points I only insist on describing them well in the paper as well.

 

 

Author Response

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Author Response File: Author Response.pdf

Reviewer 3 Report

The paper was not improved. The authors should, at least, mention TCAD simulations performed in previous published works, as references in the introduction, especially for stacked devices. Some of these works simulate the charge sharing phenomenon.

Author Response

Please see the attachment.

Author Response File: Author Response.pdf

Round 3

Reviewer 2 Report

Previous comments have been adequately addressed