Machine-Learning-Based Compact Modeling for Sub-3-nm-Node Emerging Transistors
Abstract
:1. Introduction
1.1. Related Work
1.2. Contributions
1.3. Paper Organization
2. Device Design and Dataset Generation
2.1. Process Flow of the Nanosheet FET (NSFET)
2.2. Construction of Device Datasets
2.3. Simulation Conditions
2.4. Construction of Device Datasets
3. ANN Model Architecture and Methodology
3.1. The Architecture of the Proposed ANN Model
3.2. The Workflow of the ANN Model
4. ANN Model Training and Results
5. SPICE Simulation of Circuits Using the Developed ANN Models
5.1. XOR, Ring Oscillator, and SRAM Simulation
5.2. SPICE Simulation Performance Comparison
5.2.1. Global Device Model
5.2.2. Single-Device Model
6. Conclusions
Author Contributions
Funding
Acknowledgments
Conflicts of Interest
References
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N-Type NSFET | P-Type NSFET | |
---|---|---|
[mV] | 0.218 | 0.220 |
[pA] | 98.01 | 95.03 |
[uA] | 91.13 | 90.34 |
SS 1 [mV/dec] | 65.8 | 66.4 |
Tech Node | 3 [nm] | 2.1 [nm] | 1.5 [nm] | 3 [nm] | Sub-3 [nm] |
---|---|---|---|---|---|
IRDS | IBM | Our Datasets | |||
L [nm] | 16 | 14 | 12 | 12 | 11, 12, 13 |
W [nm] | 30 | 30 | 30 | 50 | 21, 23, 25, 27, 29 |
T [nm] | 8 | 7 | 6 | 5 | 4, 5, 6 |
L [nm] | 6 | 5 | 4 | 5 | 3, 4, 5 |
T [nm] | 1.4 | 1.37 | 1.37 | 1.5 | 1, 1.5, 2 |
T [nm] | 10 | 10 | 10 | 10 | 10 |
S/D doping [cm] | - | - | - | - | 6.5 × 10 |
Channel doping [cm] | - | - | - | - | 1 × 10 |
BSIM-CMG | ANN Model | Errors [%] | ||
---|---|---|---|---|
XOR | A to Y Delay [ps] | 11.96 | 11.88 | 0.68 |
B to Y Delay [ps] | 5.94 | 5.87 | 1.13 | |
17-RO | Delay [ps] | 79.50 | 78.70 | 1.01 |
SRAM (Hold) | Margin [mV] | 286.98 | 285.88 | 0.39 |
SRAM (Read) | Margin [mV] | 129.68 | 126.01 | 2.91 |
SRAM (Write) | Margin [mV] | 223.16 | 221.72 | 0.65 |
Single-Device Model | Global Device Model | |||
---|---|---|---|---|
ANN model sizes | I-V | C-V | I-V | C-V |
(numbers of neurons in hidden layers) | (5, 5) | (5) | (20, 15) | (10, 5) |
Simulation errors | Off region: 2.5% | C: 1.3% | ||
0.3% or less | 0.3% or less | (log scale: 0.2%) | C: 1.5% | |
Medium region: 2.0% | C: 1.5% | |||
High region: 1.0% | ||||
I-V: (7 × 5) + (5 × 5) +(5 × 1) = 65 | I-V: (7 × 20) + (20 × 15) + (15 × 1) = 455 | |||
Simulation complexity 1 | C-V: (7 × 5) + (5 × 3) = 50 | C-V: (7 × 10) + (10 × 3) = 100 | ||
Activation function (tanh) calculation = 15 | Activation function (tanh) calculation = 50 | |||
Advantages | 1. Different devices can be simulated By | |||
1. The simulation speed is fast | changing the structural parameters of the circuit | |||
2. The accuracy is very high | 2. The circuit specifications (e.g., power, delay) can | |||
be evaluated based on the structural parameters | ||||
3. TCAD usage is reduced by predicting | ||||
values between structures |
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Woo, S.; Jeong, H.; Choi, J.; Cho, H.; Kong, J.-T.; Kim, S. Machine-Learning-Based Compact Modeling for Sub-3-nm-Node Emerging Transistors. Electronics 2022, 11, 2761. https://doi.org/10.3390/electronics11172761
Woo S, Jeong H, Choi J, Cho H, Kong J-T, Kim S. Machine-Learning-Based Compact Modeling for Sub-3-nm-Node Emerging Transistors. Electronics. 2022; 11(17):2761. https://doi.org/10.3390/electronics11172761
Chicago/Turabian StyleWoo, SangMin, HyunJoon Jeong, JinYoung Choi, HyungMin Cho, Jeong-Taek Kong, and SoYoung Kim. 2022. "Machine-Learning-Based Compact Modeling for Sub-3-nm-Node Emerging Transistors" Electronics 11, no. 17: 2761. https://doi.org/10.3390/electronics11172761
APA StyleWoo, S., Jeong, H., Choi, J., Cho, H., Kong, J.-T., & Kim, S. (2022). Machine-Learning-Based Compact Modeling for Sub-3-nm-Node Emerging Transistors. Electronics, 11(17), 2761. https://doi.org/10.3390/electronics11172761