Design and Implementation of a Single-Stage PFC Active-Clamp Flyback Converter with Dual Transformers

Abstract

This paper proposes an AC/DC single-stage structure by integrating a boost topology and an active clamp flyback (ACF) circuit with power-factor-correction (PFC) function. The PFC function can be achieved by controlling a boost PFC topology operated in the discontinuous conduction mode. With the coordination of active clamping components, a resonant technique is obtained and zero-voltage-switching (ZVS) can be achieved. The proposed converter is combined with the advantages of: (1) compared with two-stage circuit, a single stage circuit decreases the component of the main circuit and reduces the complexity of the control circuit; (2) a boost topology with PFC function operated in discontinuous conduction mode can be accomplished without adding any current detecting technique or detecting input signal; (3) by using the inductor from the PFC stage, ZVS function can be achieved without any additional inductor; (4) the increment of switching frequency facilitates the optimization of power density; (5) the conducting loss at the secondary side can be reduced by adding the synchronous rectification; (6) in this proposed scheme, the dual transformers with series-parallel connection are utilized, the current at the secondary side can be shared for lowering the conduction loss of the synchronous transistors. Finally, a prototype converter with AC 110 V input and DC 19 V/6.32 A (120 W) output under 300 kHz switching frequency is implemented. The efficiency of the proposed converter reaches 88.20% and 0.984 power factor in full load condition.

1. Introduction

The development of civilization and the rapid advancement of science and technology have led to a shortage of our energy. The optimization of efficiency has become one of the main goals in power electronic industries; thus, many countries have begun to establish different kinds of standards for energies gradually. In addition to that, the dimension, the efficiency, and the power density of power supplies are much more a matter of concern today. Therefore, various topologies and control methods are proposed to improve the aforementioned issues widely.

Flyback converters [1,2,3] are the most commonly used in low power electronics applications and consumer products, such as smart phone chargers, adaptors for laptops, and electric scooter battery chargers. The active-clamp techniques [4,5,6,7] have improved several drawbacks of the conventional flyback converter topology. The additional clamping capacitor can absorb the energy which is stored in the leakage inductor [8]. This helps to reduce voltage spikes during switching conditions [9,10]. By designing the parameters of the leakage inductor and the clamping capacitor to resonate appropriately, ZVS can be achieved easily [11]. This technique not only releases the energy of leakage inductance efficiently, but also makes good use of it by achieving soft switching to reduce switching loss. To pursue higher power density, increasing switching frequency can reduce the size of the transformer and magnetic component. Thus, the soft switching technique is one of the common ways to increase the switching frequency and the efficiency to a higher level. The synchronous rectification (SR) technique is also a trend to improve the efficiency of converters currently. The SR switch can be controlled by detecting the voltage across the SR switch at the secondary side. The switching period can be controlled appropriately. However, if the SR technique works perfectly and precisely, proper layout of the schematic and the good driving signal are necessary.

In addition to the better performance of converters’ efficiency, the power factor (PF) is also a key index to describe the ratio of real power and apparent power. Different output load characteristics will cause the phase shift and deformation of the input current waveform. The increment of the reactive power from the AC main will increase the losses of power line during the energy delivering process. Thus, the PFC technique [12,13] is widely used to maintain the level of power factor and to fulfill the electrical specifications of power supplies. It can be classified into passive and active [14,15,16] methods. The passive method is mainly realized by passive components which has a low cost but large size. The effect of power factor correction is also limited; active methods use the additional switch and circuit to make the input current and voltage waveform in phase to improve power factor. By using this technique, PF can approach 1 with low harmonic. The effect of the active method is much better than that of the passive one, but this method requires one independent circuit with control stage to achieve. That requires more components and the cost will also increase

In general, the structure of AC-DC converter with PFC function is a two-stage topology. It can be divided by two independent circuits [17,18]. Both of the independent circuits need to be operated by their own control systems. Hence, the number of components will definitely be increased. In order to simplify the structure of the two-stage circuit [19,20], the single-stage architecture was proposed.

In reference [21], a boost converter and a flyback converter with valley switching were combined. With the valley switching technique, switching loss is reduced by detecting auxiliary winding. The secondary side synchronous rectification is achieved through the self-made detection mechanism for increasing overall efficiency. However, it is difficult for the power factor to exceed 0.9, and the voltage spike problem of V_DS is the obstacle for developing toward a higher frequency level. Reference [22] combined a boost converter with a low-side ACF converter. Soft switching can be used to increase the switching frequency and efficiency. P-channel MOSFET can be utilized to solve the isolation issue for high-side switch in ACF topology. However, it is not common for P-channel MOSFET to have a high withstanding voltage in practical. An external inductor is also needed to achieve ZVS which increases the elements of the circuit. In reference [23], an interleaved PFC boost converter is proposed and the efficiency goes to 95% under 110 V AC input. Reference [24] proposed an ACF converter with 93% of efficiency under 120 W output condition. The overall efficiency reached about 88.35% if the ACF and PFC stages were connected. Reference [25] proposed integrating a bridgeless boost and a LLC converter. ZVS and ZCS are achieved under different conditions, but several diodes are required to prevent the wrong current direction. Thus, an external inductor is also needed in the LLC resonant tank of the circuit. It also increases the total component of the circuit. In [26], a novel high-gain DC-DC boost converter with lower component count was implemented. This novel boost converter has higher power density characteristics which is suitable for the smaller size of electronic product with PFC function to boost the voltage for 400 Vdc applications. Lower component counts also bring lower cost and loss.

To compare with previous studies, several papers have proposed a single-stage PFC converter with soft-switching technique. From [26,27,28,29], they provided different kinds of single-stage structures, and they have different benefits and features individually. In reference [27], the number of switches is one, thus the switching loss is low. In reference [28,29], the number of switches is two. The switching losses are still low, but the performances of THD for these three references are moderate or even higher. For the proposed circuit, two of the switches are used for PFC and ACF functions, the other two switchers are used for synchronous rectification for decreasing the conduction loss, and THD performs well among these studies.

Table 1. Comparison of the related single-stage converter with soft-switching function.

Item and No.	Proposed	Ref. [26]	Ref. [27]	Ref. [28]	Ref. [29]
Switch	4	1	1	2	2
Inductor	2	2	1	3	1
Diode	4	3	3	4	5
Capacitor	4	2	3	4	5
Windings	2	n/a	3	4	2
THD	Low	n/a	Moderate	High	Moderate
Switching loss	Moderate	Low	Low	Low	Low
Efficiency(%)	88.2	92.0	91.5	91.3	91.0

shows a comparison of the related studies.

To combine with the PFC stage and the DC-DC converter into one simple circuit is the main concept of this paper. It not only reduces the number of components, but also delivers the energy to the output load directly. The proposed paper is to combine the PFC technique and ACF converter into the single-stage structure. The goal of this paper is to simplify the structure and also to implement the single-stage PFC and ACF converter with dual transformer. In this proposed circuit, the dual transformers with series input and parallel output connection were selected. The benefit of this connection is that each of the transformers only needs to deliver half of the power from input to the output load. The larger inductance causes smaller current variation on L_m. This situation can reduce the peak value and effective value of the primary side current. To compare with the volume of a single winding transformer, the dual transformers are indeed larger than the single one. However, the diameter of copper wire and the size of magnetic core can be smaller for dual transformer topology. In addition, the synchronous mechanism can reduce the conduction loss effectively. To sum up the characteristics and the functions above, the proposed topology is suitable for higher power demand adaptor applications, such as gaming laptops and mini-computers.

2. Proposed AC-DC Converter

2.1. The Proposed Circuit Structure

In this paper, a single-stage circuit with AC input and DC output was developed as shown in Figure 1. The proposed design utilizes a PFC boost topology to combine with the active clamp flyback converter without any external resonant inductor [9]. The clamping capacitor C_Clamp can be shared as the common current path for both stages to reduce the number of main circuit components. The PFC stage is operated under discontinuous conduction mode for full range to lower the complexity of the PFC control method. Due to the characteristics of active clamping technique, ZVS can be easily achieved on both switches S₁ and S₂ at the primary side. In addition to that, the dual transformer connection and the synchronous rectification technique at the secondary side can reduce the conduction loss effectively.

2.2. Principle of Operation

Since the AC input voltage passes through a full-bridge rectifier, no matter whether the input voltage is positive or negative, the output voltage of the rectifier is still positive. Therefore, the following description will only focus on the positive waveform duration. As shown in Figure 2, due to the topology of the circuit, the sinusoidal waveform changes as the value of $\left|v_{in}\left(t\right)\right|$ changes. The waveform can be divided into the valley, the middle, and the peak point. The valley point means that the rectified voltage drops to 0 V and this valley point is operated as a conventional active clamp flyback converter. The peak points are influenced by the value of $\left|v_{in}\left(t\right)\right|$ the most. For the time axis, $\frac{\pi }{2}$ and $\frac{3\pi }{2}$ are the peak points of the rectified voltage. The middle points are located between the valley and the peak points which are at $\frac{\pi }{4}$ and $\frac{3\pi }{4}$ of the time axis.

After the definition of these critical points, the operation modes of the circuit will be discussed in this section. The current path of the primary side and the secondary side will be illustrated in different colors. The blue shows the power factor correction path. The red shows the active clamp current path. The green shows the current at the secondary side. These current paths help to simplify the following explanation, and the theoretical paths are shown in Figure 3.

2.2.1. Mode 1—(t₀ < t < t₁)

As shown in Figure 4, due to the previous mode, the high side switch’s parasitic capacitor C_OSS1 is discharged to zero and then S₁ turns on in this mode. ZVS of S₁ can be achieved. At the beginning of this mode, the total leakage inductor L_r, the magnetic inductors L_m1 and L_m2 keep the same current direction and charge to C_Bus as the previous state. The energy stored in the power factor correction inductor L_PFC also charges to the capacitor C_Bus at the same time. When the energy stored in L_r, L_m1, and L_m2 are released, the current direction of these inductors turns to be positive and starts to be charged. When the charging process of C_Bus ends, the coming operation mode will be carried out. In this mode, there is no energy delivered to the secondary side. The switches S₃ and S₄ at the secondary side are turned off; hence, the energy of the output load R_O is provided by the output capacitor C_o. Through the analysis above, Equations (1) and (2) can be obtained below. ω₁ is the angular frequency of the AC input voltage. In this mode, the angular frequency ω and the impedance Z are also shown in Equation (3).

$$i_{LPFC}\left(t\right)=i_{LPFC}\left(t_0\right)·\cos \omega \left(t-t_0\right)+\frac{\left[\left|V_m·\sin {\omega }_1\left(t-t_0\right)\right|-V_{Bus}-v_{Clamp}\left(t_0\right)\right]·\sin \omega \left(t-t_0\right)}{Z}$$

(1)

$$v_{Clamp}\left(t\right)=\left[\left|V_m·\sin \omega \left(t-t_0\right)\right|-V_{Bus}-v_{Clamp}\left(t_0\right)\right]·\left(1-\cos \omega \left(t-t_0\right)\right)+Z·i_{LPFC}\left(t_0\right)·\sin \omega \left(t-t_0\right)$$

(2)

$$\omega =\frac{1}{\sqrt{L_{PFC}·C_{Clamp}}} ; Z=\sqrt{\frac{L_{PFC}}{C_{Clamp}}}$$

(3)

2.2.2. Mode 2—(t₁ < t < t₂)

As shown in Figure 5, in this mode, S₁ still turns on. L_PFC continues releasing the energy and charging to the clamping capacitor C_Clamp from mode 1. L_PFC also charges to L_r, L_m1, and L_m2. In the meantime, C_Bus also charges to L_r, L_m1, and L_m2 through S₁. When the energy of L_PFC is exhausted, i_LPFC drops to 0 A. Thus, V_Clamp starts to be clamped at a constant voltage temporarily. This mode ends when S₁ is turned off.

2.2.3. Mode 3—(t₂ < t < t₃)

As shown in Figure 6, during the dead time, C_OSS1 is charged by the path of C_Bus. The charging path will be open when C_OSS1 is charged to the sum of V_Bus and v_Clamp. Since L_r, L_m1, and L_m2 maintain the same current direction from the previous step, the energy on C_OSS2 will be taken away while the current goes through S₂. After C_OSS2’s energy releases to zero, S₂’s body diode D_S2 will be turned on to maintain the negative current path. This mode ends when dead time is finished. In this step, no energy is transmitted to the secondary side. The secondary side switches S₃ and S₄ are turned off, the energy of the output load R_O is provided by the output capacitor C_o. Equation (4) can be analyzed through this step; ω and Z’s equation are shown in (5).

$$i_{Lr}\left(t\right)=i_{Lr}\left(t_2\right)·\cos \omega \left(t-t_2\right)+\frac{V_{Bus}·\sin \omega \left(t-t_2\right)}{Z}$$

(4)

$$\omega =\frac{1}{\sqrt{(L_r+2L_m)·(C_{COSS1}+C_{COSS2})}} ; Z=\sqrt{\frac{L_r+2L_m}{C_{COSS1}+C_{COSS2}}}$$

(5)

2.2.4. Mode 4—(t₃ < t < t₄)

As shown in Figure 7, due to the previous mode, the low side switch’s capacitor C_OSS2 is released to zero during the switching of S₂ in this mode. S₂’s ZVS can be achieved. L_PFC will be charged by input AC power. L_r and C_Clamp start to resonate with each other, the next mode begins when L_r releases its energy to zero. The magnetizing inductors L_m1 and L_m2 transfer energy to secondary side, v_GS3 and v_GS4 turn high to achieve synchronous rectification function to reduce losses of S₃ and S₄. Equations (6) and (7) can be analyzed through this step; ω and Z’s equation are shown in (8).

$$i_{Lr}\left(t\right)=i_{Lr}\left(t_3\right)·\cos \left[\omega \left(t-t_3\right)\right]+\frac{\left[2·n·V_O-v_{Clamp}\left(t_3\right)\right]·\sin \left[\omega \left(t-t_3\right)\right]}{Z}$$

(6)

$$v_{Clamp}\left(t\right)=\left[2·n·V_O-v_{Clamp}\left(t_3\right)\right]·\left(1-\cos \left[\omega \left(t-t_3\right)\right]\right)+Z·i_{Lr}\left(t_3\right)·\sin \left[\omega \left(t-t_3\right)\right]$$

(7)

$$\omega =\frac{1}{\sqrt{L_r·C_{Clamp}}} ; Z=\sqrt{\frac{L_r}{C_{Clamp}}}$$

(8)

2.2.5. Mode 5—(t₄ < t < t₅)

As shown in Figure 8, due to the exhaustion of L_r, C_Clamp releases its energy to L_r. Both components keep resonating with the opposite current direction as shown in mode 4. L_m1 and L_m2 release their energy to secondary side at the beginning of this step. When both of the magnetizing inductors release to zero, C_Clamp will transfer its energy to L_m1, L_m2, and the secondary side. The current direction of i_Lm1 and i_Lm2 will be opposite to the beginning of this step. L_m1 and L_m2 transfer energy to secondary at the beginning of this step, C_Clamp will keep transferring when the magnetizing inductors are out of energy. v_GS3 and v_GS4 remain high to achieve synchronous rectification function for reducing losses of S₃ and S₄. Equations (9) and (10) can be analyzed through this step; ω and Z’s equation are shown in (11).

$$i_{Lr}\left(t\right)=-i_{Lr}\left(t_4\right)·\cos \omega \left(t-t_4\right)+\frac{\left[2·n·V_O-v_{Clamp}\left(t_4\right)\right]·\sin \omega \left(t-t_4\right)}{Z}$$

(9)

$$v_{Clamp}\left(t\right)=\left[2·n·V_O-v_{Clamp}\left(t_4\right)\right] ·\left(1-\cos \omega \left(t-t_4\right)\right)+Z·i_{Lr}\left(t_4\right)·\sin \omega \left(t-t_4\right)$$

(10)

$$\frac{1}{\sqrt{L_r·C_{Clamp}}} ; Z=\sqrt{\frac{L_r}{C_{Clamp}}}$$

(11)

2.2.6. Mode 6—(t₅ < t < t₆)

As shown in Figure 9, during the dead time, C_OSS2 starts to be charged. The charging path is open when C_OSS2 is charged to the sum of V_Bus and v_Clamp. Since L_r, L_m1, and L_m2 maintain the same current direction from the previous step, the energy on C_OSS1 will be taken away during the current went through S₁. After C_OSS1’s energy releases to zero, S₂’s body diode D_S2 is turned on to maintain the negative current path. In this mode, L_PFC starts to discharge and to release energy to C_Clamp, C_Bus, and C_OSS2. C_OSS1 also discharges at the same time. This mode ends when dead time is finished. C_Clamp keeps transferring energy to secondary side. v_GS3 and v_GS4 remain high to achieve synchronous rectification function. Equation (12) can be analyzed through this step; ω and Z’s equation are shown in Equation (13).

$$i_{Lr}\left(t\right)=\frac{\left[2·n·V_O-v_{Clamp}\left(t_5\right)\right]·\sin \omega \left(t-t_5\right)}{Z}-i_{Lr}\left(t_5\right)·\cos \omega \left(t-t_5\right)$$

(12)

$$\omega =\frac{1}{\sqrt{L_r·(C_{COSS1}+C_{COSS2})}} ; Z=\sqrt{\frac{L_r}{C_{COSS1}+C_{COSS2}}}$$

(13)

2.3. Design Consideration

In order to simplify the design of single-stage architecture, the power factor correction inductor is designed to operate under discontinuous conduction mode [10,11]. The extra input voltage or current signal detection mechanism for continuous conduction mode or boundary conduction mode [12,13] can be removed. In the case of discontinuous conduction mode, Figure 10 can be drawn. The relationship of i_LPFC during the on and off time of the power switch can be obtained through the operation process, where v_total(t’) represents V_Bus + v_Clamp(t’).

Equation (14) can be derived from Figure 10 and references [14,15]. Where V_m represents the input peak voltage, D_on is the duty cycle of S₂, T_S is the switching period, and x is the voltage ratio, as shown in Equation (15). After combining Equations (14) and (15), Figure 11 can be obtained. The x-axis represents D_on, and y-axis represents voltage ratio x. Through a single curve, it can be noticed that the range of x will increase during the increment of D_on. In order to avoid excessive variation of the output voltage, D_on is set under 40%. Different curves can be compared under the same variation range of D_on. Take the range of D_on varying from 30% to 40% as an example, x increases to 0.304 with L_PFC of 60 μH, but x increases to 0.833 with L_PFC of 40 μH. It can be seen that the smaller inductance causes a higher voltage variation range. Larger variation of x also causes a higher voltage spike to increase the switching loss during the transient time. To avoid the higher voltage variation, the inductance of L_PFC should be higher. However, if L_PFC is high, i_LPFC still has to be in discontinuous conduction mode at the same time to avoid the decrement of power factor. If the converter operates in heavy load condition or the peak value of i_LPFC goes to continuous conduction mode, these impacts will decrease the power factor. Therefore, the trade-off between loss and the power factor for the inductance of L_PFC should be designed carefully.

$$L_{PFC}=\frac{V_m^2·D_{on}{}^2·T_S}{2·P_{in}}\times \left(\frac{x^3}{\sqrt{x^2-1}}·\left(1+\frac{2}{\pi }{\tan }^{-1}\frac{1}{\sqrt{x^2-1}}\right)-x^2-\frac{2}{\pi }x\right)$$

(14)

$$x=\frac{v_{total}\left(t^{\prime }\right)}{V_m}=\frac{V_{Bus}+v_{Clamp}\left(t^{\prime }\right)}{V_m}$$

(15)

To compare with the conventional boost topology for single stage structure [16], the power factor correction stage includes C_Clamp in the proposed topology. Figure 12 can be obtained through Equation (2) under different v_in. Noticing v_Clamp is influenced by v_in, the value of v_DS1 and v_DS2 will be influenced as well. Therefore, the value of C_Clamp is related to the switching loss of the primary switches. In Figure 12, the x-axis represents the time and the y-axis represents v_Clamp.

C_Clamp and L_r are the main resonant components when S₂ turns on. The resonant period T_r between the two elements is about twice of the turn-on time when S₂ is on as shown in Equation (16). C_Clamp will affect the switching loss and the capacitance of C_Clamp can be further optimized by SIMetrix software. As shown in Figure 13a, the smaller capacitance can reduce the switching loss of S₂. In the meanwhile, from Figure 13b, this will also increase the conduction loss of the synchronous rectifier switch at the secondary side. That is, the smaller capacitance causes higher current at the secondary side. Therefore, the capacitance selection of C_Clamp should be considered carefully.

$$C_{Clamp}=\frac{D_{on}^2·T_S^2}{{\pi }^2·L_r}$$

(16)

Since S₂ needs to withstand the current stress from L_PFC and C_Clamp in mode 4 and 5, the switching loss of S₂ has a great impact for the efficiency. In order to reduce the switching loss caused by S₂, the value of L_m is designed to be larger than L_m(min) to reduce the peak current at the primary side. By using the voltage-second balancing law, Equation (17) can be obtained. Where L_m(min) represents the minimum inductance of the continuous conduction mode. In this proposed topology, L_m(min) is twice that of the conventional single transformer connection under this condition. This design consideration makes S₁ have no ZVS function without L_m, which causes the failure of ZVS at the valley part. However, the overall efficiency still can be improved by reducing the switching loss of S₂.

$$L_{m\left(min\right)}=\frac{D_{on}^2·R_O·n^2·\eta }{f}$$

(17)

A step-by-step design flow chart of proposed converter is shown in Figure 14. The parameters of the converter can be acquired step by step. At first, the input and the output specifications have to be determined. Then, the following parameters of key components can be calculated by using Equations (14), (16) and (17). After all the key components are obtained, the optimization with Matlab is verified to avoid L_PFC entering into CCM or ZVS failure. Finally, the circuit can be implemented efficiently.

2.4. Switch Utilization Ratio

The definition of switch utilization ratio (U) is the output power of the converter circuit derived per unit of switch stress. For this study, the proposed ACF converter of D_on is set for 0.35 in practical design consideration. Therefore, the peak of U is 0.385 from the figure. The curve of U is plotted as shown in Figure 15.

2.5. Steady-State Voltage Gain with Varying Duty

In Figure 16, the steady-state voltage gain is depicted with varying duty-cycle. It shows a curve of the steady-state voltage gain response of the proposed converter for the duty-cycle changing from 10% to 100%.

3. Experimental and Simulation Result

The specification of the proposed circuit is shown in

Table 2. Circuit specification.

Parameters	Value
Input voltage Vin Output voltage Vo Output current Io	110 V, 60 Hz 19 V 6.32 A
Switching frequency fs	300 kHz

, and

Table 3. Component parameters.

Parameters	Value
LPFC Lr Lm1, Lm2	55 μH 5.4 μH 31 μH
Np1:Ns1	3.33:1
Np2:Ns2	3.33:1
CBus	820 μF
CClamp	30 nF

shows the parameters of the proposed circuit. L_r is the total leakage inductance of the dual transformers.

Figure 17 shows the waveforms of input voltage v_in, current i_in, and i_LPC under light load 30 W. Figure 18 shows the waveform of full load 120 W. Since i_LPFC is designed for discontinuous conduction mode, the power factor correction function can be achieved without detecting input signals.

The waveforms are measured at valley, middle, and peak points individually under full load condition. In order to reduce the switching loss on S₂, L_m is designed to be larger than L_m(min) for lowering the peak current. This situation causes i_Lm to be positive during valley point. ZVS of S₁ will fail without L_m in mode 6 shown Figure 19. On the other hand, S₂ will achieve ZVS through the current of L_r, L_m1, and L_m2 shown in Figure 20. Figure 21 shows the simulation waveforms during the valley point to verify the experimental results. As shown in Figure 22, L_r and C_Clamp only resonate during the turn off time of S₁, which is much shorter than the middle point and the valley point during the resonant time.

At the middle point under the full load condition, i_LPFC helps the negative current to flow through S₁ for achieving ZVS in mode 1 as shown in Figure 23. From Figure 24, they show the period resonated by L_PFC and C_Clamp. In this situation, the extension of resonant time for v_Clamp will also influence S₁ and S₂’s switching loss. S₂ achieves ZVS through the current from L_r, L_m1, and L_m2 in mode 2 as shown in Figure 25. In Figure 26, it shows the simulation waveforms to verify the experimental results. Because the current of S₂ is the summation of i_Lr and i_LPFC, the peak of i_DS2 will increase when i_LPFC increases.

Due to the negative current of i_LPFC, S₁ can easily achieve ZVS function at the peak point as shown in Figure 27. S₂ also achieves ZVS by the total current of L_r, L_m1, and L_m2 as shown in Figure 28. Under the influence of v_Clamp’s variation, the higher v_DS1 with the lower i_DS1 occurs at the moment when S₁ turns off momentarily. On the other hand, the higher i_DS2 with the lower v_DS2 occurs at the moment when S₂ turns off instantaneously. This complementary situation is achieved by the appropriate selection of the clamping capacitance. As shown in Figure 29, it can be seen that the charging and discharging behavior of v_Clamp is most severe at the peak point, which reduces the switching loss caused by S₂ indirectly. In Figure 30, the simulation waveform during the peak point is shown to verify the experimental results.

Because of the extension of L_r and C_Clamp’s resonant time, the waveform of i_DS2 will be affected. The difference of i_DS2 between Figure 20 and Figure 28 can clearly be seen. This situation will further affect the waveforms of i_DS3 and i_DS4. From Figure 31, the current of i_DS3 and i_DS4 are smaller at the secondary side for reducing the switching loss of S₃ and S₄ effectively.

In Figure 32, the efficiency of the proposed converter is measured and summarized. At light load condition, the efficiency starts from 85.8%. When the output goes to full load, the efficiency reaches 88.20%.

In addition, harmonic current is also a key factor to verify the PFC function. In Figure 29, the harmonic current of the proposed converter is measured which is shown in green bars. Moreover, the standard of IEC-61000-3-2 is compared which is shown in blue bars. Based on Figure 33, the current of odd-harmonic is lower than the standard.

Due to the single-stage structure, the two switches at the primary side should withstand the current stress from both side of PFC and ACF stage as shown in mode 1 and mode 5. This will cause switching loss and conduction loss on these two switches to dominate a major part of the total loss for this circuit, especially for higher switching frequency. To compare with CCM PFC converters for detecting AC input signal, the proposed topology has a slightly higher THD causing PF to drop slightly. The reason is that the designed L_PFC needs to keep the PFC current operating in DCM for low power applications, and there is no need to detect any input signal.

As shown in

Table 4. Experimental measurement.

Loading Level	25%	50%	75%	100%
vin	109.89 V	109.92 V	109.89 V	109.92 V
iin	326.6 mA	638.1 mA	955.8 mA	1.26 A
VO	19.05 V	19.01 V	19.02 V	19.02 V
IO	1.58 A	3.16 A	4.74 A	6.32 A
PF	0.977	0.979	0.978	0.984
Eff%	85.84%	87.48%	87.78%	88.20%

, after the measurements, the power factor and the efficiency reached 0.977 and 85.84% under light load. At full load condition, the power factor reached 0.984 and the efficiency goes to 88.20%.

Table 5. Power losses calculation on the switches at primary and secondary sides [30].

Item.	Model No.	RDS(ON)/CISS	Conduction Loss (IDS,RMS2 × RDS(ON)) × 2	Switching Loss $\frac{1}{2}$ ×(Ciss × VGS2 × f × 2)
Pri. (S1, S2)	C3M0065090D	65 mΩ/660 pF	0.206 W (for 2 pcs)	0.045 W (for 2 pcs)
Sec. (S3, S4)	BSC160N15NS	16 mΩ/1370 pF	1.278 W (for 2 pcs)	0.093 W (for 2 pcs)

also shows a calculation for power loss of these switches under full load condition.

The prototype of the proposed single-stage PFC active-clamp flyback converter with dual transformers is shown in Figure 34. The output power is 120 W (19 V, 6.32 A) which is suitable for laptop adaptor application. The dimension is measured in centimeters (12.5 cm × 15 cm).

4. Conclusions

This paper proposes a single-stage active clamp flyback converter with dual transformers in series and parallel connection which is implemented. Through the proposed design, the PFC inductor assists the negative current path of the high-side power switch S₁ for achieving ZVS without any additional inductors except the rectified voltage drops to the valley point. The proposed design can not only decrease the switching loss but also lower the number of the components. S₂ can also achieve ZVS by the magnetizing current from the dual transformers.

By connecting the dual transformers in series connection at primary side and parallel connection at secondary side, the copper loss and the conduction loss can be saved effectively. The efficiency of 88.20% with power factor 0.984 under full load condition has been achieved.