# The Three-Carrier Quasi Switched Boost Inverter Control Technique

^{1}

^{2}

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## Abstract

**:**

## 1. Introduction

## 2. Three-Phase, Two-Level QSBI

_{S}source, an inductor (L), a capacitor (C), two diodes (D1, D2), six inverter IGBT switches (denoted SxP, SxN where x is a, b, c), and an IGBT switch S in the boost DC–DC circuit. The output load phase voltage is u

_{a}, u

_{b}, and u

_{c}.

#### 2.1. Short Circuit for Booster Mode

_{2}turns on, so the VSI operates with a voltage supply to the capacitor C. The state of the six switches on the inverter side is like in a normal VSI, so that:

#### 2.2. None Short Circuit Mode (NST)

_{1}, D

_{2}) are turned on. The energy from the source (V

_{S}) and inductor (L) charges capacitor C and supplies the power to the VSI.

#### 2.3. Short Circuit in Inverter Mode (ST)

_{S}is the ON time of switch S, and t

_{ST}is the short circuit time on the VSI.

#### 2.4. The Two Carrier Technique for QSBI

_{S}and t

_{ST}are the same as shown in Figure 5, the duty cycle on the DC–DC boost and the inverter are the same too, and if the offset function is the third harmonic component, they have the same values as in Formula (7):

## 3. The Proposed Algorithms

_{s}and for shoot-through in the VSI as d

_{ST}

_{.}The proposed technique reduces the inverter (d

_{ST}) duty cycle and increases the modulation index, lowering the voltage of the DC-link capacitor (V

_{C}). In one cycle, there are two S turn-ons and four short-circuits in the VSI. Per carrier period, there are two S turn-ons and four short-circuits in the VSI. This is the same as when using three triangle carriers, two for the VSI and one for the booster, where each waver is phase shifted by α angle where α = π/3. The inverter carrier is CrI, while the booster carriers are CrB1 and CrB2.

_{S}/4) and charging time with the inverter switches closed (t

_{ST}/2) should be the same, so that:

_{S}and reference RMS voltage (u

_{rms}) as in (19):

_{S}) and reference RMS output voltage, $k=\frac{{V}_{S}}{{u}_{rms}}$. Compared with conventional techniques [16], the modulation index of the proposed algorithm increases the Δm value, calculated as:

_{S}= 55 V, referent output voltage u

_{rms}= 110 V, meaning k = 0.5 if the proposed algorithms are used and the modulation index can be reduced by 29% compared with the method used in [16]. Compared to the two carrier technique, the voltage across the capacitor (C) will decrease with $\u2206Vc$:

_{S}) is 55 V, 110 V, and 165 V, respectively. The calculation results of the voltage across the capacitor, the percentage reduction in the capacitor voltage, and the current ripple compared with the conventional technique are presented in Table 2.

## 4. Simulation and Experimental Results

_{S}= 55 V. From the top to the bottom of Figure 11, the first graph (Figure 11a) is the voltage of the capacitor, the second is the current in the boost inductor (Figure 11b), and the third is the inverter output voltage (Figure 11c). Red lines are with two carriers, and the blues are with the proposed algorithm. It is easy to see that the capacitor voltage reduces from 483 V down to 376 V. ΔV

_{C}is 107 V, a 22.15% reduction, and the input current ripple reduces from 0.569 A down to 0.550 A, a 3.5% reduction. Moreover, the average input current also decreased from 4.99 A to 3.87 A, equivalent to a 22.4% reduction. These values are presented in Table 2.

_{S}is 110 V, the voltage of the capacitor reduces to 348 V with ΔV

_{C}being 81 V (an 18.9% reduction) (Figure 12a) and the input current ripple reduces from 0.963 A down to 0.891 A (a 7.47% reduction) (Figure 12b).

_{S}= 165 V, the ΔV

_{C}is 52 V (a 13% reduction) and the input current ripple reduces from 1.09 A down to 0.949 A (a 12.9% reduction) (Figure 13a,b).

_{c}, the amplitude of the harmonics with the two-carrier technique is higher than it is in the proposed algorithm. This is not a problem because the proposed method has a higher modulation index.

_{S}= 2.3 mH and C

_{S}= 11.2 µF (Figure 15).

## 5. Conclusions

_{S}) and reference RMS output voltage (k) is equal to 0.5. Compared with the two-carrier technique, the proposed method reduces the voltage on the capacitor by 22.16%, but at k = 1.5 this figure is only 13.97%.

## Author Contributions

## Funding

## Conflicts of Interest

## Nomenclature

V_{S} | DC power supply | (V) |

V_{L} | Voltage on the inductor | (V) |

I_{L} | Current in the inductor | (A) |

ΔI_{L} | Ripple of the current in the inductor | (A) |

V_{PN} | DC link voltage | (V) |

$\widehat{u}$ | Amplitude of the phase voltage fundamental | (V) |

u_{rms} | RMS value of the phase voltage fundamental | (V) |

m | Modulation index | |

t_{S} | Short circuit time on the DC–DC boost side | (s) |

t_{ST} | Short circuit time on the VSI side | (s) |

d_{S} | Duty cycle when switch S is turned on | |

d_{ST} | Duty cycle when the VSI is shot through |

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**Figure 4.**The operation modes of 3P2LQSBI: (

**a**) short circuit for booster mode, (

**b**) non-short circuit mode, and (

**c**) short circuit in inverter mode (shoot-through mode).

Vector | Value | Switch On | Note |
---|---|---|---|

$\overrightarrow{{\mathrm{V}}_{1}}$ | 1.0.0 | ${\mathrm{S}}_{\mathrm{aP}},{\mathrm{S}}_{\mathrm{bN}},{\mathrm{S}}_{\mathrm{cN}\text{}}$ | Active vector |

$\overrightarrow{{\mathrm{V}}_{2}}$ | 1.1.0 | ${\mathrm{S}}_{\mathrm{aP}},{\mathrm{S}}_{\mathrm{bP}},{\mathrm{S}}_{\mathrm{cN}\text{}}$ | Active vector |

$\overrightarrow{{\mathrm{V}}_{3}}$ | 0.1.0 | ${\mathrm{S}}_{\mathrm{aN}},{\mathrm{S}}_{\mathrm{bP}},{\mathrm{S}}_{\mathrm{cN}\text{}}$ | Active vector |

$\overrightarrow{{\mathrm{V}}_{4}}$ | 0.1.1 | ${\mathrm{S}}_{\mathrm{aN}},{\mathrm{S}}_{\mathrm{bP}},{\mathrm{S}}_{\mathrm{cP}\text{}}$ | Active vector |

$\overrightarrow{{\mathrm{V}}_{5}}$ | 0.0.1 | ${\mathrm{S}}_{\mathrm{aN}},{\mathrm{S}}_{\mathrm{bN}},{\mathrm{S}}_{\mathrm{cP}\text{}}$ | Active vector |

$\overrightarrow{{\mathrm{V}}_{6}}$ | 1.0.1 | ${\mathrm{S}}_{\mathrm{aP}},{\mathrm{S}}_{\mathrm{bN}},{\mathrm{S}}_{\mathrm{cP}\text{}}$ | Active vector |

$\overrightarrow{{\mathrm{V}}_{7}}$ | 1.1.1 | ${\mathrm{S}}_{\mathrm{aP}},{\mathrm{S}}_{\mathrm{bP}},{\mathrm{S}}_{\mathrm{cP}\text{}}$ | Zero vector |

$\overrightarrow{{\mathrm{V}}_{0}}$ | 0.0.0 | ${\mathrm{S}}_{\mathrm{aN}},{\mathrm{S}}_{\mathrm{bN}},{\mathrm{S}}_{\mathrm{cN}\text{}}$ | Zero vector |

**Table 2.**The calculation results of the voltage across the capacitor, the percentage reduction in the capacitor voltage, and the current ripple.

V_{S} | u_{rms} | ΔV_{C} | ΔV_{C}% | ΔI_{L}% |
---|---|---|---|---|

55 | 110 | 107 | 22.16 | 3.65 |

110 | 110 | 79 | 18.59 | 7.88 |

165 | 110 | 52 | 13.97 | 12.82 |

No | Devices | Parameter | Note |
---|---|---|---|

1 | L_{S}-C_{S} | 2.3 mH–1.2 $\mathsf{\mu}$F | Filter |

2 | Load | 363 Ω–1 mH | Three Phase Load |

3 | L | 4.21 mH | Boost |

4 | C | 50 $\mathsf{\mu}$F | Boost |

5 | D_{1}, D_{2} | RHR15120 | Diode |

6 | IGBT | FGA25N120 |

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**MDPI and ACS Style**

Quach, T.-H.; Le, X.-V.; Truong, V.-A.
The Three-Carrier Quasi Switched Boost Inverter Control Technique. *Electronics* **2021**, *10*, 2019.
https://doi.org/10.3390/electronics10162019

**AMA Style**

Quach T-H, Le X-V, Truong V-A.
The Three-Carrier Quasi Switched Boost Inverter Control Technique. *Electronics*. 2021; 10(16):2019.
https://doi.org/10.3390/electronics10162019

**Chicago/Turabian Style**

Quach, Thanh-Hai, Xuan-Vinh Le, and Viet-Anh Truong.
2021. "The Three-Carrier Quasi Switched Boost Inverter Control Technique" *Electronics* 10, no. 16: 2019.
https://doi.org/10.3390/electronics10162019