RRAM Random Number Generator Based on Train of Pulses

Abstract

In this paper, the modulation of the conductance levels of resistive random access memory (RRAM) devices is used for the generation of random numbers by applying a train of RESET pulses. The influence of the pulse amplitude and width on the device resistance is also analyzed. For each pulse characteristic, the number of pulses required to drive the device to a particular resistance threshold is variable, and it is exploited to extract random numbers. Based on this behavior, a random number generator (RNG) circuit is proposed. To assess the performance of the circuit, the National Institute of Standards and Technology (NIST) randomness tests are applied to evaluate the randomness of the bitstreams obtained. The experimental results show that four random bits are simultaneously obtained, passing all the applied tests without the need for post-processing. The presented method provides a new strategy to generate random numbers based on RRAMs for hardware security applications.

1. Introduction

Random number generators (RNGs) are fundamental components in applications, such as problem-solving techniques, industrial simulations, computer games or hardware encryption modules in communication systems [1]. Some critical applications, such as those for security, where the generation of keys and nonces are essential, require random number sequences that must fulfill strict statistical test requirements [2]. In these applications, there is a need for devices which meet such requirements, harvesting entropy from physical phenomena, such as jitter, metastability, etc. RNGs based on physical sources of entropy are called true random number generators (TRNGs) [3]. Hence, due to the growing security concern in the era of the Internet of Things (IoT), TRNGs become indispensable. In fact, several TRNGs have previously been demonstrated based on thermal noise [4], random telegraph noise (RTN) [5], or current fluctuations [6]. Nevertheless, these TRNGs have drawbacks in scalability, power consumption, and are sensitive to external parameters, such as temperature, or need post-processing, such as the Von Neumann correction. In this context, resistive random access memory (RRAM) devices are an emerging technology with excellent properties in terms of power consumption, switching speed, endurance, scalability and CMOS-compatibility. The non-volatility properties of these devices motivated their initial use as memory devices [7]. However, RRAMs are also used in other fields such as neural networks [8], where these devices are utilized as synaptic elements, and digital logic, where RRAMs are leveraged to implement basic Boolean logic [9]. Massive production of RRAMs has been limited by their inherent stochastic features, such as probabilistic switching, inter- and intra-device variability and RTN [10]. Extensive research effort is currently devoted to overcoming these limitations [11,12]. However, the very same challenges provide interesting features for the generation of random numbers in hardware security applications [13]. In this direction, recent works have been focused on the extraction of random numbers by exploiting the cycle-to-cycle variability of RRAMs [14,15], the device-to-device variability [16], the competition between paired devices [17,18], the combination of cycle-to-cycle and device-to-device variability [19] and the occurrence of RTN [20,21,22]. Nevertheless, all these existing RRAM-based TRNGs still suffer from some limitations, such as complexity in design, need for post-processing or high cost. In this context, the present work investigates the behavior of RRAMs under the application of a train of RESET pulses for the generation of random bits. Variability is observed in the number of pulses required to drive the device to a specific high-resistance state (HRS). Experimental results show that multiple random bits can be extracted from the number of RESET pulses needed to be applied to the RRAM to induce a specific resistance state.

The rest of the paper is organized as follows. The details of the devices and the experimental set-up are presented in Section 2. Section 3 is devoted to showing the conductance variability of the devices when applying a train of pulses. The TRNG and the experimental results are presented in Section 4. Finally, the conclusions are drawn in Section 5.

2. Experimental Set-Up

The RRAM devices used in the experiments are TiN/Ti/HfO₂/W structures. The 10 nm-thick HfO₂ layer was grown by atomic layer deposition (ALD) at 225 °C using TDMAH and H₂O as precursors, and the top and bottom metal electrodes were deposited by magnetron sputtering. The bottom electrode consists of a 50 nm-W layer deposited on a 20 nm-Ti adhesion layer on a highly doped n-type silicon wafer, and the top electrode is a 200 nm-TiN on a 10 nm-Ti layer acting as oxygen getter material. Electrical contact to the bottom electrode is made through the Al-metallized back of the silicon wafer. The resulting structures are square cells of 15 × 15 μm², 5 × 5 μm² and 2 × 2 µm². The different sizes of the devices do not have any influence on the results since they reported similar behaviors for the purpose of the present work. A top view optical image is shown in Figure 1a and the corresponding schematic cross-section of the active area is given in Figure 1b.

The electrical characterization of the devices was performed using a Keysight B2912A Precision Source/Measure Unit (SMU) and a Tektronix Arbitrary Function Generator (AFG3102). The set-up is illustrated in Figure 2. For the automatic and successive measurements, the instruments were connected to a computer via GPIB and controlled using MATLAB.

3. Resistance Variability under Pulse Programming

The physical mechanism of RRAMs relies on the formation and dissolution of a conductive filament (CF) composed of defects in oxide (dielectric) between the two metal electrodes. Once this CF is formed, RRAMs can reversibly switch between a high- and a low-resistance state (LRS). This switching behavior is obtained applying a voltage difference across the electrodes. The formation and dissolution of the CF is a stochastic process, generating variability from cell to cell (inter-device variability) and also from cycle-to-cycle (intra-device variability) [23,24]. These statistical fluctuations have a significant impact on the resistance of the device. In this work, we exploit this intra-device variability. In fact, in this section, the variability in the number of pulses applied to the RRAM to reach a specific resistance is analyzed during the RESET operation. The equivalent analysis is not presented for a train of SET pulses due to the abrupt SET characteristic of the target devices. This fact is observed in the DC resistive switching behavior, see Figure 3, where double-sweep voltage ramps were applied from 0 V to +1.1 V for the SET, and from 0 V to −1.4 V for the RESET operations.

After setting the device in the LRS, a train of 500 RESET pulses was subsequently applied. As the goal of the application of this train of pulses is the modulation of the resistive state of the device, the amplitudes of the pulses were significantly lower than those corresponding to a DC RESET operation. The top electrode was grounded and positive pulses (V_RESET) were applied to the bottom electrode. The equivalent resistance of the device was obtained measuring the current after every RESET pulse at a read voltage of 0.1 V, a value low enough not to impact the resistance state of the device. Figure 4a shows the evolution of device resistance at different pulse amplitude values while keeping the pulse width constant at 100 μs. It is observed that the higher the pulse amplitude, the lower the number of pulses needed to reach a certain resistance value. Furthermore, intermediate resistance states were reached as pulses were applied. A few pulses were only required to induce a HRS when V_RESET = 0.8V. In fact, in this particular case, the train of pulses was stopped when the equivalent resistance of the device was higher than 100 kΩ. Similar behavior was obtained when exponentially varying the pulse width while keeping the RESET pulse amplitude (V_RESET) constant (0.6 V), as shown in Figure 4b. Notice that wider pulses lowered the number of pulses needed to reach a specific resistance value. These results are in agreement with previous works [25,26]. However, variability in the intermediate resistance values was observed when trains of RESET pulses were applied to a device departing from the LRS. In Figure 5a, a train of 200 RESET pulses was applied 100 times to the same device. The resistance values show variability after applying each train of pulses. This fact is clearly shown in Figure 5b, where the cumulative probability plot for the resistance of the device is extracted from the results in Figure 5a at the end of every round, i.e., once the train of 200 RESET pulses was applied. The results of Figure 4a and Figure 5a were obtained from two different RRAMs, where a slight device-to-device variability can take place.

Another experiment was conducted to observe the variability in the number of pulses required to drive the device to a threshold resistance of 5000 Ω. The experiment was repeated 43,000 times and the results are shown in Figure 6a. The results show that the number of pulses to reach the threshold resistance is random, although the distribution is not uniform. This fact is observed in the cumulative probability distribution of the number of pulses to drive the device to the threshold resistance, see Figure 6b. Anyway, the variability in the number of pulses is worthy to be taken as a source of randomness.

4. Random Number Generator Proposal

The proposed TRNG extracts random bits from the number of RESET pulses required to drive an RRAM to a specific threshold resistance. Figure 7a shows the schematic of the RRAM-based TRNG, which consists of a voltage divider, the RRAM in series with a resistor (R_f = 500 Ω), and a comparator working with V_ref. Initially, the device is in the LRS and the counter is set to 0. When the positive voltage pulse (V_pulse) is applied to the bottom terminal of the RRAM (RESET pulse), the voltage divider scales down V_pulse to the voltage at the top electrode terminal (input V- of the comparator), see Figure 7b. As the train of RESET pulses proceeds, the RRAM resistance increases, thus decreasing V_-. This voltage is compared to V_ref, which is selected according to the threshold resistance and R_f, so that it is used to evaluate whether the device has reached the selected threshold resistance value. When the device resistance is low enough, V_- becomes larger than V_ref and the comparator produces trains of “0/1”, which are counted by the edge-triggered counter. Once the RRAM resistance reaches the threshold value, V_- becomes lower than V_ref, and the counter does not count any more pulses. The number of pulses saved in the counter is variable and unpredictable.

An equivalent experiment was conducted and repeated about 20,000 times. According to the observed maximum number of pulses required by the target device to reach the threshold resistance, a 9-bit counter was considered, corresponding then to a maximum of 2⁹ − 1 = 511 RESET pulses to be applied. Therefore, nine bitstreams (B0–B8) coming from the outputs of the counter were recorded synchronously, each of them including near 20,000 values. The applied pulses (V_pulse) were 1.4 V in amplitude and 100 μs in width and the threshold resistance value was 2000 Ω. Notice that the voltage drop across the RRAM is lower than 1.4 V due to the serial resistor (R_f). A nominal RESET and SET pulse were applied between every train of pulses to initialize the device again into the LRS. Although a low throughput was achieved, due to the limitations of the experimental set-up, it would be readily improved by means of a circuit able to apply shorter pulses.

To assess the performance of the proposal, the National Institute of Standards and Technology randomness tests (NIST SP800-22) were used to evaluate the stochasticity of the bitstreams [27]. For each test, a probability value (P-value) was returned and compared to the significance level to check whether the bitstream was random. A specific test was passed only when the resulting P-value was larger than the significance level (0.01), otherwise it failed. According to the length of the bitstreams, a total of 9 out of the 15 tests were performed in all the raw bitstreams without any post-processing. The 6 remaining tests could not be performed due to the length of the bitstreams. The four least significant bits passed all the applied tests and the remaining ones only passed some of them, as indicated in Figure 8a. The detailed results of the B0-B3 bits, which passed all the tests, are shown in

Table 1. NIST SP800-22 test results for bits B0-B3. A specific test was passed when the P-value was larger than the significance level (0.01).

Test	B0	B1	B2	B3
	P-value	P-value	P-value	P-value
Frequency	0.82340	0.87983	0.05831	0.57935
Block frequency	0.03699	0.63301	0.09892	0.23719
Runs	0.45817	0.78983	0.10153	0.69051
Longest run of ones	0.46035	0.76249	0.96569	0.72316
Spectral DFT	0.16787	0.59143	0.39501	0.06316
Non-overlapping template a	0.53067	0.47208	0.47176	0.50414
Serial 1	0.06643	0.47075	0.03791	0.67948
Serial 2	0.11829	0.71713	0.29277	0.80299
Approximate entropy	0.08384	0.28695	0.18705	0.23089
Cumulative sum (forward)	0.94112	0.58962	0.01683	0.60898
Cumulative sum (reverse)	0.76293	0.72926	0.05127	0.23647

^a An average P-value is adopted for the Non-Overlapping template test.

. The accomplished 9 tests proved the quality and non-replicability of the proposed TRNG. Moreover, the inter-Hamming distances among the lowest bitstreams (B0–B3) were evaluated, see Figure 8b. They are close to the ideal 50% value, indicating their high independence level. A further comparison with existing RRAM-based TRNGs can be found in

Table 2. Comparative analysis of RRAM-based TRNGs.

Work	Entropy Source	# of RRAMs	RRAM Integration	Extra Circuitry	# of Random Bits	NIST Passed	Post-Processing
[14]	Switching delay	1	Single cell	Comparator, AND and counter	6	15/15	No
[15]	Probabilistic switching	1	1T-1R (7 × 7 array)	Comparator	1	11/15	No
[16]	Inter-device variability	2	2 Mbit array	Comparator	1	10/10	XOR
[17]	Switching delay	2	Single cell	Comparator	1	9/15	Von Neumann
[18]	Inter- and intra-device switching variability.	2	1 × 2 array	Comparator	1	12/15	Von Neumann
[19]	RRAM switching current	1	7 × 7 array	Comparator	1	12/15	XOR
[20]	RTN	1	Single cell	Comparator and D Flip-flop	1	5/15	No
[21]	RTN and intra-device switching variability	1	1T-1R (Simulation)	Ring oscillator and D Flip-flop.	1	12/12	No
[22]	RTN	2	Single cell	Comparator and DAC	1	15/15	Von Neumann
This work	Intra-device RESET switching variability	1	Single cell	Comparator and counter	4	9/9	No

. The column referred as “NIST passed” reports the number of passed tests related to the number of applied tests. In some cases, it was not possible to apply all the NIST tests (15). According to the results, the presented proposal is competitive, since it is able to generate multiple random bits based on a simple circuit with no need for post-processing. The proposed TRNG passed all the applied NIST tests, although some of them could not be applied due to the length of the bitstream, in a similar way as in other works reported in Table 2.

5. Conclusions

It has been experimentally demonstrated that an RRAM can be exploited as a source for the generation of random numbers by applying trains of RESET pulses. The resistive switching behavior of the RRAM was characterized by varying the amplitude and width of the pulses. Variability was found in the number of RESET pulses required to drive the RRAM to a certain resistance value. An RRAM-based TRNG was further proposed to obtain random bits simultaneously. Experimental measurements were conducted and four of the bitstreams successfully passed all the tests without need for further post-processing, demonstrating the validity of the proposal.