ARINC653 Channel Robustness Verification Using LeonViP-MC, a LEON4 Multicore Virtual Platform
Abstract
:1. Introduction
1.1. Motivation
1.2. Related Works
1.2.1. Multicore Simulation Techniques
1.2.2. LLVM as a Simulation Support Tool
1.3. Paper Contribution
2. Multicore Virtual Platform
2.1. Base Single-Core Virtual Platform
Cycle Accuracy
- Static cycle counting—The simulator assigns, for each instruction, the number of cycles it consumes nominally according to the LEON4 processor specification;
- Dynamic cycle counting—The LEON4 specification details those cases where having two specific instructions executed one after the other causes execution delays. These delays can be caused by data hazards or by the intrinsic nature of the instructions. During instruction execution, the simulator temporarily stores the data needed to calculate this delay effectively.
- Peripheral access cycle counting—When an instruction needs to access data or other resources beyond the processor cache, accessing the AHB bus may cause a delay in execution. This delay may be caused by the intrinsic speed of the peripheral and/or because another core is using the bus in the multicore scenario. Since this delay is pseudo-random in real hardware, we estimate the average cycles per access based on empirical tests performed on the real GR740 platform.
2.2. Multicore Simulation
2.2.1. Multicore Simulation with Threads
2.2.2. Multicore Simulation with LLVM and Coroutines
2.3. Fault-Tolerance Campaign Testing Mechanisms
3. Use Case: ARINC653 Message Channel Robustness Verification
- The verification of the BSW boot process asks for the possibility of the corruption of application binaries stored in the EEPROM or permanent faults in the SDRAM application deployment areas. First of all, the injection of permanent faults in real hardware is not technically achievable in a non-intrusive manner. Secondly, in order to carry out an exhaustive verification, each memory location of EEPROM and SDRAM areas must be individually corrupted and BSW behavior tested. This leads to a very huge amount of BSW runs. Although each just takes a few seconds, completing the entire test would take months running in a single machine. The use of virtual platforms allows the injection of permanent errors and can significantly reduce the verification time spent since several instances of the Virtual Platform can be run in parallel on different real machines, thus shortening the overall testing time [30].
- Although BSW is not deployed in the SDRAM, but is executed directly in the PROM to increase its reliability, it still uses SDRAM to map the program stack and global variables. In order to avoid the malfunction of the BSW itself due to SDRAM permanent faults, stack and runtime variables must not be statically allocated. Therefore, during system startup, an error-free memory area is searched for and used for nominal boot as is described in [32].
- The BSW is a criticality category B software, which cannot be replaced during the mission, so testing this kind of critical software must cover 100% of the source code statement and decision paths. Coverage is a major concern for dependability because parts of the code that are never executed during a test workload run cannot be properly verified. So, the efficient coverage of an exception handling code is an essential concern. Regarding BSW, the developed framework and figures are described in [7].
3.1. System under Test
3.2. Channel Buffer Provisioning Approach
3.3. Fault Injection Campaign
3.4. Results
4. Conclusions
Author Contributions
Funding
Conflicts of Interest
References
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Thread Approach | LLVM First Execution | LLVM with Cached Coroutines | |
---|---|---|---|
smpschededf01 (single-core) | 0.57 MIPS | 2.745 MIPS | 5.052 MIPS |
smpmigration01 (dual-core) | 0.791 MIPS | 4.261 MIPS | 4.862 MIPS |
smpatomic01 (quad-core) | 0.804 MIPS | 6.263 MIPS | 6.691 MIPS |
smpaffinity01 (quad-core) | 1.303 MIPS | 1.179 MIPS | 9.457 MIPS |
ARINC653 use case (quad-core) | 0.576 MIPS | 0.062 MIPS | 4.31 MIPS |
k | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | Total |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Faulty configurations | 12 | 66 | 220 | 495 | 792 | 924 | 792 | 495 | 220 | 66 | 12 | 1 | 4095 |
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Sánchez, J.; da Silva, A.; Parra, P.; R. Polo, Ó.; Martínez Hellín, A.; Sánchez, S. ARINC653 Channel Robustness Verification Using LeonViP-MC, a LEON4 Multicore Virtual Platform. Electronics 2021, 10, 1179. https://doi.org/10.3390/electronics10101179
Sánchez J, da Silva A, Parra P, R. Polo Ó, Martínez Hellín A, Sánchez S. ARINC653 Channel Robustness Verification Using LeonViP-MC, a LEON4 Multicore Virtual Platform. Electronics. 2021; 10(10):1179. https://doi.org/10.3390/electronics10101179
Chicago/Turabian StyleSánchez, Jonatan, Antonio da Silva, Pablo Parra, Óscar R. Polo, Agustín Martínez Hellín, and Sebastián Sánchez. 2021. "ARINC653 Channel Robustness Verification Using LeonViP-MC, a LEON4 Multicore Virtual Platform" Electronics 10, no. 10: 1179. https://doi.org/10.3390/electronics10101179