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J. Low Power Electron. Appl. 2018, 8(4), 41;

A Novel Approach to Design SRAM Cells for Low Leakage and Improved Stability

Department of Electronics and Communications Engineering, Inderprastha Engineering College, Ghaziabad 201010, India
GLA University, Mathura 281406, India
Department of Electronics and Communication Engineering, ABES Engineering College, Ghaziabad 201009, India
Author to whom correspondence should be addressed.
Received: 8 September 2018 / Revised: 9 October 2018 / Accepted: 12 October 2018 / Published: 24 October 2018
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The semiconductor electronic industry is advancing at a very fast pace. The size of portable and handheld devices are shrinking day by day and the demand for longer battery backup is also increasing. With these requirements, the leakage power in stand-by mode becomes a critical concern for researchers. In most of these devices, memory is an integral part and its size also scales down as the device size is reduced. So, low power and high speed memory design is a prime concern. Another crucial factor is the stability of static random-access memory (SRAM) cells. This paper combines multi threshold and fingering techniques to propose a modified 6T SRAM cell which has high speed, improved stability and low leakage current in stand-by mode of the memory cell. The simulations are done using the Cadence Virtuoso tool on UMC 55 nm technology. View Full-Text
Keywords: CMOS technology; SRAM; MTCMOS; fingering; leakage current; SNM CMOS technology; SRAM; MTCMOS; fingering; leakage current; SNM

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Tripathi, T.; Chauhan, D.S.; Singh, S.K. A Novel Approach to Design SRAM Cells for Low Leakage and Improved Stability. J. Low Power Electron. Appl. 2018, 8, 41.

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J. Low Power Electron. Appl. EISSN 2079-9268 Published by MDPI AG, Basel, Switzerland RSS E-Mail Table of Contents Alert
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