# Design of Energy Aware Adder Circuits Considering Random Intra-Die Process Variations

^{*}

## Abstract

**:**

## 1. Introduction

_{max}) and maximum power consumption (P

_{max}), and thus, to improve the parametric yield.

## 2. Adder Circuits and Nominal Performances

_{2}n inverting AND-OR delays [11]. The carry look-ahead (CLA) adder exploits a sparse carry tree that roughly doubles the delay (actually 2(log

_{2}n – 1)) in the carry tree, relative to the fast_CLA but it provides significant area savings [11]. The carry select adder (CSA) is also a high-performance circuit. However, by increasing the adder size, the growing loading on the carry-select lines can degrade performance below the expected level. The carry look-ahead/select adder (CLSA) is by far the most flexible architecture (by specifying this kind of architecture MC automatically creates a structure ranging from a Ripple to a fast_CLA adder, depending on the desired delay [11]).

_{op}), evaluated over 200 input patterns. The latter were randomly provided at a running frequency of 166 MHz. From Figure 2, it is easy to observe that the Ripple circuit exhibits energy consumption significantly lower than the remaining counterparts (i.e., up to 56%, 62%, 81% and 83% less than the CLA, CSA, fast_CLA and CLSA, respectively), proving to be the most suitable choice when low power consumption is mandatory. In contrast, the fastest adders (i.e., the fast_CLA and CLSA) are the most energy hungry architectures, thus useful only when speed is the primary concern.

## 3. Impact of Intra-Die Process Variability for Different Power Supply Voltages

## 4. Timing Yield Issues and Design Guidelines for Energy-Aware Adder Circuits

## 5. Conclusions

Adder Type | Description | Area | Delay |
---|---|---|---|

Ripple | ripple carry adder | O(n) | O(n) |

Fast_CLA | fast carry look-ahead adder | O(nlog_{2} n) | O(log_{2} n) |

CLA | carry look-ahead adder | O(n) | O(log_{2} n) |

CSA | carry select adder | O(n) | O(√n) |

CLSA | carry look-ahead/select adder | Variable (Ripple ≥ fast_CLA) | Variable (Ripple ≥ fast_CLA) |

## References

- Wong, B.; Zach, F.; Moroz, V.; Mittal, A.; Starr, G.; Kahng, A. Nano-CMOS Design for Manufacturability; John Wiley & Sons: Hoboken, NJ, USA, 2009. [Google Scholar]
- Sylvester, D.; Agarwal, K.; Shah, S. Variability in nanometer CMOS: Impact, analysis, and minimization. Integration
**2008**, 41, 319–339. [Google Scholar] - Borkar, S.; Karnik, T.; Narendra, S.; Tschanz, J.; Keshavarzi, A.; De, V. Parameter variations and impact on circuits and microarchitecture. Proceedings of the 40th Conference on Design Automation, Anaheim, CA, USA; June 2003. [Google Scholar]
- Chen, T.; Naffziger, S. Comparison of Adaptive Body Bias (ABB) and Adaptive Supply Voltage (ASV) for Improving Delay and Leakage under the Presence of Process Variation. IEEE Trans. Very Large Scale Integr. VLSI Syst.
**2003**, 11, 888–899. [Google Scholar] - Tschanz, J.; Kao, J.; Narendra, S.; Nair, R.; Antoniadis, D.; Chandrakasan, A.; De, V. Adaptive body bias for reducing impacts of die-to-die and within-die parameter variations on microprocessor frequency and leakage. IEEE J. Solid-State Circuit
**2002**, 37, 422–423. [Google Scholar] - Wei, G.-Y.; Horowitz, M. A fully digital, energy-efficient, adaptive power-supply regulator. IEEE J. Solid-State Circuits
**1999**, 34, 520–528. [Google Scholar] - Kim, J.; Horowitz, R. An efficient digital sliding controller for adaptive power supply regulation. IEEE J. Solid-State Circuits
**2002**, 37, 639–647. [Google Scholar] - Rabaey, J.; Chandrakasan, A.; Nikolic, B. Digital Integrated Circuits: A Design Perspective; Prentice Hall: Englewood Cliffs, NJ, USA, 2003. [Google Scholar]
- Nagendra, C.; Irwin, M.; Owens, R. Area-time-power tradeoffs in parallel adders. IEEE Trans. Circuits Syst. II
**1996**, 43, 689–702. [Google Scholar] - Parhami, B. Computer Arithmetic: Algorithms and Hardware Designs; Oxford University Press: New York, NY, USA, 2000. [Google Scholar]
- Synopsys Documentation. Available online: http://www.synopsys.com/home.aspx (accessed on 28 March 2011).
- Srivastava, A.; Kachru, T.; Sylvester, D. Low-Power-Design Space Exploration Considering Process Variation Using Robust Optimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
**2007**, 26, 67–79. [Google Scholar]

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**MDPI and ACS Style**

Lanuzza, M.; Frustaci, F.; Perri, S.; Corsonello, P.
Design of Energy Aware Adder Circuits Considering Random Intra-Die Process Variations. *J. Low Power Electron. Appl.* **2011**, *1*, 97-108.
https://doi.org/10.3390/jlpea1010097

**AMA Style**

Lanuzza M, Frustaci F, Perri S, Corsonello P.
Design of Energy Aware Adder Circuits Considering Random Intra-Die Process Variations. *Journal of Low Power Electronics and Applications*. 2011; 1(1):97-108.
https://doi.org/10.3390/jlpea1010097

**Chicago/Turabian Style**

Lanuzza, Marco, Fabio Frustaci, Stefania Perri, and Pasquale Corsonello.
2011. "Design of Energy Aware Adder Circuits Considering Random Intra-Die Process Variations" *Journal of Low Power Electronics and Applications* 1, no. 1: 97-108.
https://doi.org/10.3390/jlpea1010097