Read Operation Mechanism of Feedback Field-Effect Transistors with Quasi-Nonvolatile Memory States

Abstract

In this study, the read operation of feedback field-effect transistors (FBFETs) with quasi-nonvolatile memory states was analyzed using a device simulator. For FBFETs, write pulses of 40 ns formed potential barriers in their channels, and charge carriers were accumulated (depleted) in these channels, generating the memory state “State 1 (State 0)”. Read pulses of 40 ns read these states with a retention time of 3 s, and the potential barrier formation and carrier accumulation were influenced by these read pulses. The potential barriers were analyzed, using junction voltage and current density to explore the memory states. Moreover, FBFETs exhibited nondestructive readout characteristics during the read operation, which depended on the read voltage and pulse width.

1. Introduction

Quasi-nonvolatile memory has been developed as a novel memory technology. Its retention time ranges from 64 ms to 10 years, which is the gap between volatile and nonvolatile memories [1]. The ability to store data without a power supply reduces power consumption [2,3]. This type of memory addresses the timescale gap in the memory hierarchy. Traditional memory has evolved to satisfy the demands of high-performance computing [4,5]. Volatile memory, such as static or dynamic random-access memory, offers an ultrahigh speed with a limited retention time [6,7,8]. Nonvolatile memory, such as NAND flash memory, provides a retention time of 10 years but exhibits a low operation speed [6,9]. With the current data-centric trend, a timescale gap in the memory hierarchy worsens memory bottlenecks [10,11]. Recent studies have demonstrated the potential of quasi-nonvolatile memory; however, improvements are still required [12,13]. To replace traditional memory successfully, the new memory must possess unlimited write/read cycles. Feedback field-effect transistors (FBFETs) have emerged as attractive candidates for quasi-nonvolatile memory owing to their fast write/read speeds, long retention times, and nondestructive readout characteristics [3]. Furthermore, their inherent operating mechanism ensures high endurance, and their compatibility with complementary metal–oxide–semiconductor (CMOS) technology indicates that they can potentially replace traditional memory fully [3,14].

In FBFETs, the positive feedback mechanism enables quasi-nonvolatile memory operations. Their memory states are defined by the presence (State 1) and absence (State 0) of excess charge carriers in the channels. When the potential barriers collapse (form) abruptly due to the accumulation (depletion) of excess charge carriers, the positive feedback loop is activated (eliminated) in their channels, and their memory state becomes State 1 (State 0) [15,16]. Consequently, State 1 (State 0) is perceived by reading the high (low) current. The speed and pulse configuration of the reading influence the formation of the potential barrier [17,18,19]; thus, the readout characteristics depend on the read pulse. Understanding the read mechanism is crucial for further enhancing quasi-nonvolatile characteristics. In this study, the read operation of FBFETs with quasi-nonvolatile memory states was analyzed using technology computer-aided design (TCAD) simulation. The read operation of the FBFETs was newly interpreted via the analysis of a positive feedback mechanism at a nanosecond-order speed. Junction voltage and current density analysis were employed to examine the carrier type predominantly influencing the formation of the positive feedback loop and the role of channel potential barriers during the read operation. This study provides valuable insight into optimizing the FBFET design for performance enhancement and suggests the potential for achieving ultra-high-speed operation through a new reading scheme.

2. Results and Discussions

Figure 1a shows a schematic of a representative FBFET with a p-n-p-n structure. The dimensional parameters were a gated channel length (L_G) of 50 nm, a nongated channel length (L_NG) of 50 nm, a channel thickness (t_Si) of 20 nm, and a gate oxide SiO₂ thickness (t_ox) of 5 nm. The doping concentrations were 3 × 10¹⁹ cm⁻³ for the source and drain regions and 5 × 10¹⁸ cm⁻³ for the gated and nongated channel regions. The gate, drain, and source electrodes were made of aluminum (work function = 4.0 eV). These parameters are summarized in

Table 1. Dimensional parameters and doping concentrations for simulations.

Simulation Parameters	Value (Unit)
Drain/source doping concentration	3 × 1019 (cm−3)
Gated/nongated channel doing concentration	5 × 1018 (cm−3)
Gated channel length (LG)	50 (nm)
Nongated channel length (LNG)	50 (nm)
Channel thickness (tSi)	20 (nm)
Gate oxide thickness (tox)	5 (nm)
Work function of gate, drain, and source electrodes	4.0 (eV)

. Figure 1b shows a schematic of a V_DS pulse (with V_GS = 0 V) for reading quasi-nonvolatile memory states. During the read operation, V_DS increased to the reading voltage (V_Read) within the rising time (T_rise) and fell to 0 V during the falling time (T_fall), the T_fall value was the same as the T_rise value. Memory states were verified by measuring the drain-to-source current (I_DS) during the reading time (T_Read). The quasi-nonvolatile memory operation is depicted in Figure 1c, where the T_rise and T_Read values were 10 and 20 ns, respectively. The sequence Write 1-Read-Write 0-Read was performed to verify the memory states. After the write operation, the I_DS values were ~12 μA and 3.8 pA for States 1 and 0, respectively. Moreover, the retention time was 3 s, as observed in the full memory cycle (Figure 1d).

Figure 2 shows the output characteristics (a) and band diagram (b) of the FBFETs. For the T_rise values of 1, 10⁻³, and 10⁻⁸ s, the FBFETs exhibited bistable characteristics (in the forward and reverse drain-to-source voltage (V_DS) sweeps) caused by the positive feedback loop associated with the potential barrier and carrier accumulation in the channel. A positive feedback loop was activated when the repeated accumulation of excess carriers collapsed the potential barrier in the channel. For a T_rise of 1 s, the I_DS abruptly increased at a V_DS of 1.47 V in the sweep of V_DS from 0 to 2.0 V, which was the latch-up phenomenon. For a T_rise shorter than 1 s, the formation of the potential barrier was hindered sufficiently to block the carrier flow; for a T_rise of 10⁻⁸ s, the potential barrier in the gated channel decreased as V_DS increased (Figure 2b). Consequently, the latch-up voltage decreased from 1.47 to 1.26 V and the transient leakage current increased from ~10⁻¹⁶ to ~10⁻⁹ A as T_rise decreased from 1 to 10⁻⁸ s.

The formation of the potential barrier affects each p-n junction of the FBFETs during the read operation. As shown in Figure 3a, the junction voltages (V₁, V₂, and V₃) are defined as the differences between the electron and hole quasi-Fermi levels (E_FN and E_FP, respectively). Note that the positive V₂ was the reverse bias to the center junction; the equation V_Read = V₁ + V₂ + V₃ was established before the latch-up [20]. The junction voltages indicated the potential barrier heights of the channels. The accumulation (depletion) of charge carriers in the channels generated a memory state: State 1 (State 0). The accumulation and depletion of charge carriers are described in detail in the supplementary information. The potential barrier in the gated channel was higher by 0.4 eV in State 0 than in State 1 (Figure 3b). Thus, at V_Read = 0 V, the initial values of V₁ and V₂ differed by 0.40 V between States 1 and 0, which corresponded to the difference in the potential barrier in the gated channel. As V_Read w\s swept for a T_rise of 10 ns (Figure 3c), V₁ and V₂ sustained the difference between States 1 and 0 during the V_Read sweep, whereas V₃ was the same for States 1 and 0 before latch-up. The sustained potential barrier induced a difference between States 1 and 0. As V_Read reached 1.05 V, V₁ and V₃ increased, and V₂ decreased abruptly in State 1. These results indicate that the potential barrier collapsed at 1.05 V in State 1 but not in State 0. V₁ accounted for most of V_Read in both states. An increase in V₁ signified an increase in the forward bias applied to the drain-side p-n junction. Therefore, the collapse of the channel potential barrier in State 1 arose from the unintended carrier flow at the drain-side p-n junction.

When a positive V_DS was applied to the FBFETs, electrons flowed toward the drain, whereas holes flowed toward the source. Some electrons injected from the source accumulated in the potential well, whereas the rest passed through the channel. Thus, the electron current density (J_n) at the drain-side p-n junction represents the electrons that pass through, which are related to the increase in the V₁ value. In contrast, the hole current density (J_p) at the drain-side p-n junction refers to hole injection from the drain. The number of injected holes is equal to the sum of the numbers of holes that are accumulated, recombined (or generated), and passed through. J_n and J_p at the drain-side p-n junction are plotted as functions of V_DS in Figure 4. For a T_rise of 10 ns, as V_Read increased to 2.00 V, J_n instantly increased in State 1, whereas it remained at 10⁻¹¹ A/cm in State 0 until a V_Read of 0.42 V (Figure 4a). However, J_p remained at ~10² A/cm before the latch-up in both memory states (Figure 4b). As J_n reached the same magnitude as J_p (~10² A/cm), J_p increased and eventually led to a latch-up; the increase in J_n induced the collapse of the channel potential barrier. As the J_n curve in State 0 was shifted rightward by 0.42 V compared with State 1, the latch-up phenomenon occurred at V_Read = 1.05 V for State 1, whereas it did not for State 0. The results showed that the flow of electrons in the channel influenced the activation of the positive feedback loop. In State 0, the higher potential barrier in the gated channel inhibited the flow of electrons, resulting in a difference from State 1.

Figure 5 shows the I_DS response to the read operation for various V_Read values in States 1 and 0 with a T_rise of 10 ns. The I_DS value indicates the memory state during T_Read. Accordingly, the moderate V_Read range depends on the selection of T_Read. For T_Read = 20 ns, marked with dotted lines in the figure, States 1 and 0 exhibited distinct I_DS results during the read operation. As shown in Figure 5a, as V_Read decreased to 0.90 V, the positive feedback loop activation was delayed in State 1. However, even if V_Read was less than the latch-up voltage, the positive feedback loop was activated in State 1. In Figure 5b, for State 0, the I_DS values stabilized at ~10⁻¹⁶ A over time. The carrier flows were hindered by the potential barrier in State 0 during V_Read; thus, the FBFETs exhibited nondestructive readout characteristics.

An investigation of the read operation is necessary to improve the reading speed of quasi-nonvolatile memory states. The memory window, namely, the V_Read range for recognizing memory states, is not exclusively defined by the DC characteristics of the FBFETs. At nanosecond-order speeds, the flow of charge carriers in the channel influences the activation of a positive feedback loop. To enhance the current-sensing margin, the reinforcement of the gated channel barrier is required to suppress the carriers passing through and reduce the leakage current. In State 1, charge carriers are accumulated in the gated channel after the read operation, which reduces the activation time of the positive feedback loop for the subsequent read operation. In State 0, owing to the high-potential barrier, charge carriers remain depleted in the gated channel after the read operation (for more details, see the Supplementary Information). The nondestructive readout characteristics enable stable and recursive read operations [21]. Therefore, incorporating the initialized operation into the read pulse scheme allows FBFETs to operate at an SRAM-like speed (sub-1 ns). Moreover, applying a flexible pulse scheme during repetitive read operations can improve the performance of FBFETs. Consequently, a suitable tool can be designed for a specific purpose through an in-depth understanding of the reading operation of FBFETs.

3. Conclusions

The read operations of FBFETs were investigated with quasi-nonvolatile memory states. FBFETs exhibited a retention time of 3 s for write and read pulses of 40 ns. State 1 (State 0) was generated by the accumulation (depletion) of charge carriers in the channels. During the rise in V_Read at a T_rise of 10 ns, the increase in electron flow at the drain-side p-n junction affected the activation of the positive feedback loop in the channel. In State 1, as J_n reached the same magnitude as J_p (~10² A/cm), the potential barrier collapsed at a V_Read of 1.05 V, which caused a latch-up. In State 0, the high-potential barrier in the gated channel inhibited the flow of electrons, which differed from State 1. Consequently, the read operation was distinguishable for States 1 and 0 with nondestructive characteristics. Moreover, the range of V_Read depended on the pulse width during the read operation. The results provided insights for improving the performance of FBFETs as quasi-nonvolatile memory devices.

4. Simulation Method

The simulation was performed with a two-dimensional structure using the commercial device simulator Synopsys Sentaurus (O_2018.06) [22]. The Lombardi, Philips unified mobility, and high-field saturation models were used to consider the doping and field dependencies of carrier mobility. The Fermi statistics were used to perform an accurate simulation. Also, bandgap narrowing (Slotboom model), band-to-band tunneling, Shockley–Read–Hall (SRH) recombination with concentration-dependent lifetimes, surface SRH recombination, and Auger recombination were considered. Furthermore, an area factor of 20 nm was specified in the simulation to determine the device width.