Novel Modeling Approach to Analyze Threshold Voltage Variability in Short Gate-Length (15–22 nm) Nanowire FETs with Various Channel Diameters

Abstract

In this study, threshold voltage (V_th) variability was investigated in silicon nanowire field-effect transistors (SNWFETs) with short gate-lengths of 15–22 nm and various channel diameters (D_NW) of 7, 9, and 12 nm. Linear slope and nonzero y-intercept were observed in a Pelgrom plot of the standard deviation of V_th (σV_th), which originated from random and process variations. Interestingly, the slope and y-intercept differed for each D_NW, and σV_th was the smallest at a median D_NW of 9 nm. To analyze the observed D_NW tendency of σV_th, a novel modeling approach based on the error propagation law was proposed. The contribution of gate-metal work function, channel dopant concentration (N_ch), and D_NW variations (WFV, ∆N_ch, and ∆D_NW) to σV_th were evaluated by directly fitting the developed model to measured σV_th. As a result, WFV induced by metal gate granularity increased as channel area increases, and the slope of WFV in Pelgrom plot is similar to that of σV_th. As D_NW decreased, SNWFETs became robust to ∆N_ch but vulnerable to ∆D_NW. Consequently, the contribution of ∆D_NW, WFV, and ∆N_ch is dominant at D_NW of 7 nm, 9 nm, and 12, respectively. The proposed model enables the quantifying of the contribution of various variation sources of V_th variation, and it is applicable to all SNWFETs with various L_G and D_NW.

1. Introduction

Gate-all-around (GAA) silicon nanowire field-effect transistors (SNWFETs) are considered as a viable option for future device architecture due to their adequate gate-controllability with GAA structures [1,2,3]. However, ultrascaled SNWFETs suffer from severe threshold voltage (V_th) variation because the device-to-device variation increases with the decrease in the effective channel width (W_eff) and gate-length (L_G) [4,5]. According to previous studies, random variations such as metal gate granularity (MGG), line edge roughness (LER), and random dopant fluctuation (RDF) cause V_th variation in ultrascaled GAA transistors [6,7,8,9,10]. Additionally, the V_th variation is also induced by the process variations such as junction gradient and channel thickness variation [11,12,13,14,15,16,17].

Therefore, several simulations and models have been recommended to analyze the contribution of multiple sources to V_th variation. First, technology computer-aided design (TCAD) simulations are suitable for analyzing the influence of variation sources, but it is difficult to predict the cause of variation inversely from measured V_th variation [6,7,8,9,10]. Second, simulation program with integrated circuit emphasis (SPICE)-based models can be applied to analyze the variation sources of measured V_th variation, but it consumes time and makes an error because all devices should be calibrated [15]. Last, models based on the error propagation law have been proposed [16,17]. These modeling approaches enable extraction of the contribution of each variation source to the standard deviation of V_th (σV_th) fast and accurately because they directly model σV_th. However, the error propagation law-based model to analyze the V_th variability of SNWFET has not been suggested.

Previously, V_th variability in SNWFETs was investigated considering various L_G using a SPICE-based model [15]. However, the study did not consider the effect of channel dopant concentration (N_ch) variation and nanowire diameter (D_NW) change. Furthermore, although D_NW influences W_eff, electrostatics, and quantum effect [18], the D_NW tendency of V_th variability in SNWFET with short L_G has not been thoroughly investigated.

Therefore, in this study, we quantitatively analyzed the sources of V_th variation in SNWFETs with short L_G (15–22 nm) and multiple D_NW (7, 9, 12 nm). A novel modeling approach based on the error propagation law is proposed to estimate the contribution of multiple variation sources to the V_th variability. The dominant variation source of V_th variation is analyzed for each D_NW by using the proposed model. Additionally, the standard deviation of N_ch (σN_ch) and D_NW (σD_NW) according to L_G is presented.

2. Device Structure and Modeling Methods

2.1. Structure and Possible V_th Variation Sources of SNWFETs

Figure 1 depicts the schematic and V_th variation sources of SNWFETs, fabricated using the same process flow reported in [19,20]. The SNWFETs adopted Mid-gap TiN metal gate, gate oxide thickness (t_ox) of 3.4 nm, and (110) channel direction. The gate and nanowire trimming process was used to obtain L_G varying from 15 to 22 nm and D_NW of 7, 9, and 12 nm. In this process, D_NW variation (∆D_NW) was caused by LER occurred at the nanowire (NW) edges and under- or over-etching of the NW [21]. MGG occurred in the TiN metal gate and generated the metal work function variation (WFV) [22]. The transmission electron microscope (TEM) image shows many grain boundaries exist in the TiN metal gate of the SNWFETs [19]. Although the SNWFET is fabricated with an undoped channel, the source/drain (S/D) dopants diffuse into the channel with short L_G [18,23]. Consequently, N_ch variation (∆N_ch) was caused by RDF, the S/D dopant implant, annealing, and SiGe strain variation [8,9,10].

Figure 2a depicts the I_D–V_G characteristics of SNWFETs with L_G = 15 nm and D_NW = 7 nm at a drain bias of 0.05 V. About 50 samples were measured per device condition. Here, V_th was extracted at I_D = 10⁻⁷ × πD_NW/L_G using the constant current method. The fluctuation of extracted V_th shows the process and random variation affect the physical characteristics of SNWFETs. Figure 2b illustrates a quantile plot of V_th for each D_NW in SNWFETs with an L_G of 15 nm, which shows the distribution of V_th. The distribution of V_th predominantly follows the theoretical normal distribution for all device conditions, which indicates that sufficient V_th values were obtained to analyze σV_th.

Figure 3 is the Pelgrom plot of σV_th in SNWFETs for each D_NW, showing the trend of σV_th as channel area changes. The slope of the Pelgrom plot, defined as the Pelgrom coefficient (A_vt), represents the effect of random variation [4]. The y-intercept of the Pelgrom plot is also observed, indicating the effect of the process variation and short channel effect [12,24]. Remarkably, the values of A_vt and y-intercepts differed for each D_NW, and the σV_th is smallest in median D_NW of 9 nm. We anticipated that this result implies a trade-off relationship between the various variation sources. Hence, a novel modeling approach is proposed to analyze the contribution of each variation source to σV_th.

2.2. Proposed σV_th Model of SNWFETs

Figure 4 shows the proposed modeling flow to analyze the contribution of WFV, ∆N_ch, and ∆D_NW to σV_th. To model σV_th, we started from a physical model for V_th of SNWFET, as follows [25,26]:

$$V_{\mathrm{th}}={\Phi }_{\mathrm{M}}-{\Phi }_{\mathrm{S}}-q{N}_{\mathrm{ch}}\left(\frac{\pi r_{\mathrm{nw}}^2}{C_{\mathrm{ox}}}+\frac{r_{\mathrm{nw}}^2}{4{\epsilon }_{\mathrm{si}}}\right)+\frac{h^2}{4\pi m^{\ast }q{r}_{\mathrm{nw}}^2},$$

(1)

where Φ_M denotes the work function of the TiN gate metal; Φ_S represents the work function of silicon channel calculated as χ_si − E_g/2 + kT/q∙ln(N_ch/n_i), where χ_si is the electron affinity and E_g is the band gap of silicon; r_nw indicates the radius of NW; ${\epsilon }_{\mathrm{si}}$ and ${\epsilon }_{\mathrm{ox}}$ represent the dielectric constant of silicon and oxide, respectively; h denotes the Planck constant; and m* indicates the effective mass of an electron. C_ox represents the oxide capacitance calculated as 2πε_ox/ln(1 + t_ox/r_nw). The possible V_th variation sources in Equation (1) are Φ_M, N_ch, D_NW, and t_ox variations. Among them, t_ox is not considered because its variation and effect are very small and negligible [11,12,27]. Although the variation of effective channel length (L_eff) is not considered directly, N_ch variation partially represents L_eff variation because S/D dopant diffusion and L_G variation change N_ch and L_eff simultaneously.

Hence, considering three identical variation sources of WFV, ∆N_ch, and ∆D_NW, σV_th can be expressed based on the error propagation law as

$$\mathsf{\sigma }{V}_{\mathrm{th}}^2=\mathsf{\sigma }{\Phi }_{\mathrm{M}}{}^2+{\left(\frac{\partial V_{\mathrm{th}}}{\partial N_{\mathrm{ch}}}·\mathsf{\sigma }{N}_{\mathrm{ch}}\right)}^2+{\left(\frac{\partial V_{\mathrm{th}}}{\partial D_{\mathrm{NW}}}·\mathsf{\sigma }{D}_{\mathrm{NW}}\right)}^2.$$

(2)

To analyze σV_th using Equation (2), the sensitivity of V_th against variation sources and their standard deviation should be extracted. First, the standard deviation of metal work function (σΦ_M) can be estimated by the existing WFV model for SNWFETs, as follows [22]:

$$\mathsf{\sigma }{\Phi }_{\mathrm{M}}=RGG\times SL=\frac{G_{\mathrm{size}}}{\sqrt{L_{\mathrm{G}}\left(D_{\mathrm{NW}}+2t_{\mathrm{ox}}\right)\pi }}\times SL,$$

(3)

where RGG is the ratio of average grain size to the gate area, SL is the sensitivity of σV_th against RGG, and G_size is the grain size of the metal gate. Here, G_size can be estimated from a TEM image of the TiN metal gate of SNWFETs. SL of SNWFETs can be obtained from previous research based on TCAD simulation [22].

Second, the sensitivity of V_th against ∆N_ch and ∆D_NW can be obtained by calculating the partial differentiation of Equation (1), as follows:

$$\frac{\partial V_{\mathrm{th}}}{\partial N_{\mathrm{ch}}}=\frac{kT/q}{N_{\mathrm{ch}}}-q{r}_{\mathrm{nw}}^2\left(\frac{\ln (1+t_{\mathrm{ox}}/r_{\mathrm{nw}})}{2{\epsilon }_{\mathrm{ox}}}+\frac{1}{4{\epsilon }_{\mathrm{si}}}\right),$$

(4)

$$\frac{\partial V_{\mathrm{th}}}{\partial D_{\mathrm{NW}}}=-\frac{q{N}_{\mathrm{ch}}{r}_{\mathrm{nw}}}{2}\left(\frac{1}{{\epsilon }_{\mathrm{ox}}}\left(2\ln \left(1+\frac{t_{\mathrm{ox}}}{r_{\mathrm{nw}}}\right)-\frac{t_{\mathrm{ox}}}{t_{\mathrm{ox}}+r_{\mathrm{nw}}}\right)+\frac{1}{{\epsilon }_{\mathrm{si}}}\right)-\frac{h^2}{2\pi m^{\ast }q{r}_{\mathrm{nw}}^3},$$

(5)

where k denotes the Boltzmann constant. Here, N_ch can be extracted where Equation (1) best fits to measured V_th. Finally, σN_ch and σD_NW are extracted when Equation (2) best fits the square of the measured σV_th.

The proposed model obtains the V_th sensitivity against ∆N_ch and ∆D_NW through simple calculation and extracts the standard deviation of each variation source by fitting the model to the measured σV_th. Therefore, the contribution of multiple variation sources to σV_th can be directly and quickly modeled and analyzed using the proposed model without any TCAD or SPICE simulation. Furthermore, the proposed V_th modeling flow is expected to be applied to analyze σV_th in most multigate devices with various L_G and channel thicknesses.

3. Results and Discussion

3.1. V_th Modeling Results of SNWFETs

N_ch is extracted where Equation (1) fitted V_th versus D_NW with high accuracy in SNWFET with L_G of 15 nm, as shown in Figure 5a. Figure 5b shows N_ch increases as L_G decreases because more dopant diffused to the center of the channel from S/D even with the same S/D junction gradient. The sensitivity of V_th against ∆N_ch and ∆D_NW was calculated by substituting N_ch and other parameters in Equations (4) and (5).

3.2. V_th Standard Deviation Modeling Results of SNWFETs

3.2.1. Extraction of G_size and WFV of SNWFETs

G_size should be determined from the TEM image of the TiN metal gate of the SNWFET to analyze WFV. Figure 6a shows a schematic of the grain boundaries based on TiN metal gate TEM image [19]. G_size was measured as the average of values obtained by dividing the length of TiN metal in the TEM image (L_TEM) by the number of intersections between grain boundaries and horizontal lines (N_int), as follow [28]:

$$G_{\mathrm{size}}=\frac{{{\displaystyle \sum }}_{\mathrm{i}=1}^{N_{\mathrm{line}}}{L}_{\mathrm{TEM}}/(N_{\mathrm{int}, \mathrm{i}}+1)}{N_{\mathrm{line}}},$$

(6)

where N_line is the number of horizontal lines. The distance between the lines was set to 5 nm, as shown in Figure 6a. Consequently, G_size measured using Equation (6) was 11.8 nm in SNWFETs. According to previous research, the value of SL is 105 V/nm in SNWFETs [22]. σΦ_M was calculated by putting obtained G_size and SL into Equation (3), and Figure 6b shows σΦ_M as a function of the square root of the channel area. Interestingly, the trend and value of the slope in Figure 6b (A_WFV) are very similar to A_vt for each D_NW. It means WFV induced by MGG is the dominant random variation component of V_th variation in the SNWFETs.

3.2.2. The Contribution of Variation Sources to σV_th for Each D_NW

Figure 7 shows that Equation (2) accurately fitted the measured σV_th with the relative root mean square error of 0.3% where σN_ch = 1.11 × 10¹⁸ cm and σD_NW = 0.743 nm. WFV and D_NW are slightly correlated because D_NW is included in Equation (3), which can affect the modeling accuracy. However, assuming the occurrence of ∆D_NW of 0.743 nm, the possible WFV fluctuation is only by 2.4% of total σV_th and does not change the D_NW tendency of σV_th induced by each variation source. The D_NW tendency of σV_th can be explained by the different contributions of the three variation sources, which are represented using pink (WFV), red (∆N_ch), and green (∆D_NW) lines in Figure 7. The modeling results are shown considering L_G = 15 nm; however, the model was also applied to SNWFET with other L_G, and the modeling accuracy and trend of each variation sources are very similar.

Although A_MGG decreases when D_NW decreases, the contribution of WFV increases owing to the decrease in the channel area. As D_NW decreases, SNWFETs become robust to ∆N_ch-induced V_th variation. This is because the influence of depletion charge and surface potential is reduced proportional to $r_{\mathrm{nw}}^2$ because of the improvement in gate-controllability, as shown in Equation (4). Conversely, SNWFETs become vulnerable to ∆D_NW-induced V_th variation because the sensitivity of V_th to quantum effect is proportional to 1/$r_{\mathrm{nw}}^3$, as indicated in Equation (5). Consequently, the contribution of ∆D_NW, WFV, and ∆N_ch is dominant when at D_NW of 7 nm, 9 nm, and 12, respectively.

3.2.3. The Tendency of σN_ch and σD_NW as L_G Changes

Figure 8 shows both σN_ch and σD_NW increases as L_G decreases. This result means that RDF and LER occur because their influence increases as the device dimension decreases. However, the degree of σN_ch and σD_NW increase is small, about 5%, as L_G decreases from 22 to 15 nm. In addition, we already verified WFV by MGG is the dominant random variation component of V_th variation in Section 3.2.1. Hence, most ∆N_ch and ∆D_NW originated from process variation sources, which causes non-zero y-intercept in Figure 3.

4. Conclusions

The contribution of WFV, ∆N_ch, and ∆D_NW in V_th variation of SNWFET was quantitatively analyzed for each D_NW using the novel modeling approach. The sensitivity of WFV against the channel area is similar to that of σV_th. As D_NW decreases, SNWFETs became robust to ∆N_ch but vulnerable to ∆D_NW. The dominant variation sources differed for each D_NW. Hence, the strategy to improve the variability of SNWFETs should be different for each D_NW. Furthermore, with slight modifications, the proposed modeling approach and results are expected to be used in most multigate devices, including FinFET and nanosheet FET.