Novel Modeling Approach to Analyze Threshold Voltage Variability in Short Gate-Length (15–22 nm) Nanowire FETs with Various Channel Diameters

In this study, threshold voltage (Vth) variability was investigated in silicon nanowire field-effect transistors (SNWFETs) with short gate-lengths of 15–22 nm and various channel diameters (DNW) of 7, 9, and 12 nm. Linear slope and nonzero y-intercept were observed in a Pelgrom plot of the standard deviation of Vth (σVth), which originated from random and process variations. Interestingly, the slope and y-intercept differed for each DNW, and σVth was the smallest at a median DNW of 9 nm. To analyze the observed DNW tendency of σVth, a novel modeling approach based on the error propagation law was proposed. The contribution of gate-metal work function, channel dopant concentration (Nch), and DNW variations (WFV, ∆Nch, and ∆DNW) to σVth were evaluated by directly fitting the developed model to measured σVth. As a result, WFV induced by metal gate granularity increased as channel area increases, and the slope of WFV in Pelgrom plot is similar to that of σVth. As DNW decreased, SNWFETs became robust to ∆Nch but vulnerable to ∆DNW. Consequently, the contribution of ∆DNW, WFV, and ∆Nch is dominant at DNW of 7 nm, 9 nm, and 12, respectively. The proposed model enables the quantifying of the contribution of various variation sources of Vth variation, and it is applicable to all SNWFETs with various LG and DNW.

Therefore, several simulations and models have been recommended to analyze the contribution of multiple sources to V th variation. First, technology computer-aided design (TCAD) simulations are suitable for analyzing the influence of variation sources, but it is difficult to predict the cause of variation inversely from measured V th variation [6][7][8][9][10]. Second, simulation program with integrated circuit emphasis (SPICE)-based models can be applied to analyze the variation sources of measured V th variation, but it consumes time and makes an error because all devices should be calibrated [15]. Last, models based on the error propagation law have been proposed [16,17]. These modeling approaches enable extraction of the contribution of each variation source to the standard deviation of V th (σV th ) fast and accurately because they directly model σV th . However, the error propagation law-based model to analyze the V th variability of SNWFET has not been suggested.
Previously, V th variability in SNWFETs was investigated considering various L G using a SPICE-based model [15]. However, the study did not consider the effect of channel dopant concentration (N ch ) variation and nanowire diameter (D NW ) change. Furthermore, although D NW influences W eff , electrostatics, and quantum effect [18], the D NW tendency of V th variability in SNWFET with short L G has not been thoroughly investigated.
Therefore, in this study, we quantitatively analyzed the sources of V th variation in SNWFETs with short L G (15-22 nm) and multiple D NW (7, 9, 12 nm). A novel modeling approach based on the error propagation law is proposed to estimate the contribution of multiple variation sources to the V th variability. The dominant variation source of V th variation is analyzed for each D NW by using the proposed model. Additionally, the standard deviation of N ch (σN ch ) and D NW (σD NW ) according to L G is presented. Figure 1 depicts the schematic and V th variation sources of SNWFETs, fabricated using the same process flow reported in [19,20]. The SNWFETs adopted Mid-gap TiN metal gate, gate oxide thickness (t ox ) of 3.4 nm, and (110) channel direction. The gate and nanowire trimming process was used to obtain L G varying from 15 to 22 nm and D NW of 7, 9, and 12 nm. In this process, D NW variation (∆D NW ) was caused by LER occurred at the nanowire (NW) edges and under-or over-etching of the NW [21]. MGG occurred in the TiN metal gate and generated the metal work function variation (WFV) [22]. The transmission electron microscope (TEM) image shows many grain boundaries exist in the TiN metal gate of the SNWFETs [19]. Although the SNWFET is fabricated with an undoped channel, the source/drain (S/D) dopants diffuse into the channel with short L G [18,23]. Consequently, N ch variation (∆N ch ) was caused by RDF, the S/D dopant implant, annealing, and SiGe strain variation [8][9][10]. and makes an error because all devices should be calibrated [15]. Last, models based on the error propagation law have been proposed [16,17]. These modeling approaches enable extraction of the contribution of each variation source to the standard deviation of Vth (σVth) fast and accurately because they directly model σVth. However, the error propagation lawbased model to analyze the Vth variability of SNWFET has not been suggested.

Structure and Possible V th Variation Sources of SNWFETs
Previously, Vth variability in SNWFETs was investigated considering various LG using a SPICE-based model [15]. However, the study did not consider the effect of channel dopant concentration (Nch) variation and nanowire diameter (DNW) change. Furthermore, although DNW influences Weff, electrostatics, and quantum effect [18], the DNW tendency of Vth variability in SNWFET with short LG has not been thoroughly investigated.
Therefore, in this study, we quantitatively analyzed the sources of Vth variation in SNWFETs with short LG (15-22 nm) and multiple DNW (7, 9, 12 nm). A novel modeling approach based on the error propagation law is proposed to estimate the contribution of multiple variation sources to the Vth variability. The dominant variation source of Vth variation is analyzed for each DNW by using the proposed model. Additionally, the standard deviation of Nch (σNch) and DNW (σDNW) according to LG is presented.  [19,20]. The SNWFETs adopted Mid-gap TiN metal gate, gate oxide thickness (tox) of 3.4 nm, and (110) channel direction. The gate and nanowire trimming process was used to obtain LG varying from 15 to 22 nm and DNW of 7, 9, and 12 nm. In this process, DNW variation (∆DNW) was caused by LER occurred at the nanowire (NW) edges and under-or over-etching of the NW [21]. MGG occurred in the TiN metal gate and generated the metal work function variation (WFV) [22]. The transmission electron microscope (TEM) image shows many grain boundaries exist in the TiN metal gate of the SNWFETs [19]. Although the SNWFET is fabricated with an undoped channel, the source/drain (S/D) dopants diffuse into the channel with short LG [18,23]. Consequently, Nch variation (∆Nch) was caused by RDF, the S/D dopant implant, annealing, and SiGe strain variation [8][9][10].   of SNWFETs. Figure 2b illustrates a quantile plot of V th for each D NW in SNWFETs with an L G of 15 nm, which shows the distribution of V th . The distribution of V th predominantly follows the theoretical normal distribution for all device conditions, which indicates that sufficient V th values were obtained to analyze σV th . Nanomaterials 2022, 12, x FOR PEER REVIEW 3 of 10 Figure 2a depicts the ID-VG characteristics of SNWFETs with LG = 15 nm and DNW = 7 nm at a drain bias of 0.05 V. About 50 samples were measured per device condition. Here, Vth was extracted at ID = 10 −7 × πDNW/LG using the constant current method. The fluctuation of extracted Vth shows the process and random variation affect the physical characteristics of SNWFETs. Figure 2b illustrates a quantile plot of Vth for each DNW in SNWFETs with an LG of 15 nm, which shows the distribution of Vth. The distribution of Vth predominantly follows the theoretical normal distribution for all device conditions, which indicates that sufficient Vth values were obtained to analyze σVth.  showing the trend of σVth as channel area changes. The slope of the Pelgrom plot, defined as the Pelgrom coefficient (Avt), represents the effect of random variation [4]. The y-intercept of the Pelgrom plot is also observed, indicating the effect of the process variation and short channel effect [12,24]. Remarkably, the values of Avt and y-intercepts differed for each DNW, and the σVth is smallest in median DNW of 9 nm. We anticipated that this result implies a trade-off relationship between the various variation sources. Hence, a novel modeling approach is proposed to analyze the contribution of each variation source to σVth.   [4]. The y-intercept of the Pelgrom plot is also observed, indicating the effect of the process variation and short channel effect [12,24]. Remarkably, the values of A vt and y-intercepts differed for each D NW , and the σV th is smallest in median D NW of 9 nm. We anticipated that this result implies a trade-off relationship between the various variation sources. Hence, a novel modeling approach is proposed to analyze the contribution of each variation source to σV th .  Figure 4 shows the proposed modeling flow to analyze the contribution of WFV, ∆Nch, and ∆DNW to σVth. To model σVth, we started from a physical model for Vth of   Figure 4 shows the proposed modeling flow to analyze the contribution of WFV, ∆N ch , and ∆D NW to σV th . To model σV th , we started from a physical model for V th of SNWFET, as follows [25,26]:

Proposed σV th Model of SNWFETs
where Φ M denotes the work function of the TiN gate metal; Φ S represents the work function of silicon channel calculated as χ si − E g /2 + kT/q·ln(N ch /n i ), where χ si is the electron affinity and E g is the band gap of silicon; r nw indicates the radius of NW; ε si and ε ox represent the dielectric constant of silicon and oxide, respectively; h denotes the Planck constant; and m* indicates the effective mass of an electron. C ox represents the oxide capacitance calculated as 2πε ox /ln(1 + t ox /r nw ). The possible V th variation sources in Equation (1) are Φ M, N ch , D NW , and t ox variations. Among them, t ox is not considered because its variation and effect are very small and negligible [11,12,27]. Although the variation of effective channel length (L eff ) is not considered directly, N ch variation partially represents L eff variation because S/D dopant diffusion and L G variation change N ch and L eff simultaneously.  Hence, considering three identical variation sources of WFV, ∆Nch, and ∆DNW, σVth can be expressed based on the error propagation law as To analyze σVth using Equation (2), the sensitivity of Vth against variation sources and their standard deviation should be extracted. First, the standard deviation of metal work function (σΦM) can be estimated by the existing WFV model for SNWFETs, as follows [22]: where RGG is the ratio of average grain size to the gate area, SL is the sensitivity of σVth against RGG, and Gsize is the grain size of the metal gate. Here, Gsize can be estimated from a TEM image of the TiN metal gate of SNWFETs. SL of SNWFETs can be obtained from previous research based on TCAD simulation [22]. Second, the sensitivity of Vth against ∆Nch and ∆DNW can be obtained by calculating the partial differentiation of Equation (1), as follows: Hence, considering three identical variation sources of WFV, ∆N ch , and ∆D NW , σV th can be expressed based on the error propagation law as To analyze σV th using Equation (2), the sensitivity of V th against variation sources and their standard deviation should be extracted. First, the standard deviation of metal work function (σΦ M ) can be estimated by the existing WFV model for SNWFETs, as follows [22]: where RGG is the ratio of average grain size to the gate area, SL is the sensitivity of σV th against RGG, and G size is the grain size of the metal gate. Here, G size can be estimated from a TEM image of the TiN metal gate of SNWFETs. SL of SNWFETs can be obtained from previous research based on TCAD simulation [22]. Second, the sensitivity of V th against ∆N ch and ∆D NW can be obtained by calculating the partial differentiation of Equation (1), as follows: where k denotes the Boltzmann constant. Here, N ch can be extracted where Equation (1) best fits to measured V th . Finally, σN ch and σD NW are extracted when Equation (2) best fits the square of the measured σV th .
The proposed model obtains the V th sensitivity against ∆N ch and ∆D NW through simple calculation and extracts the standard deviation of each variation source by fitting the model to the measured σV th . Therefore, the contribution of multiple variation sources to σV th can be directly and quickly modeled and analyzed using the proposed model without any TCAD or SPICE simulation. Furthermore, the proposed V th modeling flow is expected to be applied to analyze σV th in most multigate devices with various L G and channel thicknesses.

V th Modeling Results of SNWFETs
N ch is extracted where Equation (1) fitted V th versus D NW with high accuracy in SNWFET with L G of 15 nm, as shown in Figure 5a. Figure 5b shows N ch increases as L G decreases because more dopant diffused to the center of the channel from S/D even with the same S/D junction gradient. The sensitivity of V th against ∆N ch and ∆D NW was calculated by substituting N ch and other parameters in Equations (4) and (5).

Vth Modeling Results of SNWFETs
Nch is extracted where Equation (1) fitted Vth versus DNW with high accuracy in SNWFET with LG of 15 nm, as shown in Figure 5a. Figure 5b shows Nch increases as LG decreases because more dopant diffused to the center of the channel from S/D even with the same S/D junction gradient. The sensitivity of Vth against ∆Nch and ∆DNW was calculated by substituting Nch and other parameters in Equations (4) and (5).

Extraction of Gsize and WFV of SNWFETs
Gsize should be determined from the TEM image of the TiN metal gate of the SNWFET to analyze WFV. Figure 6a shows a schematic of the grain boundaries based on TiN metal gate TEM image [19]. Gsize was measured as the average of values obtained by dividing the length of TiN metal in the TEM image (LTEM) by the number of intersections between   Figure 6a shows a schematic of the grain boundaries based on TiN metal gate TEM image [19]. G size was measured as the average of values obtained by dividing the length of TiN metal in the TEM image (L TEM ) by the number of intersections between grain boundaries and horizontal lines (N int ), as follow [28]: where N line is the number of horizontal lines. The distance between the lines was set to 5 nm, as shown in Figure 6a. Consequently, G size measured using Equation (6) was 11.8 nm in SNWFETs. According to previous research, the value of SL is 105 V/nm in SNWFETs [22]. σΦ M was calculated by putting obtained G size and SL into Equation (3), and Figure 6b shows σΦ M as a function of the square root of the channel area. Interestingly, the trend and value of the slope in Figure 6b Figure 7 shows that Equation (2) accurately fitted the measured σVth with the relative root mean square error of 0.3% where σNch = 1.11 × 10 18 cm and σDNW = 0.743 nm. WFV and DNW are slightly correlated because DNW is included in Equation (3), which can affect the modeling accuracy. However, assuming the occurrence of ∆DNW of 0.743 nm, the possible WFV fluctuation is only by 2.4% of total σVth and does not change the DNW tendency of σVth induced by each variation source. The DNW tendency of σVth can be explained by the different contributions of the three variation sources, which are represented using pink (WFV), red (∆Nch), and green (∆DNW) lines in Figure 7. The modeling results are shown considering LG = 15 nm; however, the model was also applied to SNWFET with other LG, and the modeling accuracy and trend of each variation sources are very similar.

The Contribution of Variation Sources to σVth for Each DNW
Although AMGG decreases when DNW decreases, the contribution of WFV increases owing to the decrease in the channel area. As DNW decreases, SNWFETs become robust to ∆Nch-induced Vth variation. This is because the influence of depletion charge and surface potential is reduced proportional to because of the improvement in gate-controllability, as shown in Equation (4). Conversely, SNWFETs become vulnerable to ∆DNW-induced  Figure 7 shows that Equation (2) accurately fitted the measured σV th with the relative root mean square error of 0.3% where σN ch = 1.11 × 10 18 cm and σD NW = 0.743 nm. WFV and D NW are slightly correlated because D NW is included in Equation (3), which can affect the modeling accuracy. However, assuming the occurrence of ∆D NW of 0.743 nm, the possible WFV fluctuation is only by 2.4% of total σV th and does not change the D NW tendency of σV th induced by each variation source. The D NW tendency of σV th can be explained by the different contributions of the three variation sources, which are represented using pink (WFV), red (∆N ch ), and green (∆D NW ) lines in Figure 7. The modeling results are shown considering L G = 15 nm; however, the model was also applied to SNWFET with other L G , and the modeling accuracy and trend of each variation sources are very similar.

The Contribution of Variation Sources to σV th for Each D NW
Although A MGG decreases when D NW decreases, the contribution of WFV increases owing to the decrease in the channel area. As D NW decreases, SNWFETs become robust to ∆N ch -induced V th variation. This is because the influence of depletion charge and surface potential is reduced proportional to r 2 nw because of the improvement in gate-controllability, as shown in Equation (4). Conversely, SNWFETs become vulnerable to ∆D NW -induced V th variation because the sensitivity of V th to quantum effect is proportional to 1/r 3 nw , as indicated in Equation (5). Consequently, the contribution of ∆D NW , WFV, and ∆N ch is dominant when at D NW of 7 nm, 9 nm, and 12, respectively. LG decreases. This result means that RDF and LER occur because their influence increases as the device dimension decreases. However, the degree of σNch and σDNW increase is small, about 5%, as LG decreases from 22 to 15 nm. In addition, we already verified WFV by MGG is the dominant random variation component of Vth variation in Section 3.2.1. Hence, most ∆Nch and ∆DNW originated from process variation sources, which causes non-zero y-intercept in Figure 3.

Conclusions
The contribution of WFV, ∆Nch, and ∆DNW in Vth variation of SNWFET was quantita-  Figure 8 shows both σN ch and σD NW increases as L G decreases. This result means that RDF and LER occur because their influence increases as the device dimension decreases. However, the degree of σN ch and σD NW increase is small, about 5%, as L G decreases from 22 to 15 nm. In addition, we already verified WFV by MGG is the dominant random variation component of V th variation in Section 3.2.1. Hence, most ∆N ch and ∆D NW originated from process variation sources, which causes non-zero y-intercept in Figure 3. LG decreases. This result means that RDF and LER occur because their influence increases as the device dimension decreases. However, the degree of σNch and σDNW increase is small, about 5%, as LG decreases from 22 to 15 nm. In addition, we already verified WFV by MGG is the dominant random variation component of Vth variation in Section 3.2.1. Hence, most ∆Nch and ∆DNW originated from process variation sources, which causes non-zero y-intercept in Figure 3.

Conclusions
The contribution of WFV, ∆Nch, and ∆DNW in Vth variation of SNWFET was quantita-

Conclusions
The contribution of WFV, ∆N ch , and ∆D NW in V th variation of SNWFET was quantitatively analyzed for each D NW using the novel modeling approach. The sensitivity of WFV against the channel area is similar to that of σV th . As D NW decreases, SNWFETs became robust to ∆N ch but vulnerable to ∆D NW . The dominant variation sources differed for each D NW . Hence, the strategy to improve the variability of SNWFETs should be different for each D NW . Furthermore, with slight modifications, the proposed modeling approach and results are expected to be used in most multigate devices, including FinFET and nanosheet FET.