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A High Throughput Hardware Architecture for Parallel Recursive Systematic Convolutional Encoders

Department of Information Engineering, University of Pisa, Via Girolamo Caruso, 16, 56122 Pisa, Italy
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Information 2019, 10(4), 151; https://doi.org/10.3390/info10040151
Received: 30 March 2019 / Revised: 21 April 2019 / Accepted: 22 April 2019 / Published: 24 April 2019
(This article belongs to the Special Issue ICSTCC 2018: Advances in Control and Computers)
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Abstract

During the last years, recursive systematic convolutional (RSC) encoders have found application in modern telecommunication systems to reduce the bit error rate (BER). In view of the necessity of increasing the throughput of such applications, several approaches using hardware implementations of RSC encoders were explored. In this paper, we propose a hardware intellectual property (IP) for high throughput RSC encoders. The IP core exploits a methodology based on the ABCD matrices model which permits to increase the number of inputs bits processed in parallel. Through an analysis of the proposed network topology and by exploiting data relative to the implementation on Zynq 7000 xc7z010clg400-1 field programmable gate array (FPGA), an estimation of the dependency of the input data rate and of the source occupation on the parallelism degree is performed. Such analysis, together with the BER curves, provides a description of the principal merit parameters of a RSC encoder. View Full-Text
Keywords: recursive systematic convolutional encoder; parallelism; FPGA; high throughput recursive systematic convolutional encoder; parallelism; FPGA; high throughput
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Meoni, G.; Giuffrida, G.; Fanucci, L. A High Throughput Hardware Architecture for Parallel Recursive Systematic Convolutional Encoders. Information 2019, 10, 151.

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