Start-Up Current Spike Mitigation of High-Power Laser Diode Driving Controller for Vehicle Headlamp Applications

Featured Application

Vehicle headlamp and laser diode driving and control.

Abstract

A high-power laser diode driving controller (HPLDDC), which incorporates the power converter with the feedback controller, was developed and implemented in this paper. The synchronous buck–boost converter (SBBC) was the topology of the power converter; the SBBC could be operated in step-up or step-down mode in accordance with variable on-board battery voltage inputs into the HPLDDC. Moreover, the feedback controllers were equipped with a current-loop controller (CLC) and a voltage-loop controller (VLC); the VLC was employed to regulate the SBBC output voltage to drive and start-up the high-power laser diode (HPLD). The CLC was used to regulate the SBBC output current to supply a constant-current driving the HPLDs. During the start-up transient phase, when the SBBC output mode is changed from the constant-voltage to the constant-current, a start-up current spike occurs that can destroy the semiconductor material of the laser diode. However, few studies have discussed methods of coping with this problem. Therefore, this study proposed a proportional-integral associating proportional (PIAP) control technology, which can be applied to the CLC for the start-up current spike mitigation. Complete designs and analyses are presented in this paper. Simulations and experiments validate that the PIAP control method is effectual to solve the start-up current spike.

1. Introduction

As semiconductor technology continues to develop and innovate, the uses of electronic devices and elements in the on-board parts of vehicles or electric cars are progressively increasing. Twin headlamps in the front end of vehicles, including the blink lights, low beam lights, and high beam lights, are applied to cope with different traffic circumstances. In vehicle headlamps, incandescent halogen lamps have been replaced with optoelectronic semiconductors (OPSs) in a new generation of cars, due to their benefits such as direct-current (DC) driving, high brightness, high efficiency of power conversion, and outstanding color rendering [1,2,3,4,5,6]. In addition, when motor vehicles are driven in road tunnels or on roadways in the night, the headlamp irradiation ranges can be expanded using high beam lights, the brightness of which settles on metal halide high-intensity discharge (HID) lamps. However, several negative characteristics of HID lamps should be contemplated, including alternating-current (AC) power driving, AC high-voltage start-up, and negative resistance characteristic; thus, electronic ballasts can be used to stabilize the brightness and driving current of HID lamps [7,8,9].

The abbreviation, laser, is an acronym for light amplification by stimulated emission of radiation. According to laser oscillator configurations, laser devices can be classified based on the various materials used for construction, such as solid-state laser, gas laser, semiconductor laser, and fiber laser. Figure 1a is a simple model of the semiconductor laser, whose active layer is embedded in between the p-type and n-type materials. The p-type Gallium Nitride (p-GaN ) can be a positive electrode, and the n-type Gallium Nitride (n-GaN) contact can be a negative electrode. When the laser diode (LD) is excited, the active layer can emit laser beams, which can be amplified using the mirror surfaces to emit laser beams [10]. When voltage from a power source is applied to the positive–negative electrode and the laser diode operates in the forward bias, the electrons are injected into the active layer from the n-type semiconductor; the wide band gap of the heterojunction can limit the amount of electron combinations in the active layer, and, through this carrier confinement, the population inversion probabilities can be substantially increased to promote high-intensity light emission [11], as shown in Figure 1b. In addition, the semiconductor laser possesses several exceptional characteristics, including monochromaticity, high directionality, high coherence, and high energy density. Thus, motor vehicle manufacturers have started to develop the high beam light of high brightness based on the high-power laser diode (HPLD).

In this study, the HPLD of InGaN-based blue beam was used as the illuminant sources for vehicle headlamps. Due to the optical output power (OOP) of HPLD being directly proportional to its forward operating current [12], the HPLDs must be driven by a constant-current (CC). Therefore, the design of high-power laser diode driving controller (HPLDDC) requires a current-loop controller (CLC) and a voltage-loop controller (VLC) to manipulate the HPLDDC, achieving the constant-current output mode (CCOM) and constant-voltage output mode (CVOM), and the CLC and VLC can apply the proportional-integral (PI) control to accomplish the low steady-state error and system stable requirement. The PI control has excellent behavior in the low steady-state error; however, the tardy response speed of PI control can result in the current spike problem and the long settling time during the HPLDDC start-up transient phase. Therefore, studies [13,14,15] have proposed the use of dual control loops, including the proportional (P) control and PI control, in which the P control can promote transient responses, and the dual control loops combined a P control loop with a PI control loop to reduce steady-state errors; thus, the system can address the requirements of transient responses and steady-state stability. However, the implementations of dual control loops with P and PI controls in the HPLDDC are too complex. Therefore, this study employed a control method, proportional-integral, associating proportional (PIAP) control, to depress the start-up current spikes.

An HPLDDC was implemented and developed in this study to drive blue beam HPLDs as the illuminant source for motor vehicle headlamps. Because the on-bard battery was used as the HPLDDC’s input power and the battery voltage varied during charging or discharging, a synchronous buck–boost converter (SBBC) was applied as the power converter of HPLDDC. In addition, SBBC’s CCOM or CVOM operation could be implemented through the CLC or VLC manipulation. During the HPLDDC start-up transient phase, when the HPLDDC changed its output mode from the CVOM to CCOM, the CLC adopting the PIAP control was effectual for the start-up current spike depressing. Six sections are presented in this paper. SBBC principles and analyses are presented in Section 2. The PIAP control method to solve the start-up current problem is explained and analyzed in Section 3. Section 4 includes design considerations, analyses, and simulations for the HPLDDC current loop. In Section 5, experimental waveforms can confirm that the PIAP control is efficacious. Section 6 is this study’s conclusions.

2. Power Converter Principle

The HPLDDC system configuration is depicted in Figure 2, including the CVOM and CCOM controllers, a DC–DC convertor, and safety standard components. The on-board battery supplies a DC-power to the HPLDDC inlet; the HPLDDC outlet connects three HPLDs in series. To protect the SBBC, CVOM, and CCOM controllers, the SBBC input side must place safety standard components because voltage impulses and spikes or EMI/EMC noises from the battery power bus can be filtered out. In addition, the DC–DC converter topology is the SBBC; an SBBC circuit is shown in Figure 3; this circuit composition includes an output capacitor, C_o, power switches, Q₁–Q₄, and an inductor, L₁. Principles and analyses in the buck and boost modes are discussed in the following.

2.1. Buck Mode Principle

In the buck operation, power switches, Q₁–Q₄, (Figure 3) are replaced with power metal-oxide-semiconductor field-effect transistors (MOSFETs); the synchronous buck circuit with the operating timing is presented in Figure 4. In Figure 4a, v_gs1–v_gs4 are the MOSFET gate-to-source pulse width modulation (PWM) driving signals, and i_L represents the inductor current. When the SBBC input voltage, V_in, is greater than the HPLDDC output voltage, V_o (V_in > V_o), v_gs4 is at the high-voltage level, and, consequently, the MOSFET Q₄ is always turned on; v_gs3 is always at the low-voltage level to turn off the MOSFET Q₃. The time intervals, t_k0–t_k1 and t_k2–t_k3, are dead times that can prevent MOSFETs Q₁ and Q₂ from concurrently turning on and becoming a short–circuit. v_gs2 is changed to the high-voltage level during the time interval, t_k1–t_k2, thereby decreasing i_L. Figure 4b presents the operating circuit during the time interval, t_k0–t_k2.

When i_L is lower than the current command inside the SBBC controller at t_k2, v_gs2 is changed to the low-voltage level, thus, turning off Q₂, and v_gs1 is changed to the high-voltage level at t_k3, thus, increasing i_L. The operating circuit during the time interval, t_k3–t_k4, is depicted in Figure 4c. When i_L is greater than the current command inside the SBBC controller at t_k4, v_gs1 is changed to the low-voltage level, thus, turning off Q₁.

2.2. Boost Mode Principle

Figure 5 illustrates the synchronous boost circuit and the timing chart. When V_in is lower than V_o (V_in < V_o) throughout the operation, v_gs1 is at the high-voltage level to turn on Q₁, and v_gs2 is at the low-voltage level to turn off Q₂. Both the time intervals, t_t0–t_t1 and t_t2–t_t3, are dead times that can prevent Q₃ and Q₄ from concurrently turning on and causing the short–circuit. v_gs3 is changed to the high-voltage level during the time interval, t_t1–t_t2, thus, increasing i_L; the operating circuit in the time interval, t_t1–t_t2, is depicted in Figure 5b. At t_t2, because i_L is greater than the current command inside the SBBC controller, v_g3 is changed to the low-voltage level, thus, turning off Q₃. In the time interval, t_t3–t_t4, v_g4 is at the high-voltage level and Q₄ is turned on, hence, decreasing i_L; the operating circuit during t_t3–t_t4 is depicted in Figure 5c. When i_L is lower than the current command inside the SBBC controller at time, t_t4, v_gs4 is changed to the low-voltage level, thus, turning off Q₄.

2.3. Designs of Output Capacitor and Inductor

Because the SBBC was the topology of the power converter, which can implement the buck or boost mode, the output capacitor and inductor should be computed to address the practical circuit application. The calculating formulas and explanations are in the following sections.

2.3.1. SBBC Inductor for Buck Mode

In accordance with the study [14], the inductor for the SBBC’s buck mode operation can be estimated as follows:

$$L_{bk}=D_{bk}(V_{in(max)}-V_{\mathrm{o}(min)})/(2f_s\Delta i_L).$$

(1)

The notation, L₁, (Figure 3) can be replaced with L_bk. ∆i_L is the inductor peak current that can be estimated using the βI_o, β is the percent from the peak-to-peak inductor current, and I_o is the HPLDDC output current. D_bk is the duty cycle of the buck mode that can be estimated using the V_o(min)/V_in(max), V_o(min) is the HPLDDC minimum output voltage, and V_o(max) is the HPLDDC maximum output voltage. f_s is the switching frequency of Q₁–Q₄. Substitution of ∆i_L = βI_o and D_bk = V_o(min)/V_in(max) into (1) can rewrite the equation as follows:

$$L_{bk}=V_{o(min)}(V_{in(max)}-V_{o(min)})/(2V_{in(max)}{f}_s{I}_o\beta ).$$

(2)

2.3.2. SBBC Inductor for Boost Mode

In accordance with the study [16], the inductor for the SBBC’s boost mode operation can be estimated as follows:

$$L_{bt}=V_{in(min)}{D}_{bt}/(2f_s\Delta i_L).$$

(3)

L₁ can be replaced with L_bt, D_bt is the duty cycle of the boost mode that can be estimated using (V_o(max)−V_in(min))/V_o(max). V_in(min) is the HPLDDC minimum input voltage. Substitution of ∆i_L = βI_o and D_bt = (V_o(max)−V_in(min))/V_o(max) into Equation (3) can rewrite the equation as follows:

$$L_{bt}=V_{in(min)}(V_{o(max)}-V_{in(min)})/(2f_s{V}_{o(max)}{I}_o\beta ).$$

(4)

2.3.3. SBBC Output Capacitor

In accordance with the study [16], the SBBC output capacitor (Figure 3) can be estimated as follows:

$$C_o=D{V}_o/(2\Delta v_o{f}_s{R}_o),$$

(5)

where D represents the duty cycle from D_bk or D_bt. ∆v_o is the HPLDDC output ripple voltage that can be estimated using 〈V_o(min), and the ripple voltage peak can be defined by a percentage, α. R_o is the output equivalent resistance at the HPLDDC output side.

In addition, an effective series resistance (ESR) parasitizes on C_o that can be expressed as follows [17]:

$$ESR\le \Delta v_o/I_{in(peck),}$$

(6)

where I_in(peak) is the peak value of the HPLDDC input current. According to I_o/I_in = 1/D_bk, I_in(peak) can be estimated as I_oD_bk(1+β).

• SBBC Output Capacitor for Buck Mode

For the buck mode, the notation C_o in Equation (5) can be replaced with C_obk. Substitution of C_o = C_obk, V_o = V_o(min), R_o= V_o(min)/I_o, D = D_bk = V_o(min)/V_in(max), and ∆v_o = αV_o(min) into Equation (5) obtains the output capacitor of the buck mode operation as follows:

$$C_{obk}=I_o/(2V_{in(max)}\alpha f_s).$$

(7)

ESR in Equation (6) is replaced with ESR_bk. Substitution of ∆v_o = αV_o(min) and D_bk = V_o(min)/V_in(max) into Equation (6) can rewrite the equation as follows:

$$ES{R}_{bk}\le \alpha V_{in(max)}/[I_o(1+\beta )].$$

(8)

• SBBC Output Capacitor for Boost Mode

For the boost mode, C_o can be replaced with C_obt. Substitution of C_o = C_obt, V_o = V_o(max), D = D_bt = (V_o(max) − V_o(min))/V_o(max), ∆v_o = αV_o(max), and R_o = V_o(max)/I_o into Equation (5) can obtain the output capacitor of the boost mode as follows:

$$C_{obt}=I_o(V_{o(max)}-V_{in(min)})/(2\alpha V_{o(max)}^2{f}_s).$$

(9)

ESR is replaced with ESR_bt. Substitution of ∆v_o = αV_o(min) and D_bt = (V_o(max)−V_in(min))/V_o(max) into (6) can rewrite the equation as follows:

$$ES{R}_{bt}\le \alpha V_{in(min)}/[I_o(1+\beta )].$$

(10)

3. HPLDDC Control Loop

Figure 6 depicts the ideal voltage–current characteristic of LD; V_LDF is the forward voltage of LD and a slight current (approximating to no current) flows if the LD driving voltage is lower than V_LDF. Without any driving devices to regulate the LD driving current, if the LD driving voltage is higher than V_LDF, more current is indispensable to drive the LD strengthening the laser beams, and the driving current can be increased exponentially. Because the constant OOP originates from a stable LD driving current, the LD can be driven by a CC output power supply, or regulated by a CC sink. Several control methods for the LD driving are discussed in the following section.

3.1. Constant-Current Sink Control

The optoelectronic semiconductor (OPS) including the light-emitting diode (LED), the organic light-emitting diode (OLED), and the LD, should be driven by a CC to obtain a constant OOP or luminance. Figure 7 presents a familiar OPS control circuit that includes the lighting driver, OPSs, and the current regulator (CR). To control the constant driving current in OPSs, a CR comprising an operational amplifier (OPA), a transistor, and a current–voltage (C-V) converter, is the critical circuit because the CR can be considered as a current sink; when the OPS operates in the forward bias, the OPS driving current I_f sinks into the transistor, and then I_f can be converted by the C–V converter becoming a voltage V_If; therefore, the transistor can be considered as a variable resistance for adjusting the I_f because the OPA compares the V_If with a CC command to control the transistor’s operating region [18,19]. However, the CR is unable to address less steady-state errors and sufficient phase margins. Moreover, the lighting driver is a constant-voltage (CV) power source, and although the CC can be achieved using the CR; however, the transistor’s equivalent resistance would cause the power loss and heating. Therefore, the CR is unsuitable for the high-power OPS control.

3.2. Constant-Current Source Driving and CLC Using PI Control

To supply a CV or CC DC-power to drive HPLDs, CVOM and CCOM controllers play a critical role in dominating HPLDDC operations. In Figure 2, CVOM and CCOM controllers comprise a SBBC controller, a C-V converter, a voltage divider, a signal amplifier (SA), and a CLC. As shown in Figure 8, to accomplish the HPLDDC’s CVOM, the voltage divider detects V_o to output a voltage V_os, and then the VLC of SBBC controller can obey V_os to produce an error voltage to manipulate the PWM module. Therefore, the HPLDDC can be controlled in the CVOM to supply the adequate and stable forward voltage driving HPLDs. In addition, in the HPLDDC’s CCOM, the HPLD driving current can be detected by the C-V converter to become a voltage signal, and then the SA can amplify this voltage signal becoming a current detection signal V_is. According to the V_is variation, an error voltage $V^{\prime }{}_{cea}$ can be produced by the CLC to manipulate the SBBC controller accomplishing the HPLDDC CCOM.

Both start-up voltage and current spikes are pernicious to the HPLD’s semiconductor material. The start-up voltage spike can be solved using the soft-start module (Figure 8). Moreover, the integral action of the PI control causes the start-up current spike; thus, when the SBBC output mode is changed from CVOM to CCOM, the HPLD driving current should avoid the start-up current spike occurrence.

3.3. Constant-Current Source Driving and CLC Using PIAP Control

A circuit configuration diagram of CLC using the PIAP control is depicted in Figure 9. In Figure 9b, during Phase I, the HPLDDC is dominated by the VLC and the soft-start module of the SBBC controller, and then V_o can slowly increase to avoid the voltage overshoot occurrence. When the I_o increase has reached a current value of I₁, a switch, st, (Figure 9a) connects to the position, s₁; thus, the CLC can implement P control during Phase II (Figure 9b), hence, the response speed of CLC can be promoted to mitigate the start-up current spike. In Phase III, I_o has reached the target CC I_cc, the st connects to the position, s₂, and then the CLC uses the PI control to regulate the HPLD driving current in the CC state. The aforementioned three CC control methods can be compared and are listed in

Table 1. Three constant-current (CC) control methods.

CC Control Technology	Driver Output Mode	Driving Current Compensation	Start-up Current Spike Mitigation
CC Sink	CVOM	N/A	N/A
CC Source Using Proportional-Integral (PI) Control	CVOM & CCOM	PI compensation	N/A
CC Source Using Proportional-Integral Associating Proportional (PIAP) Control	CVOM & CCOM	P and PI compensations	Effectual

.

The transfer function (TF) of the duty cycle to the SBBC output current for the buck or boost operation can refer to studies [20,21]; both models have been derived based on a PWM switch model technology from previous studies [16,22,23]. Therefore, the SBBC transfer function is defined as follows:

$$G_{kt}(s)={\tilde{i}}_o/\tilde{d}=k_{con}({nu}_2{s}^2+{nu}_{1}s+{nu}_0){/(de}_2{\mathrm{s}}^2+{de}_{1}s+{de}_0).$$

(11)

According to the buck or boost operation of SBBC, these parameters in (11) are listed in

Table 2. Parameters in Equation (11).

Notation	Transfer Function (TF) Parameter for Buck Mode	TF Parameter for Boost Mode
nu2	0	−L1rc/rhpld
nu1	rcCo	rc(1 − Dbt)2 − L1/(rhpldCo) – rcrL/rhpld
nu0	1	−rL/(rhpldCo) + (1 − Dbt)2/Co
de2	(L1Co)(rhpld + rc)/(rhpld + rL)	L1(rc/rhpld + 1)
de1	Corc + rhpldrL/(rhpld + rL) + L1/(rhpld + rL)	rc(1 − Dbt)2 + rL + rcrL/rhpld + L1/(rhpldCo)
de0	1	rL/(rhpldCo) + (1 − Dbt)2/Co
kcon	Vin(max)/[rhpld (rhpld + rL)]	Vo/[rhpld (1 − Dbt)]

. In Table 2, r_c represents the capacitor’s ESR. r_L represents the inductor’s wire-wind resistance. r_hpld represents the HPLDs’ equivalent dynamic resistor, which can be calculated as:

r_hpld = 3(V_LD2 − V_LD1)/(I_LD2 − I_LD1),

(12)

where V_LD1 and V_LD2 are HPLDs’ operating forward voltages, and I_LD1 and I_LD2 are HPLDs’ operating forward currents.

The current-loop control block diagram of FSBBC is illustrated in Figure 10. In Figure 10, the FSBBC gain is G_kt, the FSBBC controller gain is G_ctlr, the CLC gain using the P control is G_cea(P), the CLC gain using the PI control is G_cea(PI), and a feedback gain is a constant, k_c. In addition, the soft-start function would affect the start-up current spike, hence, it should be considered; G_ss represents the soft-start control gain.

Despite whether the SBBC controller implements the buck or boost control, a linear polynomial of the d-v_cea characteristic is expressed as follows:

d = k_ceav_cea + r,

(13)

where d is the PWM duty cycle that incorporates the large-signal, D, with the small-signal, $\tilde{d}$. v’_cea is the CLC output voltage that incorporates the large-signal, V’_cea, with the small-signal, $\tilde{v}{}^{\prime }{}_{cea}$. Both k_cea and r are constants. Substitution of d = D + $\tilde{d}$ and v’_cea = V’_cea + $\tilde{v}{}^{\prime }{}_{cea}$ into Equation (13), results in the SBBC controller TF being expressed as follows:

$$G_{ctlr}(s)=\tilde{d}/{\tilde{v}}_{cea}=k_{cea}.$$

(14)

The v_cea can exponentially increase in the start-up transient phase to accomplish the soft-start control for the CLC output voltage, v’_cea; hence, the TF of the soft-start control can be expressed as follows:

$$G_{ss}(s)={\tilde{v}}_{cea}/\tilde{v}{}^{\prime }{}_{cea}=1000/(s+1000).$$

(15)

From Figure 10, open-loop TFs G_op(bt) (s) and G_op(bk) (s) can be obtained using (11) and (14), which can be expressed as follows:

G_op(bt) (s) = G_ctlr(bt)(s) G_kt(bt) (s),

(16)

G_op(bk) (s) = G_ctlr(bk) (s) G_kt(bk) (s),

(17)

where G_kt(bt) (s) and G_ctlr(bt) (s) are the SBBC TF and SBBC controller in the boost mode operation. G_kt(bk) (s) and G_ctlr(bk) (s) are in the buck mode operation.

By substituting Equations (16) and (17), and using the MATLAB software, the frequency response to design the CLC for the current loop compensation of HPLDDC can be obtained. Therefore, the HPLDDC requirements for the steady-state operation, including an adequate phase margin, a high low-frequency gain (LFG), and a feasible crossover frequency, can be achieved. The TF of the CLC using the PI control is expressed as follows:

$$G_{cea(PI),}(s)=g_p(s+g_i/g_p)/s=g_p+g_i/s$$

(18)

where g_i and g_p are the integral and proportional gains.

4. Design Consideration and Simulation

In this study, the PL TB405B is the HPLD type-number (Osram Opto Semiconductors Inc., Regensburg, Germany). Its specification is listed in

Table 3. Specification of high-power laser diode (HPLD) at 25 °C.

Depiction	Specification
Operating forward voltage (VLD1) at the operating forward current ILD1 = 0.9 A	4.7 V
Operating forward voltage (VLD2) at the operating forward current ILD2 = 1.2 A	4.8 V
Optical output power	1.6 W
Maximum operating current	1.5 A
Laser emission wavelength	450 nm
Operating temperature range	−40 °C to 85 °C
Package	TO56

from the datasheet [12].

As shown in Figure 2, at the HPLDDC input side, the minimum input voltage, V_in(min), and the maximum input voltage, V_in(max), from the on-board batter were set as 9 and 16 V; at the HPLDDC output side, three blue-beam HPLDs were series connections, and the HPLD’s forward voltage was 14.4 V from V_LD2 in Table 3. Hence, the minimum output voltage of HPLDDC V_o(min) was set as 13 V, and the maximum output voltage of HPLDDC V_o(max) was set as 16 V. The HPLDDC output current, I_o, was 1.2 A for the CC operation. In addition, the switching frequency of Q₁−Q₄ (Figure 3) f_s was 400 kHz. α was set as 1%, and β was set as 20%. These parameters and specifications are listed in

Table 4. High-power laser diode driving controller (HPLDDC) parameters and specifications.

Parameter	Specification	Parameter	Specification
Vin(min)	9 V	Vin(max)	16 V
Vo(min)	13 V	Vo(max)	16 V
Io	1.2 A	fs	400 kHz
α	1%	β	20%

.

The power converter topology was the SBBC, which could be operated in both buck and boost conversion modes, when variable battery voltages input to the HPLDDC. In different input and output voltages, the SBBC operating mode can be changed by the SBBC controller. To ensure the estimating inductor and output capacitor can address the buck and boost operating modes in practical applications, this study provides the design considerations and calculating rule to obtain the single element value for the SBBC circuit assembly.

4.1. Inductor Value Calculation

From Table 4, substitution of V_o(min) = 13 V, V_in(max) = 16 V, f_s = 400 kHz, β = 20%, and I_o = 1.2 A into (2) can obtain L_bk = 9.1 μH. In addition, substitution of V_o(max) = 16 V, V_in(min) = 9 V, f_s = 400 kHz, I_o = 1.2 A, and β = 20% into (4) can obtain L_bt = 20.5 μH.

4.2. Output Capacitor Value Calculation

From Table 4, substitution of I_o = 1.2 A, V_in(max) = 16 V, α = 1%, and f_s = 400 kHz into (7) can obtain C_obk = 9.4 μF; in addition, substitution of the aforementioned parameters and β = 20% into (8) can obtain ESR_bk ≤ 109 mΩ. Moreover, substitution of I_o = 1.2 A, V_in(min) = 9 V, V_o(max) = 16 V, α = 1%, and f_s = 400 kHz into (9) can obtain C_obt = 4.1 μF. Substitution of the aforementioned parameters and β = 20% into (10) can obtain ESR_bt ≤ 62 mΩ. These calculating values, including L_bk, C_obk, ESR_bk, L_bt, C_obt, and ESR_bt, are listed in

Table 5. Calculating inductance and output capacitance values.

Notation	Calculating Value	Notation	Calculating Value
Lbk	9.1 μH	Lbt	20.5 μH
Cobk	9.4 μF	Cobt	4.1 μF
ESRbk	109 mΩ	ESRbt	62 mΩ

. Circuit element specifications in Figure 2 and Figure 9 are listed in

Table 6. Circuit element specification.

Circuit Element	Type-Number	Specification
Q1, Q2, Q3, Q4	IRF7478PBF	Maximum drain–source voltage is 60 V Drain–source turning on resistance is 26 mΩ Drain current is 7 A at 25 °C
L1	CS127060	Inductance value: 30 μH Material: Sendust
Co	EEU-FR1E471Y	Inductance value: 470 μF ESR ≤ 41 mΩ, Aluminum electrolytic capacitance
Blue-beam HPLDs	PL TB405B	Semiconductor laser diode Material: InGaN-base Laser emission: Blue beam. See the Table 3
Operational amplifier of SA and CLC	LM258ADR	Range of DC power supply: 3 V to 32 VOpen-loop differential voltage gain: 100 dB Unity gain bandwidth: 0.7 MHz Operational amplifier, package: SO8 Operating temperature: −40 °C to 85 °C.

.

4.3. HPLDDC Current Loop Analysis and Simulation

Parameter values of Table 2 are listed in

Table 7. Parameter values of Table 2.

Parameter	Value	Parameter	Value
rc	41 mΩ	rL	68 mΩ
Vin(max)	16 V	Co	470 μF
L1	30 μH	rhpld	0.99 Ω
Dbt	0.437

. In Table 7, substitution of V_LD1, V_LD2, I_LD1, and I_LD2 from Table 3 into (12) can yield r_hpld = 0.99 Ω. From Table 4, substation of V_o(max) = 16 V and V_in(min) = 9 V into the formula (V_o(max) − V_in(min))/V_o(max) can yield D_bt = 0.437.

To yield the d–v_cea characteristic of SBBC in the boost mode, the testing conditions were defined as V_o(max) = 16 V and V_in(min) = 9 V and, and the SBBC output current, I_o, was adjusted from 0.5 to 1.2 A; the measurement points are depicted in Figure 11a. In addition, the curve fitting function of MATLAB was used to obtain a linear polynomial, and the notation, d, was replaced with d_bt; hence, Equation (13) can be rewritten as follows:

$$d_{bt}=0.1v_{cea}+0.35$$

(19)

Similarly, to yield the d–v_cea characteristic of SBBC in the buck mode, the testing conditions were defined as V_o = 12 V and V_{in (max)} = 16 V, and the SBBC output current, I_o, was adjusted from 0.5 to 1.2 A; the measurement points are depicted in Figure 11b. In addition, the curve fitting function of MATLAB was used to obtain a linear polynomial, and d was replaced with d_bk; therefore, Equation (13) can be rewritten as follows:

$$d_{bk}=0.23v_{cea}+0.64.$$

(20)

From Equation (14), G_ctlr(s) = k_cea, and k_cea in the boost mode equals the constant 0.1 from Equation (19); hence, G_ctlr(bt) (s) = 0.1. From Equation (20), in the buck mode, G_ctlr (s) can be obtained and defined as G_ctlr(bk) (s) = 0.23.

Substitution of G_ctlr(bt) (s) = 0.1 and G_ctlr(bk) (s) = 0.23 into Equations (16) and (17), and using Matlab, frequency responses of buck and boost modes, are illustrated in Figure 12. From Figure 12, a resonant frequency point of G_op(bt) (s) was at 450 Hz; hence, the compensative crossover frequency, f_cf, must be deviated from this resonant frequency point because the resonant occurrence would cause the HPLDDC instability. Moreover, G_op(bk) (s) bandwidth (BW) was 7.7 Hz, and it should be expanded for the HPLDDC response speed promotion. In addition, in the switching-mode DC-DC converters, f_cf can be lower than the f_s/10 [24]. According to these circumstances, f_cf was 50 Hz for the HPLDDC operation.

According to Figure 12, at 50 Hz, G_op(bk) should be promoted from −5.52 to 0 dB. Therefore, the magnitude of Equation (18) can equal to a constant, 1.89 (20 log 1.89 = 5.52 dB). Moreover, g_p can be select as a suitable constant value. Hence, substitution of g_p = 2.2, |G_cea(PI)[j(2πf_cf)]| = 1.89 and f_cf = 50 Hz into Equation (18) can obtain g_i = 1.11 × 10³.

Therefore, substitution of g_i = 1.11 × 10³ and g_p = 2.2 into Equation (18) can rewire G_cea(PI) (s), whose TF can be expressed as follows:

$$G_{cea(PI)}(s)=g_p+g_i/s=2.2+1.11\times {10}^3/s.$$

(21)

In this study, the CLC TF using the PI control can adopt Equation (21). The CLC TF using the P control can employ the g_p gain from Equation (18) that is given by:

$$G_{cea(P)}(s)=g_p=2.2.$$

(22)

In Figure 9 and Figure 10, k_c is equal to g_sa × k_cv, g_sa is the SA’s amplifier gain, k_cv is the C-V converter gain. In this study, g_sa and k_cv were set as 16 and 0.05, respectively; hence k_c equaled to 0.8. Moreover, an open-loop gain G_op(btcea) (s) equaled to k_c × G_op(bt) (s) × G_cea(PI) (s). Therefore, use of the MATLAB could simulate the frequency response of G_op(btcea) (s), as shown in Figure 12b. From Figure 12b, the LFG was promoted to 38.3 dB, and the phase was −33.6° at 50 Hz. Furthermore, an open-loop gain, G_op(bkcea) (s), equaled to k_c × G_op(bk) (s) × G_cea(PI) (s). Hence, G_op(btcea) (s) simulation using the MATLAB is illustrated in Figure 12b. From Figure 12b, LFG was promoted to 44.7 dB, and the phase was −107° at 50 Hz. According to the frequency responses of G_op(btcea) (s) and G_op(bkcea) (s), the HPLDDC using the designing CLC PI control can address the system stable requirement for buck and boost operations.

Incorporating G_op(btcea) (s) with G_ss (s) of (15) and using Matlab, the simulation of HPLDDC start-up current for the boost mode is illustrated in Figure 13a. In addition, incorporating G_op(bkcea) (s) with G_ss (s) and using MATLAB, the simulation of the HPLDDC start-up current for the buck mode is illustrated in Figure 13b. Several situations can be observed in Figure 13:

1. Boost mode: No current spike occurred. The settling time was 40 ms. The final current was 1.2 A; and

2. Buck mode: Maximum start-up current peak was 1.65 A. The settling time was 230 ms. The final current was 1.2 A.

From both figures, although the final current, 1.2 A, could correspond to the specification, a start-up current spike occurred in the buck mode operation. From these simulations, several disadvantages can be identified when the CLC uses the PI control. First, the peak current of 1.65 A already overstepped the specified 1.5 A, and this situation was harmful for HPLDs. Second, although the CLC using PI control had an outstanding ability to regulate steady-state errors, the PI control caused the start-up current spike when the SBBC operated in the buck mode.

To depress the start-up current spike, the CLC using the PIAP control method was employed. Simulations are presented in Figure 14. From Figure 14, despite the SBBC operating mode, the use of P control method cannot achieve the target final current of 1.2 A.

Thus, a CLC using the PIAP control method could be adopted in the HPLDDC. Figure 14 simulations show several benefits: First, the start-up current spike mitigated effectualness. Second, no steady-state errors were achieved, and the final current could address the specified 1.2 A because the HPLDDC using CLC can become the PI control in the SBBC CCOM. Third, the settling time was reduced from 230 to 80 ms in the SBBC buck mode.

5. Experimental Results

In accordance with the system configuration in Figure 2, the HPLDDC can drive the three blue-beam HPLDs. Figure 15 and Figure 16 present the experimental waveforms, including the HPLDDC output current (HPLDs driving current), I_o, the HPLDDC input voltage, V_in, and the HPLDDC output voltage (HPLDs driving voltage), V_o.

5.1. CLC Using PI Control Method

• At a V_in of 9 V, the HPLDDC operated in the boost mode because (V_in = 9 V) < (V_o = 15 V), and a slight current spike was observed, with a peak value of 1.4 A, and the settling time was 60 ms (simulation was 40 ms), as shown in Figure 15a.
• At a V_in of 15 V, the HPPLD operated in the buck–boost mode because (V_in = 15 V) = (V_o = 15 V), and the current spike was observed, with a peak was 1.6 A, which overstepped the HPLD maximum operating current of 1.5 A (Table 3). The settling time was 260 ms, as shown in Figure 15b.
• At a V_in of 16 V, the HPPLD operated in the buck mode because (V_in = 16 V) > (V_o = 15 V), and the current spike was observed, with a peak was 1.65 A. This peak value was also over the HPLD maximum operating current of 1.5 A. Then, the settling time was 260 ms (simulation was 230 ms), as shown in Figure 15c.

Thus, the start-up current spike must be mitigated, and it should be lower than the HPLD maximum operating current of 1.5 A.

5.2. CLC Using PIAP Control Method

• At a V_in of 9 V, the HPPLD operated the in the boost mode, and a slight current spike with a peak value of 1.25 A was observed. The settling time was 65 ms (simulation was 40 ms), as shown in Figure 16a.
• At a V_in of 15 V, the HPPLD operated in the buck–boost mode, a slight current spike was observed, with a peak of 1.3 A, which was lower than the HPLD maximum operating current of 1.5 A. The settling time was 100 ms, as shown in Figure 16b.
• At a V_in of 16 V, the HPPLD operated in the buck mode, and a slight current spike with a peak of 1.3 A was observed. This peak value was also lower than 1.5 A. The settling time was 80 ms (simulation was 80 ms), as shown in Figure 16c.

Therefore, the start-up current spike could be mitigated, and the current settling time could be obviously reduced, when the CLC used the PIAP control technology.

A photograph of the HPLDDC system is presented in Figure 17, including three HPLDs’ heat sinks, three heat-sink struts, a lead-acid battery, and a print circuit board assembly of the HPLDDC. The lead-acid battery could supply to the HPLDDC to drive HPLDs, and then laser blue beams were produced.

6. Conclusions

This study developed and implemented an HPLDDC to drive three blue-beam HPLDs. An SBBC was employed as the power converter, which implemented the boost, buck, or buck–boost operation, to deal with the variable on-board battery voltages. In addition, the soft-start control was used to reduce the voltage spike in the start-up transient phase; however, this soft-start control method was incapable of handling the start-up current spike problem when the SBBC operated in the buck mode. Therefore, the proposed PIAP control technology could be applied in the CLC, which accomplished the following results: First, the PIAP control incorporated the P with the PI control to reduce the start-up current spike, and to abridge the settling time of the start-up current. Second, in the HPLDDC CCOM, the PIAP control can become the PI control to obtain the required stabilities, low steady-state errors, and sufficient phase margins. Third, the compensation parameters of the CLC were not required to be modified for the proposed PIAP control method. Finally, the CLC using the PIAP control technology was suitable in the current loop control of SBBC for accomplishing the HPLDDC CC operation.