Start-Up Current Spike Mitigation of High-Power Laser Diode Driving Controller for Vehicle Headlamp Applications

Kai-Jun Pai 1,* ID , Lin-De Qin 2, Chang-Hua Lin 3 and Sheng-Yi Tang 4 1 Department of Electrical Engineering, Ming Chi University of Technology, New Taipei City 24301, Taiwan 2 Department of Electrical Engineering, Tungnan University, New Taipei City 22202, Taiwan; show9051649@gmail.com 3 Department of Electrical Engineering, National Taiwan University of Science and Technology, Taipei City 10607, Taiwan; link@mail.ntust.edu.tw 4 Department of Power Mechanical Engineering, National Formosa University, Huwei Town, Yunlin County 63201, Taiwan; arthurta@nfu.edu.tw * Correspondence: carypai@mail.mcut.edu.tw; Tel.: +886-2-2908-9899 (ext. 4849)


Introduction
As semiconductor technology continues to develop and innovate, the uses of electronic devices and elements in the on-board parts of vehicles or electric cars are progressively increasing.Twin headlamps in the front end of vehicles, including the blink lights, low beam lights, and high beam lights, are applied to cope with different traffic circumstances.In vehicle headlamps, incandescent halogen lamps have been replaced with optoelectronic semiconductors (OPSs) in a new generation of cars, due to their benefits such as direct-current (DC) driving, high brightness, high efficiency of power conversion, and outstanding color rendering [1][2][3][4][5][6].In addition, when motor vehicles are driven in road tunnels or on roadways in the night, the headlamp irradiation ranges can be expanded using high beam lights, the brightness of which settles on metal halide high-intensity discharge (HID) lamps.However, several negative characteristics of HID lamps should be contemplated, including alternating-current (AC) power driving, AC high-voltage start-up, and negative resistance characteristic; thus, electronic ballasts can be used to stabilize the brightness and driving current of HID lamps [7][8][9].
The abbreviation, laser, is an acronym for light amplification by stimulated emission of radiation.According to laser oscillator configurations, laser devices can be classified based on the various materials used for construction, such as solid-state laser, gas laser, semiconductor laser, and fiber laser.Figure 1a is a simple model of the semiconductor laser, whose active layer is embedded in between the p-type and n-type materials.The p-type Gallium Nitride (p-GaN ) can be a positive electrode, and the n-type Gallium Nitride (n-GaN) contact can be a negative electrode.When the laser diode (LD) is excited, the active layer can emit laser beams, which can be amplified using the mirror surfaces to emit laser beams [10].When voltage from a power source is applied to the positive-negative electrode and the laser diode operates in the forward bias, the electrons are injected into the active layer from the n-type semiconductor; the wide band gap of the heterojunction can limit the amount of electron combinations in the active layer, and, through this carrier confinement, the population inversion probabilities can be substantially increased to promote high-intensity light emission [11], as shown in Figure 1b.In addition, the semiconductor laser possesses several exceptional characteristics, including monochromaticity, high directionality, high coherence, and high energy density.Thus, motor vehicle manufacturers have started to develop the high beam light of high brightness based on the high-power laser diode (HPLD).
Appl.Sci.2018, 8, 1532 2 of 19 expanded using high beam lights, the brightness of which settles on metal halide high-intensity discharge (HID) lamps.However, several negative characteristics of HID lamps should be contemplated, including alternating-current (AC) power driving, AC high-voltage start-up, and negative resistance characteristic; thus, electronic ballasts can be used to stabilize the brightness and driving current of HID lamps [7][8][9].The abbreviation, laser, is an acronym for light amplification by stimulated emission of radiation.According to laser oscillator configurations, laser devices can be classified based on the various materials used for construction, such as solid-state laser, gas laser, semiconductor laser, and fiber laser.Figure 1a is a simple model of the semiconductor laser, whose active layer is embedded in between the p-type and n-type materials.The p-type Gallium Nitride (p-GaN ) can be a positive electrode, and the n-type Gallium Nitride (n-GaN) contact can be a negative electrode.When the laser diode (LD) is excited, the active layer can emit laser beams, which can be amplified using the mirror surfaces to emit laser beams [10].When voltage from a power source is applied to the positive-negative electrode and the laser diode operates in the forward bias, the electrons are injected into the active layer from the n-type semiconductor; the wide band gap of the heterojunction can limit the amount of electron combinations in the active layer, and, through this carrier confinement, the population inversion probabilities can be substantially increased to promote high-intensity light emission [11], as shown in Figure 1b.In addition, the semiconductor laser possesses several exceptional characteristics, including monochromaticity, high directionality, high coherence, and high energy density.Thus, motor vehicle manufacturers have started to develop the high beam light of high brightness based on the high-power laser diode (HPLD).In this study, the HPLD of InGaN-based blue beam was used as the illuminant sources for vehicle headlamps.Due to the optical output power (OOP) of HPLD being directly proportional to its forward operating current [12], the HPLDs must be driven by a constant-current (CC).Therefore, the design of high-power laser diode driving controller (HPLDDC) requires a current-loop controller (CLC) and a voltage-loop controller (VLC) to manipulate the HPLDDC, achieving the constant-current output mode (CCOM) and constant-voltage output mode (CVOM), and the CLC and VLC can apply the proportional-integral (PI) control to accomplish the low steady-state error and system stable requirement.The PI control has excellent behavior in the low steady-state error; however, the tardy response speed of PI control can result in the current spike problem and the long settling time during the HPLDDC start-up transient phase.Therefore, studies [13][14][15] have proposed the use of dual control loops, including the proportional (P) control and PI control, in which the P control can promote transient responses, and the dual control loops combined a P In this study, the HPLD of InGaN-based blue beam was used as the illuminant sources for vehicle headlamps.Due to the optical output power (OOP) of HPLD being directly proportional to its forward operating current [12], the HPLDs must be driven by a constant-current (CC).Therefore, the design of high-power laser diode driving controller (HPLDDC) requires a current-loop controller (CLC) and a voltage-loop controller (VLC) to manipulate the HPLDDC, achieving the constant-current output mode (CCOM) and constant-voltage output mode (CVOM), and the CLC and VLC can apply the proportional-integral (PI) control to accomplish the low steady-state error and system stable requirement.The PI control has excellent behavior in the low steady-state error; however, the tardy response speed of PI control can result in the current spike problem and the long settling time during the HPLDDC start-up transient phase.Therefore, studies [13][14][15] have proposed the use of dual control loops, including the proportional (P) control and PI control, in which the P control can promote transient responses, and the dual control loops combined a P control loop with a PI control loop to reduce steady-state errors; thus, the system can address the requirements of transient responses and steady-state stability.However, the implementations of dual control loops with P and PI controls in the HPLDDC are too complex.Therefore, this study employed a control method, proportional-integral, associating proportional (PIAP) control, to depress the start-up current spikes.
An HPLDDC was implemented and developed in this study to drive blue beam HPLDs as the illuminant source for motor vehicle headlamps.Because the on-bard battery was used as the HPLDDC's input power and the battery voltage varied during charging or discharging, a synchronous buck-boost converter (SBBC) was applied as the power converter of HPLDDC.In addition, SBBC's CCOM or CVOM operation could be implemented through the CLC or VLC manipulation.During the HPLDDC start-up transient phase, when the HPLDDC changed its output mode from the CVOM to CCOM, the CLC adopting the PIAP control was effectual for the start-up current spike depressing.Six sections are presented in this paper.SBBC principles and analyses are presented in Section 2. The PIAP control method to solve the start-up current problem is explained and analyzed in Section 3. Section 4 includes design considerations, analyses, and simulations for the HPLDDC current loop.In Section 5, experimental waveforms can confirm that the PIAP control is efficacious.Section 6 is this study's conclusions.

Power Converter Principle
The HPLDDC system configuration is depicted in Figure 2, including the CVOM and CCOM controllers, a DC-DC convertor, and safety standard components.The on-board battery supplies a DC-power to the HPLDDC inlet; the HPLDDC outlet connects three HPLDs in series.To protect the SBBC, CVOM, and CCOM controllers, the SBBC input side must place safety standard components because voltage impulses and spikes or EMI/EMC noises from the battery power bus can be filtered out.In addition, the DC-DC converter topology is the SBBC; an SBBC circuit is shown in Figure 3; this circuit composition includes an output capacitor, C o , power switches, Q 1 -Q 4 , and an inductor, L 1 .Principles and analyses in the buck and boost modes are discussed in the following.control loop with a PI control loop to reduce steady-state errors; thus, the system can address the requirements of transient responses and steady-state stability.However, the implementations of dual control loops with P and PI controls in the HPLDDC are too complex.Therefore, this study employed a control method, proportional-integral, associating proportional (PIAP) control, to depress the start-up current spikes.
An HPLDDC was implemented and developed in this study to drive blue beam HPLDs as the illuminant source for motor vehicle headlamps.Because the on-bard battery was used as the HPLDDC's input power and the battery voltage varied during charging or discharging, a synchronous buck-boost converter (SBBC) was applied as the power converter of HPLDDC.In addition, SBBC's CCOM or CVOM operation could be implemented through the CLC or VLC manipulation.During the HPLDDC start-up transient phase, when the HPLDDC changed its output mode from the CVOM to CCOM, the CLC adopting the PIAP control was effectual for the start-up current spike depressing.Six sections are presented in this paper.SBBC principles and analyses are presented in Section 2. The PIAP control method to solve the start-up current problem is explained and analyzed in Section 3. Section 4 includes design considerations, analyses, and simulations for the HPLDDC current loop.In Section 5, experimental waveforms can confirm that the PIAP control is efficacious.Section 6 is this study's conclusions.

Power Converter Principle
The HPLDDC system configuration is depicted in Figure 2, including the CVOM and CCOM controllers, a DC-DC convertor, and safety standard components.The on-board battery supplies a DC-power to the HPLDDC inlet; the HPLDDC outlet connects three HPLDs in series.To protect the SBBC, CVOM, and CCOM controllers, the SBBC input side must place safety standard components because voltage impulses and spikes or EMI/EMC noises from the battery power bus can be filtered out.In addition, the DC-DC converter topology is the SBBC; an SBBC circuit is shown in Figure 3; this circuit composition includes an output capacitor, Co, power switches, Q1-Q4, and an inductor, L1.Principles and analyses in the buck and boost modes are discussed in the following.

Buck Mode Principle
In the buck operation, power switches, Q1-Q4, (Figure 3) are replaced with power metal-oxide-semiconductor field-effect transistors (MOSFETs); the synchronous buck circuit with the operating timing is presented in Figure 4.In Figure 4a, vgs1-vgs4 are the MOSFET gate-to-source pulse width modulation (PWM) driving signals, and iL represents the inductor current.When the SBBC input voltage, Vin, is greater than the HPLDDC output voltage, Vo (Vin > Vo), vgs4 is at the high-voltage level, and, consequently, the MOSFET Q4 is always turned on; vgs3 is always at the low-voltage level to turn off the MOSFET Q3.The time intervals, tk0-tk1 and tk2-tk3, are dead times that can prevent MOSFETs Q1 and Q2 from concurrently turning on and becoming a short-circuit.vgs2 is changed to the high-voltage level during the time interval, tk1-tk2, thereby decreasing iL. Figure 4b presents the operating circuit during the time interval, tk0-tk2.When iL is lower than the current command inside the SBBC controller at tk2, vgs2 is changed to the low-voltage level, thus, turning off Q2, and vgs1 is changed to the high-voltage level at tk3, thus, increasing iL.The operating circuit during the time interval, tk3-tk4, is depicted in Figure 4c.When iL is greater than the current command inside the SBBC controller at tk4, vgs1 is changed to the low-voltage level, thus, turning off Q1.

Buck Mode Principle
In the buck operation, power switches, Q 1 -Q 4 , (Figure 3) are replaced with power metal-oxidesemiconductor field-effect transistors (MOSFETs); the synchronous buck circuit with the operating timing is presented in Figure 4.In Figure 4a, v gs1 -v gs4 are the MOSFET gate-to-source pulse width modulation (PWM) driving signals, and i L represents the inductor current.When the SBBC input voltage, V in , is greater than the HPLDDC output voltage, V o (V in > V o ), v gs4 is at the high-voltage level, and, consequently, the MOSFET Q 4 is always turned on; v gs3 is always at the low-voltage level to turn off the MOSFET Q 3 .The time intervals, t k0 -t k1 and t k2 -t k3 , are dead times that can prevent MOSFETs Q 1 and Q 2 from concurrently turning on and becoming a short-circuit.v gs2 is changed to the high-voltage level during the time interval, t k1 -t k2 , thereby decreasing i L . Figure 4b presents the operating circuit during the time interval, t k0 -t k2 .

Buck Mode Principle
In the buck operation, power switches, Q1-Q4, (Figure 3) are replaced with power metal-oxide-semiconductor field-effect transistors (MOSFETs); the synchronous buck circuit with the operating timing is presented in Figure 4.In Figure 4a, vgs1-vgs4 are the MOSFET gate-to-source pulse width modulation (PWM) driving signals, and iL represents the inductor current.When the SBBC input voltage, Vin, is greater than the HPLDDC output voltage, Vo (Vin > Vo), vgs4 is at the high-voltage level, and, consequently, the MOSFET Q4 is always turned on; vgs3 is always at the low-voltage level to turn off the MOSFET Q3.The time intervals, tk0-tk1 and tk2-tk3, are dead times that can prevent MOSFETs Q1 and Q2 from concurrently turning on and becoming a short-circuit.vgs2 is changed to the high-voltage level during the time interval, tk1-tk2, thereby decreasing iL. Figure 4b presents the operating circuit during the time interval, tk0-tk2.When iL is lower than the current command inside the SBBC controller at tk2, vgs2 is changed to the low-voltage level, thus, turning off Q2, and vgs1 is changed to the high-voltage level at tk3, thus, increasing iL.The operating circuit during the time interval, tk3-tk4, is depicted in Figure 4c.When iL is greater than the current command inside the SBBC controller at tk4, vgs1 is changed to the low-voltage level, thus, turning off Q1.When i L is lower than the current command inside the SBBC controller at t k2 , v gs2 is changed to the low-voltage level, thus, turning off Q 2 , and v gs1 is changed to the high-voltage level at t k3 , thus, increasing i L .The operating circuit during the time interval, t k3 -t k4 , is depicted in Figure 4c.When i L is greater than the current command inside the SBBC controller at t k4 , v gs1 is changed to the low-voltage level, thus, turning off Q 1 .

Boost Mode Principle
Figure 5 illustrates the synchronous boost circuit and the timing chart.When V in is lower than V o (V in < V o ) throughout the operation, v gs1 is at the high-voltage level to turn on Q 1 , and v gs2 is at the low-voltage level to turn off Q 2 .Both the time intervals, t t0 -t t1 and t t2 -t t3 , are dead times that can prevent Q 3 and Q 4 from concurrently turning on and causing the short-circuit.v gs3 is changed to the high-voltage level during the time interval, t t1 -t t2 , thus, increasing i L ; the operating circuit in the time interval, t t1 -t t2 , is depicted in Figure 5b.At t t2 , because i L is greater than the current command inside the SBBC controller, v g3 is changed to the low-voltage level, thus, turning off Q 3 .In the time interval, t t3 -t t4 , v g4 is at the high-voltage level and Q 4 is turned on, hence, decreasing i L ; the operating circuit during t t3 -t t4 is depicted in Figure 5c.When i L is lower than the current command inside the SBBC controller at time, t t4 , v gs4 is changed to the low-voltage level, thus, turning off Q 4 .
Appl.Sci.2018, 8, 1532 5 of 19 Figure 5 illustrates the synchronous boost circuit and the timing chart.When Vin is lower than Vo (Vin < Vo) throughout the operation, vgs1 is at the high-voltage level to turn on Q1, and vgs2 is at the low-voltage level to turn off Q2.Both the time intervals, tt0-tt1 and tt2-tt3, are dead times that can prevent Q3 and Q4 from concurrently turning on and causing the short-circuit.vgs3 is changed to the high-voltage level during the time interval, tt1-tt2, thus, increasing iL; the operating circuit in the time interval, tt1-tt2, is depicted in Figure 5b.At tt2, because iL is greater than the current command inside the SBBC controller, vg3 is changed to the low-voltage level, thus, turning off Q3.In the time interval, tt3-tt4, vg4 is at the high-voltage level and Q4 is turned on, hence, decreasing iL; the operating circuit during tt3-tt4 is depicted in Figure 5c.When iL is lower than the current command inside the SBBC controller at time, tt4, vgs4 is changed to the low-voltage level, thus, turning off Q4.

Designs of Output Capacitor and Inductor
Because the SBBC was the topology of the power converter, which can implement the buck or boost mode, the output capacitor and inductor should be computed to address the practical circuit application.The calculating formulas and explanations are in the following sections.

SBBC Inductor for Buck Mode
In accordance with the study [14], the inductor for the SBBC's buck mode operation can be estimated as follows: The notation, L1, (Figure 3) can be replaced with Lbk.∆i L is the inductor peak current that can be estimated using the βIo, β is the percent from the peak-to-peak inductor current, and Io is the HPLDDC output current.Dbk is the duty cycle of the buck mode that can be estimated using the Vo(min)/Vin(max), Vo(min) is the HPLDDC minimum output voltage, and Vo(max) is the HPLDDC maximum output voltage.fs is the switching frequency of Q1-Q4.Substitution of ∆i L = βIo and Dbk = Vo(min)/Vin(max) into (1) can rewrite the equation as follows: 2.3.2.SBBC Inductor for Boost Mode (c) operating circuit in t t3 -t t4 .

Designs of Output Capacitor and Inductor
Because the SBBC was the topology of the power converter, which can implement the buck or boost mode, the output capacitor and inductor should be computed to address the practical circuit application.The calculating formulas and explanations are in the following sections.

SBBC Inductor for Buck Mode
In accordance with the study [14], the inductor for the SBBC's buck mode operation can be estimated as follows: The notation, L 1 , (Figure 3) can be replaced with L bk .∆i L is the inductor peak current that can be estimated using the βI o , β is the percent from the peak-to-peak inductor current, and I o is the HPLDDC output current.D bk is the duty cycle of the buck mode that can be estimated using the V o(min) /V in(max) , V o(min) is the HPLDDC minimum output voltage, and V o(max) is the HPLDDC maximum output voltage. 1) can rewrite the equation as follows: (2)

SBBC Inductor for Boost Mode
In accordance with the study [16], the inductor for the SBBC's boost mode operation can be estimated as follows: L 1 can be replaced with L bt , D bt is the duty cycle of the boost mode that can be estimated using 3) can rewrite the equation as follows: (4)

SBBC Output Capacitor
In accordance with the study [16], the SBBC output capacitor (Figure 3) can be estimated as follows: where D represents the duty cycle from D bk or D bt .∆v o is the HPLDDC output ripple voltage that can be estimated using V o(min) , and the ripple voltage peak can be defined by a percentage, α.R o is the output equivalent resistance at the HPLDDC output side.
In addition, an effective series resistance (ESR) parasitizes on C o that can be expressed as follows [17]: where I in(peak) is the peak value of the HPLDDC input current.According to I o /I in = 1/D bk , I in(peak) can be estimated as I o D bk (1+β).

• SBBC Output Capacitor for Buck Mode
For the buck mode, the notation C o in Equation ( 5) can be replaced with C obk .Substitution of , and ∆v o = αV o(min) into Equation ( 5) obtains the output capacitor of the buck mode operation as follows: ESR in Equation ( 6) is replaced with ESR bk .Substitution of ∆v o = αV o(min) and D bk = V o(min) /V in(max) into Equation ( 6) can rewrite the equation as follows: • SBBC Output Capacitor for Boost Mode For the boost mode, C o can be replaced with C obt .Substitution of 5) can obtain the output capacitor of the boost mode as follows: ESR is replaced with ESR bt .Substitution of ∆v o = αV o(min) and 6) can rewrite the equation as follows:

HPLDDC Control Loop
Figure 6 depicts the ideal voltage-current characteristic of LD; V LDF is the forward voltage of LD and a slight current (approximating to no current) flows if the LD driving voltage is lower than V LDF .Without any driving devices to regulate the LD driving current, if the LD driving voltage is higher than V LDF , more current is indispensable to drive the LD strengthening the laser beams, and the driving current can be increased exponentially.Because the constant OOP originates from a stable LD driving current, the LD can be driven by a CC output power supply, or regulated by a CC sink.Several control methods for the LD driving are discussed in the following section.

Constant-Current Sink Control
The optoelectronic semiconductor (OPS) including the light-emitting diode (LED), the organic light-emitting diode (OLED), and the LD, should be driven by a CC to obtain a constant OOP or luminance.Figure 7 presents a familiar OPS control circuit that includes the lighting driver, OPSs, and the current regulator (CR).To control the constant driving current in OPSs, a CR comprising an operational amplifier (OPA), a transistor, and a current-voltage (C-V) converter, is the critical circuit because the CR can be considered as a current sink; when the OPS operates in the forward bias, the OPS driving current If sinks into the transistor, and then If can be converted by the C-V converter becoming a voltage VIf; therefore, the transistor can be considered as a variable resistance for adjusting the If because the OPA compares the VIf with a CC command to control the transistor's operating region [18,19].However, the CR is unable to address less steady-state errors and sufficient phase margins.Moreover, the lighting driver is a constant-voltage (CV) power source, and although the CC can be achieved using the CR; however, the transistor's equivalent resistance would cause the power loss and heating.Therefore, the CR is unsuitable for the high-power OPS control.

Constant-Current Source Driving and CLC Using PI Control
To supply a CV or CC DC-power to drive HPLDs, CVOM and CCOM controllers play a critical role in dominating HPLDDC operations.In Figure 2, CVOM and CCOM controllers comprise a SBBC controller, a C-V converter, a voltage divider, a signal amplifier (SA), and a CLC.As shown in Figure 8, to accomplish the HPLDDC's CVOM, the voltage divider detects Vo to output a voltage Vos, and then the VLC of SBBC controller can obey Vos to produce an error voltage to manipulate the PWM module.Therefore, the HPLDDC can be controlled in the CVOM to supply the adequate and stable forward voltage driving HPLDs.In addition, in the HPLDDC's CCOM, the HPLD driving current can be detected by the C-V converter to become a voltage signal, and then the SA can

Constant-Current Sink Control
The optoelectronic semiconductor (OPS) including the light-emitting diode (LED), the organic light-emitting diode (OLED), and the LD, should be driven by a CC to obtain a constant OOP or luminance.Figure 7 presents a familiar OPS control circuit that includes the lighting driver, OPSs, and the current regulator (CR).To control the constant driving current in OPSs, a CR comprising an operational amplifier (OPA), a transistor, and a current-voltage (C-V) converter, is the critical circuit because the CR can be considered as a current sink; when the OPS operates in the forward bias, the OPS driving current I f sinks into the transistor, and then I f can be converted by the C-V converter becoming a voltage V If ; therefore, the transistor can be considered as a variable resistance for adjusting the I f because the OPA compares the V If with a CC command to control the transistor's operating region [18,19].However, the CR is unable to address less steady-state errors and sufficient phase margins.Moreover, the lighting driver is a constant-voltage (CV) power source, and although the CC can be achieved using the CR; however, the transistor's equivalent resistance would cause the power loss and heating.Therefore, the CR is unsuitable for the high-power OPS control.

Constant-Current Sink Control
The optoelectronic semiconductor (OPS) including the light-emitting diode (LED), the organic light-emitting diode (OLED), and the LD, should be driven by a CC to obtain a constant OOP or luminance.Figure 7 presents a familiar OPS control circuit that includes the lighting driver, OPSs, and the current regulator (CR).To control the constant driving current in OPSs, a CR comprising an operational amplifier (OPA), a transistor, and a current-voltage (C-V) converter, is the critical circuit because the CR can be considered as a current sink; when the OPS operates in the forward bias, the OPS driving current If sinks into the transistor, and then If can be converted by the C-V converter becoming a voltage VIf; therefore, the transistor can be considered as a variable resistance for adjusting the If because the OPA compares the VIf with a CC command to control the transistor's operating region [18,19].However, the CR is unable to address less steady-state errors and sufficient phase margins.Moreover, the lighting driver is a constant-voltage (CV) power source, and although the CC can be achieved using the CR; however, the transistor's equivalent resistance would cause the power loss and heating.Therefore, the CR is unsuitable for the high-power OPS control.

Constant-Current Source Driving and CLC Using PI Control
To supply a CV or CC DC-power to drive HPLDs, CVOM and CCOM controllers play a critical role in dominating HPLDDC operations.In Figure 2, CVOM and CCOM controllers comprise a SBBC controller, a C-V converter, a voltage divider, a signal amplifier (SA), and a CLC.As shown in Figure 8, to accomplish the HPLDDC's CVOM, the voltage divider detects Vo to output a voltage Vos, and then the VLC of SBBC controller can obey Vos to produce an error voltage to manipulate the PWM module.Therefore, the HPLDDC can be controlled in the CVOM to supply the adequate and stable forward voltage driving HPLDs.In addition, in the HPLDDC's CCOM, the HPLD driving current can be detected by the C-V converter to become a voltage signal, and then the SA can

Constant-Current Source Driving and CLC Using PI Control
To supply a CV or CC DC-power to drive HPLDs, CVOM and CCOM controllers play a critical role in dominating HPLDDC operations.In Figure 2, CVOM and CCOM controllers comprise a SBBC controller, a C-V converter, a voltage divider, a signal amplifier (SA), and a CLC.As shown in Figure 8, to accomplish the HPLDDC's CVOM, the voltage divider detects V o to output a voltage V os , and then the VLC of SBBC controller can obey V os to produce an error voltage to manipulate the PWM module.Therefore, the HPLDDC can be controlled in the CVOM to supply the adequate and stable forward voltage driving HPLDs.In addition, in the HPLDDC's CCOM, the HPLD driving current can be detected by the C-V converter to become a voltage signal, and then the SA can amplify this voltage signal becoming a current detection signal V is .According to the V is variation, an error voltage V cea can be produced by the CLC to manipulate the SBBC controller accomplishing the HPLDDC CCOM.Both start-up voltage and current spikes are pernicious to the HPLD's semiconductor material.The start-up voltage spike can be solved using the soft-start module (Figure 8).Moreover, the integral action of the PI control causes the start-up current spike; thus, when the SBBC output mode is changed from CVOM to CCOM, the HPLD driving current should avoid the start-up current spike occurrence.

.Constant-Current Source Driving and CLC Using PIAP Control
A circuit configuration diagram of CLC using the PIAP control is depicted in Figure 9.In Figure 9b, during Phase I, the HPLDDC is dominated by the VLC and the soft-start module of the SBBC controller, and then Vo can slowly increase to avoid the voltage overshoot occurrence.When the Io increase has reached a current value of I1, a switch, st, (Figure 9a) connects to the position, s1; thus, the CLC can implement P control during Phase II (Figure 9b), hence, the response speed of CLC can be promoted to mitigate the start-up current spike.In Phase III, Io has reached the target CC Icc, the st connects to the position, s2, and then the CLC uses the PI control to regulate the HPLD driving current in the CC state.The aforementioned three CC control methods can be compared and are listed in Table 1.
The transfer function (TF) of the duty cycle to the SBBC output current for the buck or boost operation can refer to studies [20,21]; both models have been derived based on a PWM switch model technology from previous studies [16,22,23].Therefore, the SBBC transfer function is defined as follows: According to the buck or boost operation of SBBC, these parameters in (11) are listed in Table 2.In Table 2, rc represents the capacitor's ESR.rL represents the inductor's wire-wind resistance.rhpld represents the HPLDs' equivalent dynamic resistor, which can be calculated as: where VLD1 and VLD2 are HPLDs' operating forward voltages, and ILD1 and ILD2 are HPLDs' operating forward currents.The current-loop control block diagram of FSBBC is illustrated in Figure 10.In Figure 10, the FSBBC gain is Gkt, the FSBBC controller gain is Gctlr, the CLC gain using the P control is Gcea(P), the CLC gain using the PI control is Gcea(PI), and a feedback gain is a constant, kc.In addition, the soft-start Both start-up voltage and current spikes are pernicious to the HPLD's semiconductor material.The start-up voltage spike can be solved using the soft-start module (Figure 8).Moreover, the integral action of the PI control causes the start-up current spike; thus, when the SBBC output mode is changed from CVOM to CCOM, the HPLD driving current should avoid the start-up current spike occurrence.

Constant-Current Source Driving and CLC Using PIAP Control
A circuit configuration diagram of CLC using the PIAP control is depicted in Figure 9.In Figure 9b, during Phase I, the HPLDDC is dominated by the VLC and the soft-start module of the SBBC controller, and then V o can slowly increase to avoid the voltage overshoot occurrence.When the I o increase has reached a current value of I 1 , a switch, st, (Figure 9a) connects to the position, s 1 ; thus, the CLC can implement P control during Phase II (Figure 9b), hence, the response speed of CLC can be promoted to mitigate the start-up current spike.In Phase III, I o has reached the target CC I cc , the st connects to the position, s 2 , and then the CLC uses the PI control to regulate the HPLD driving current in the CC state.The aforementioned three CC control methods can be compared and are listed in Table 1.
The transfer function (TF) of the duty cycle to the SBBC output current for the buck or boost operation can refer to studies [20,21]; both models have been derived based on a PWM switch model technology from previous studies [16,22,23].Therefore, the SBBC transfer function is defined as follows: According to the buck or boost operation of SBBC, these parameters in (11) are listed in Table 2.In Table 2, r c represents the capacitor's ESR.r L represents the inductor's wire-wind resistance.r hpld represents the HPLDs' equivalent dynamic resistor, which can be calculated as: where V LD1 and V LD2 are HPLDs' operating forward voltages, and I LD1 and I LD2 are HPLDs' operating forward currents.
function would affect the start-up current spike, hence, it should be considered; Gss represents the soft-start control gain.
Despite whether the SBBC controller implements the buck or boost control, a linear polynomial of the d-vcea characteristic is expressed as follows: where d is the PWM duty cycle that incorporates the large-signal, D, with the small-signal, d ~. v'cea is the CLC output voltage that incorporates the large-signal, V'cea, with the small-signal, cea ' v ~.Both kcea and r are constants.Substitution of into Equation (13), results in the SBBC controller TF being expressed as follows: The current-loop control block diagram of FSBBC is illustrated in Figure 10.In Figure 10, the FSBBC gain is G kt , the FSBBC controller gain is G ctlr , the CLC gain using the P control is G cea(P) , the CLC gain using the PI control is G cea(PI) , and a feedback gain is a constant, k c .In addition, the soft-start function would affect the start-up current spike, hence, it should be considered; G ss represents the soft-start control gain.
Despite whether the SBBC controller implements the buck or boost control, a linear polynomial of the d-v cea characteristic is expressed as follows: where d is the PWM duty cycle that incorporates the large-signal, D, with the small-signal, d. v' cea is the CLC output voltage that incorporates the large-signal, V' cea , with the small-signal, v cea .Both k cea and r are constants.Substitution of d = D + d and v' cea = V' cea + v cea into Equation (13), results in the SBBC controller TF being expressed as follows: The v cea can exponentially increase in the start-up transient phase to accomplish the soft-start control for the CLC output voltage, v' cea ; hence, the TF of the soft-start control can be expressed as follows: Appl.Sci.2018, 8, 1532 10 of 19 The vcea can exponentially increase in the start-up transient phase to accomplish the soft-start control for the CLC output voltage, v'cea; hence, the TF of the soft-start control can be expressed as follows: From Figure 10, open-loop TFs Gop(bt) (s) and Gop(bk) (s) can be obtained using ( 11) and ( 14), which can be expressed as follows: Gop(bt) (s) = Gctlr(bt)(s) Gkt(bt) (s), ( 16) where Gkt(bt) (s) and Gctlr(bt) (s) are the SBBC TF and SBBC controller in the boost mode operation.Gkt(bk) (s) and Gctlr(bk) (s) are in the buck mode operation.By substituting Equations ( 16) and ( 17), and using the MATLAB software, the frequency response to design the CLC for the current loop compensation of HPLDDC can be obtained.Therefore, the HPLDDC requirements for the steady-state operation, including an adequate phase margin, a high low-frequency gain (LFG), and a feasible crossover frequency, can be achieved.The TF of the CLC using the PI control is expressed as follows: where gi and gp are the integral and proportional gains.

Design Consideration and Simulation
In this study, the PL TB405B is HPLD type-number (Osram Opto Semiconductors Inc., Regensburg, Germany).Its specification is listed in Table 3 from the datasheet [12].From Figure 10, open-loop TFs G (s) and G op(bk) (s) can be obtained using ( 11) and ( 14), which can be expressed as follows: where G kt(bt) (s) and G ctlr(bt) (s) are the SBBC TF and SBBC controller in the boost mode operation.G kt(bk) (s) and G ctlr(bk) (s) are in the buck mode operation.By substituting Equations ( 16) and ( 17), and using the MATLAB software, the frequency response to design the CLC for the current loop compensation of HPLDDC can be obtained.Therefore, the HPLDDC requirements for the steady-state operation, including an adequate phase margin, a high low-frequency gain (LFG), and a feasible crossover frequency, can be achieved.The TF of the CLC using the PI control is expressed as follows: where g i and g p are the integral and proportional gains.

Design Consideration and Simulation
In this study, the PL TB405B is the HPLD type-number (Osram Opto Semiconductors Inc., Regensburg, Germany).Its specification is listed in Table 3 from the datasheet [12].
As shown in Figure 2, at the HPLDDC input side, the minimum input voltage, V in(min), and the maximum input voltage, V in(max) , from the on-board batter were set as 9 and 16 V; at the HPLDDC output side, three blue-beam HPLDs were series connections, and the HPLD's forward voltage was 14.4 V from V LD2 in Table 3.Hence, the minimum output voltage of HPLDDC V o(min) was set as 13 V, and the maximum output voltage of HPLDDC V o(max) was set as 16 V.The HPLDDC output current, I o , was 1.2 A for the CC operation.In addition, the switching frequency of Q 1 −Q 4 (Figure 3) f s was 400 kHz.α was set as 1%, and β was set as 20%.These parameters and specifications are listed in Table 4.

Depiction Specification
Operating forward voltage (V LD1 ) at the operating forward current I LD1 = 0.9 A 4.7 V Operating forward voltage (V LD2 ) at the operating forward current I LD2 = 1.
The power converter topology was the SBBC, which could be operated in both buck and boost conversion modes, when variable battery voltages input to the HPLDDC.In different input and output voltages, the SBBC operating mode can be changed by the SBBC controller.To ensure the estimating inductor and output capacitor can address the buck and boost operating modes in practical applications, this study provides the design considerations and calculating rule to obtain the single element value for the SBBC circuit assembly.

Circuit Element Type-Number Specification
Maximum drain-source voltage is 60 V Drain-source turning on resistance is 26 mΩ Drain current is 7 A at 25

HPLDDC Current Loop Analysis and Simulation
Parameter values of Table 2 are listed in Table 7.In Table 7, substitution of V LD1 , V LD2 , I LD1 , and I LD2 from Table 3 into (12) can yield r hpld = 0.99 Ω.From Table 4, substation of V o(max) = 16 V and V in(min) = 9 V into the formula (V o(max) − V in(min) )/V o(max) can yield D bt = 0.437.To yield the d-v cea characteristic of SBBC in the boost mode, the testing conditions were defined as V o(max) = 16 V and V in(min) = 9 V and, and the SBBC output current, I o , was adjusted from 0.5 to 1.2 A; the measurement points are depicted in Figure 11a.In addition, the curve fitting function of MATLAB was used to obtain a linear polynomial, and the notation, d, was replaced with d bt ; hence, Equation ( 13) can be rewritten as follows: Similarly, to yield the d-v cea characteristic of SBBC in the buck mode, the testing conditions were defined as V o = 12 V and V in (max) = 16 V, and the SBBC output current, I o , was adjusted from 0.5 to 1.2 A; the measurement points are depicted in Figure 11b.In addition, the curve fitting function of MATLAB was used to obtain a linear polynomial, and d was replaced with d bk ; therefore, Equation ( 13) can be rewritten as follows: From Equation ( 14), G ctlr (s) = k cea , and k cea in the boost mode equals the constant 0.1 from Equation (19); hence, G ctlr(bt) (s) = 0.1.From Equation (20), in the buck mode, G ctlr (s) can be obtained and defined as G ctlr(bk) (s) = 0.23.From Equation ( 14), Gctlr(s) = kcea, and kcea in the boost mode equals the constant 0.1 from Equation ( 19); hence, Gctlr(bt) (s) = 0.1.From Equation (20), in the buck mode, Gctlr (s) can be obtained and defined as Gctlr(bk) (s) = 0.23.
Substitution of Gctlr(bt) (s) = 0.1 and Gctlr(bk) (s) = 0.23 into Equations ( 16) and ( 17), and using Matlab, frequency responses of buck and boost modes, are illustrated in Figure 12.From Figure 12, a resonant frequency point of Gop(bt) (s) was at 450 Hz; hence, the compensative crossover frequency, fcf, must be deviated from this resonant frequency point because the resonant occurrence would cause the HPLDDC instability.Moreover, Gop(bk) (s) bandwidth (BW) was 7.7 Hz, and it should be expanded for the HPLDDC response speed promotion.In addition, in the switching-mode DC-DC converters, fcf can be lower than the fs/10 [24].According to these circumstances, fcf was 50 Hz for the HPLDDC operation.
Therefore, substitution of gi = 1.11 × 10 3 and gp = 2.2 into Equation ( 18) can rewire Gcea(PI) (s), whose TF can be expressed as follows: In this study, the CLC TF using the PI control can adopt Equation (21).The CLC TF using the P control can employ the gp gain from Equation ( 18) that is given by: In Figures 9 and 10, kc is equal to gsa × kcv, gsa is the SA's amplifier gain, kcv is the C-V converter gain.In this study, gsa and kcv were set as 16 and 0.05, respectively; hence kc equaled to 0.8.
Moreover, an open-loop gain Gop(btcea) (s) equaled to kc × Gop(bt) (s) × Gcea(PI) (s).Therefore, use of the MATLAB could simulate the frequency response of Gop(btcea) (s), as shown in Figure 12b.From Figure 12b, the LFG was promoted to 38.3 dB, and the phase was −33.6° at 50 Hz.Furthermore, an open-loop gain, Gop(bkcea) (s), equaled to kc × Gop(bk) (s) × Gcea(PI) (s).Hence, Gop(btcea) (s) simulation using the MATLAB is illustrated in Figure 12b.From Figure 12b, LFG was promoted to 44.7 dB, and the phase was −107° at 50 Hz.According to the frequency responses of Gop(btcea) (s) and Gop(bkcea) (s), the HPLDDC using the designing CLC PI control can address the system stable requirement for buck and boost operations.Substitution of G ctlr(bt) (s) = 0.1 and G ctlr(bk) (s) = 0.23 into Equations ( 16) and ( 17), and using Matlab, frequency responses of buck and boost modes, are illustrated in Figure 12.From Figure 12, a resonant frequency point of G op(bt) (s) was at 450 Hz; hence, the compensative crossover frequency, f cf , must be deviated from this resonant frequency point because the resonant occurrence would cause the HPLDDC instability.Moreover, G op(bk) (s) bandwidth (BW) was 7.7 Hz, and it should be expanded for the HPLDDC response speed promotion.In addition, in the switching-mode DC-DC converters, f cf can be lower than the f s /10 [24].According to these circumstances, f cf was 50 Hz for the HPLDDC operation.Incorporating Gop(btcea) (s) with Gss (s) of ( 15) and using Matlab, the simulation of HPLDDC start-up current for the boost mode is illustrated in Figure 13a.In addition, incorporating Gop(bkcea) (s) with Gss (s) and using MATLAB, the simulation of the HPLDDC start-up current for the buck mode is illustrated in Figure 13b.Several situations can be observed in Figure 13: 1. Boost mode: No current spike occurred.The settling time was 40 ms.The final current was 1.2 A; and 2. Buck mode: Maximum start-up current peak was 1.65 A. The settling time was 230 ms.The final current was 1.2 A.
From both figures, although the final current, 1.2 A, could correspond to the specification, a start-up current spike occurred in the buck mode operation.From these simulations, several disadvantages can be identified when the CLC uses the PI control.First, the peak current of 1.65 A already overstepped the specified 1.5 A, and this situation was harmful for HPLDs.Second, although the CLC using PI control had an outstanding ability to regulate steady-state errors, the PI control caused the start-up current spike when the SBBC operated in the buck mode.According to Figure 12, at 50 Hz, G op(bk) should be promoted from −5.52 to 0 dB.Therefore, the magnitude of Equation ( 18) can equal to a constant, 1.89 (20 log 1.89 = 5.52 dB).Moreover, g p can be select as a suitable constant value.Hence, substitution of g p = 2.2, |G cea(PI) [j(2πf cf )]| = 1.89 and f cf = 50 Hz into Equation ( 18) can obtain g i = 1.11 × 10 3 .Therefore, substitution of g i = 1.11 × 10 3 and g p = 2.2 into Equation ( 18) can rewire G cea(PI) (s), whose TF can be expressed as follows: In this study, the CLC TF using the PI control can adopt Equation (21).The CLC TF using the P control can employ the g p gain from Equation ( 18) that is given by: In Figures 9 and 10, k c is equal to g sa × k cv , g sa is the SA's amplifier gain, k cv is the C-V converter gain.In this study, g sa and k cv were set as 16 and 0.05, respectively; hence k c equaled to 0.8.Moreover, an open-loop gain G op(btcea) (s) equaled to k c × G op(bt) (s) × G cea(PI) (s).Therefore, use of the MATLAB could simulate the frequency response of G op(btcea) (s), as shown in Figure 12b.From Figure 12b, the LFG was promoted to 38.3 dB, and the phase was −33.6 • at 50 Hz.Furthermore, an open-loop gain, G op(bkcea) (s), equaled to k c × G op(bk) (s) × G cea(PI) (s).Hence, G op(btcea) (s) simulation using the MATLAB is illustrated in Figure 12b.From Figure 12b, LFG was promoted to 44.7 dB, and the phase was −107 • at 50 Hz.According to the frequency responses of G op(btcea) (s) and G op(bkcea) (s), the HPLDDC using the designing CLC PI control can address the system stable requirement for buck and boost operations.
Incorporating G op(btcea) (s) with G ss (s) of ( 15) and using Matlab, the simulation of HPLDDC start-up current for the boost mode is illustrated in Figure 13a.In addition, incorporating G op(bkcea) (s) with G ss (s) and using MATLAB, the simulation of the HPLDDC start-up current for the buck mode is illustrated in Figure 13b.Several situations can be observed in Figure 13: Incorporating Gop(btcea) (s) with Gss (s) of ( 15) and using Matlab, the simulation of HPLDDC start-up current for the boost mode is illustrated in Figure 13a.In addition, incorporating Gop(bkcea) (s) with Gss (s) and using MATLAB, the simulation of the HPLDDC start-up current for the buck mode is illustrated in Figure 13b.Several situations can be observed in Figure 13: 1. Boost mode: No current spike occurred.The settling time was 40 ms.The final current was 1.2 A; and 2. Buck mode: Maximum start-up current peak was 1.65 A. The settling time was 230 ms.The final current was 1.2 A.
From both figures, although the final current, 1.2 A, could correspond to the specification, a start-up current spike occurred in the buck mode operation.From these simulations, several disadvantages can be identified when the CLC uses the PI control.First, the peak current of 1.65 A already overstepped the specified 1.5 A, and this situation was harmful for HPLDs.Second, although the CLC using PI control had an outstanding ability to regulate steady-state errors, the PI control caused the start-up current spike when the SBBC operated in the buck mode.To depress the start-up current spike, the CLC using the PIAP control method was employed.Simulations are presented in Figure 14.From Figure 14, despite the SBBC operating mode, the use of P control method cannot achieve the target final current of 1.2 A.
Thus, a CLC using the PIAP control method could be adopted in the HPLDDC.Figure 14 simulations show several benefits: First, the start-up current spike mitigated effectualness.Second , no steady-state errors were achieved, and the final current could address the specified 1.2 A because the HPLDDC using CLC can become the PI control in the SBBC CCOM.Third, the settling time was reduced from 230 to 80 ms in the SBBC buck mode.From both figures, although the final current, 1.2 A, could correspond to the specification, a start-up current spike occurred in the buck mode operation.From these simulations, several disadvantages can be identified when the CLC uses the PI control.First, the peak current of 1.65 A already overstepped the specified 1.5 A, and this situation was harmful for HPLDs.Second, although the CLC using PI control had an outstanding ability to regulate steady-state errors, the PI control caused the start-up current spike when the SBBC operated in the buck mode.
To depress the start-up current spike, the CLC using the PIAP control method was employed.Simulations are presented in Figure 14.From Figure 14, despite the SBBC operating mode, the use of P control method cannot achieve the target final current of 1.2 A.
Thus, a CLC using the PIAP control method could be adopted in the HPLDDC.Figure 14 simulations show several benefits: First, the start-up current spike mitigated effectualness.Second, no steady-state errors were achieved, and the final current could address the specified 1.2 A because the HPLDDC using CLC can become the PI control in the SBBC CCOM.Third, the settling time was reduced from 230 to 80 ms in the SBBC buck mode.

Experimental Results
In accordance with the system configuration in Figure 2, the HPLDDC can drive the three blue-beam HPLDs.Figures 15 and 16   At a V in of 9 V, the HPLDDC operated in the boost mode because (V in = 9 V) < (V o = 15 V), and a slight current spike was observed, with a peak value of 1.4 A, and the settling time was 60 ms (simulation was 40 ms), as shown in Figure 15a.

2.
At a V in of 15 V, the HPPLD operated in the buck-boost mode because (V in = 15 V) = (V o = 15 V), and the current spike was observed, with a peak was 1.6 A, which overstepped the HPLD maximum operating current of 1.5 A (Table 3).The settling time was 260 ms, as shown in Figure 15b.

3.
At a V in of 16 V, the HPPLD operated in the buck mode because (V in = 16 V) > (V o = 15 V), and the current spike was observed, with a peak was 1.65 A. This peak value was also over the HPLD maximum operating current of 1.5 A. Then, the settling time was 260 ms (simulation was 230 ms), as shown in Figure 15c.
Thus, the start-up current spike must be mitigated, and it should be lower than the HPLD maximum operating current of 1.5 A.

1.
At a V in of 9 V, the HPPLD operated the in the boost mode, and a slight current spike with a peak value of 1.25 A was observed.The settling time was 65 ms (simulation was 40 ms), as shown in Figure 16a.2.
At a V in of 15 V, the HPPLD operated in the buck-boost mode, a slight current spike was observed, with a peak of 1.3 A, which was lower than the HPLD maximum operating current of 1.5 A. The settling time was 100 ms, as shown in Figure 16b.

3.
At a V in of 16 V, the HPPLD operated in the buck mode, and a slight current spike with a peak of 1.3 A was observed.This peak value was also lower than 1.5 A. The settling time was 80 ms (simulation was 80 ms), as shown in Figure 16c.
Therefore, the start-up current spike could be mitigated, and the current settling time could be obviously reduced, when the CLC used the PIAP control technology.

CLC Using PI Control Method
1.At a Vin of 9 V, the HPLDDC operated in the boost mode because (Vin = 9 V) < (Vo = 15 V), and a slight current spike was observed, with a peak value of 1.4 A, and the settling time was 60 ms (simulation was 40 ms), as shown in Figure 15a.
2. At a Vin of 15 V, the HPPLD operated in the buck-boost mode because (Vin = 15 V) = (Vo = 15 V), and the current spike was observed, with a peak was 1.6 A, which overstepped the HPLD maximum operating current of 1.5 A (Table 3).The settling time was 260 ms, as shown in Figure 15b.
3. At a Vin of 16 V, the HPPLD operated in the buck mode because (Vin = 16 V) > (Vo = 15 V), and the current spike was observed, with a peak was 1.65 A. This peak value was also over the HPLD maximum operating current of 1.5 A. Then, the settling time was 260 ms (simulation was 230 ms), as shown in Figure 15c.
Thus, the start-up current spike must be mitigated, and it should be lower than the HPLD maximum operating current of 1.5 A.

CLC Using PIAP Control Method
1.At a Vin of 9 V, the HPPLD operated the in the boost mode, and a slight current spike with a peak value of 1.25 A was observed.The settling time was 65 ms (simulation was 40 ms), as shown in Figure 16a.
2. At a Vin of 15 V, the HPPLD operated in the buck-boost mode, a slight current spike was observed, with a peak of 1.3 A, which was lower than the HPLD maximum operating current of 1.5 A. The settling time was 100 ms, as shown in Figure 16b.
3. At a Vin of 16 V, the HPPLD operated in the buck mode, and a slight current spike with a peak of 1.3 A was observed.This peak value was also lower than 1.5 A. The settling time was 80 ms (simulation was 80 ms), as shown in Figure 16c.
Therefore, the start-up current spike could be mitigated, and the current settling time could be obviously reduced, when the CLC used the PIAP control technology.

Figure 1 .
Figure 1.Laser diode configuration and heterojunction: (a) Semiconductor configuration; (b) recombination of electron-hole pair at the heterojunction.

Figure 1 .
Figure 1.Laser diode configuration and heterojunction: (a) Semiconductor configuration; (b) recombination of electron-hole pair at the heterojunction.

Figure 4 .
Figure 4. Buck mode principle: (a) v gs1 -v gs4 and i L timing charts; (b) operating circuit in t k1 -t k2 ; and (c) operating circuit in t k3 -t k4 .
, and f s = 400 kHz into (9) can obtain C obt = 4.1 µF.Substitution of the aforementioned parameters and β = 20% into (10) can obtain ESR bt ≤ 62 mΩ.These calculating values, including L bk , C obk, ESR bk , L bt , C obt , and ESR bt , are listed in Table
present the experimental waveforms, including the HPLDDC output current (HPLDs driving current), Io, the HPLDDC input voltage, Vin, and the HPLDDC output voltage (HPLDs driving voltage), Vo.

Vin High-Power Laser Diode Driving Controller
Without any driving devices to regulate the LD driving current, if the LD driving voltage is higher than VLDF, more current is indispensable to drive the LD strengthening the laser beams, and the driving current can be increased exponentially.Because the constant OOP originates from a stable LD driving current, the LD can be driven by a CC output power supply, or regulated by a CC sink.Several control methods for the LD driving are discussed in the following section.
Without any driving devices to regulate the LD driving current, if the LD driving voltage is higher than VLDF, more current is indispensable to drive the LD strengthening the laser beams, and the driving current can be increased exponentially.Because the constant OOP originates from a stable LD driving current, the LD can be driven by a CC output power supply, or regulated by a CC sink.Several control methods for the LD driving are discussed in the following section.Laser diode (LD) voltage-current characteristic.

Table 4 .
High-power laser diode driving controller (HPLDDC) parameters and specifications.

Table 5 .
Calculating inductance and output capacitance values.
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