Sizing the Split DC Link Capacitance in Three-Phase Three-Level Bidirectional AC-DC Converters Operating with Arbitrary Power Factor Under Zero-Sequence Injection Restriction

Abstract

The paper presents a methodology for determining the minimum split DC link capacitance for a family of three-phase, three-level grid-connected bidirectional AC-DC converters operating under arbitrary power factor under restriction of DC-only zero-sequence injection. The approach is based on the recently revealed generalized behavior of split DC link voltages in the above-mentioned converters family while distinguishing between leading and lagging power factors in order to highlight different impacts on split DC link capacitor voltages pulsating components. The minimum capacitance value is derived from the boundary condition, ensuring the mains voltage remains below or equal to the capacitor voltage at all times. It is revealed that operation with the lowest expected leading power factor should be employed as the design operating point. The accuracy of the proposed methodology is validated by simulations and experiments carried out employing a 10 kVA grid-connected T-type converter prototype. The results demonstrate close agreement between theoretical predictions and experiments, confirming the practical applicability of the proposed method.

1. Introduction

The ever-growing demand for high-power on/off-grid bidirectional AC-DC converters underscores their pivotal role in modern power and energy systems. As a result, multi-level converters have emerged as a preferred choice across various applications, owing to their superior performance characteristics [1]. These converters offer notable advantages such as enhanced efficiency, reduced dv/dt stress, and lower output voltage total harmonic distortion, making them indispensable in meeting stringent grid standards [2]. In addition, these converters are often required to operate with non-unity power factors, either to supply (absorb) reactive power to (from) the grid or accommodate loads operating with varying power factor [3]. Multi-level converters are known to be crucial in dual-stage power conversion systems that utilize an intermediate DC voltage link [4,5,6,7,8,9]. In such multi-level conversion systems, the DC link is usually implemented using multiple split capacitors [10,11]. The topology allows power decoupling between conversion stages and permits self-governing converter operation while employing diverse pulse width modulation (PWM) techniques [12,13,14,15,16,17,18]. In fact, 10–100 kVA rated multilevel AC-DC and DC-AC converters have become increasingly prominent across diverse industrial applications [19].

Dual-stage AC-DC and DC-AC converters usually include a short-term energy storage unit (typically realized by a capacitor bank) on the DC side to manage pulsating power components [20], maintain stable operation during power mismatches occurring during transients [21], and comply with hold-up requirements [22]. On the other hand, the capacitance of the DC link is a bottleneck in terms of physical size and reliability [23,24,25]. The DC link capacitance value is typically imposed by the hold-up time constraint. In applications where temporary loss-of-mains is tolerable, hold-up time constraint is absent, and it is possible to reduce the value of required DC link capacitance. Numerous approaches for DC link capacitance reduction have been suggested in the literature, e.g., active capacitance reduction [26,27,28], AC-side current distortion (up to minimum allowed power quality merit) [29,30], permitting DC link voltage ripple increase [31,32], etc. Minimum attainable values of DC link capacitance under active power decoupling, AC-side current distortion, notch-based DC link voltage control, and increased DC link voltage ripple were derived in [32,33,34], respectively.

A methodology for establishing a baseline for determining split DC link voltages behavior for a family of three-level, three-phase AC-DC and DC-AC power converters was revealed in [35]. The approach is based on the assumption of the third-harmonic-dominated nature of split DC link voltages ripple. The revealed approach focused on converters operating with a unity power factor and a constrained-to-DC zero-sequence component. A subsequent study [36] utilized the outcomes of [35] to derive the lowest feasible values of split DC link capacitance for the above-mentioned family of converters. The impact of operation with arbitrary power factor on the behavior of split DC link voltages was recently explored in [37]. It was shown that operation under non-unity power factor gives rise to significant high-order harmonic content, which aggregates split DC link voltage ripple magnitudes and displaces them relative to mains voltages. Consequently, the assumption of third-harmonic-only content (shown to be accurate in case of unity power factor operation in [35]) does not hold anymore. As a result, the derivation of corresponding analytical expressions is nearly unmanageable. In order to tackle this gap, a numerical solution was adopted in [37] for the derivation of a general expression for normalized split DC link ripple energy and the angle between split DC link voltages and AC-side voltages as a function of the power factor.

This work proposes a methodology for determining the minimum split DC link capacitance for the above-mentioned family of converters by utilizing the assessment of split DC link voltage behavior carried out in [37]. It is revealed that the operating point corresponding to the minimum expected leading power factor should be employed for capacitance sizing. Experimental results fully support the proposed design methodology.

2. Split DC Link Voltages in Zero-Sequence-Restricted Three-Phase Three-Level AC-DC Converter

A common dual-stage three-phase power conversion system, consisting of a three-level AC-DC (or DC/AC) converter, a DC link, and a DC-DC converter, is depicted in Figure 1. System power flow is bidirectional in general, i.e., energy may be transferred from the AC to the DC side or in the reverse direction [36]. Consequently, the ’Load’ in Figure 1 may be regenerative or serve as a source in case the power is displaced from DC to AC side. The DC link contains three terminals (X, O, Y) at the side of the AC-DC converter and can be either two-level or three-level at the DC/DC converter side, as shown. Under balanced sinusoidal conditions (which are considered in this paper), steady-state AC-side electrical parameters may be expressed as

$${\overrightarrow{v}}_{RST}(t)=\left(\begin{array}{c}{v}_{RN}(t)\\ v_{SN}(t)\\ v_{TN}(t)\end{array}\right)=V_M\left(\begin{array}{c}\sin \left(\omega t\right)\\ \sin \left(\omega t-\theta \right)\\ \sin \left(\omega t+\theta \right)\end{array}\right)$$

(1a)

and

$${\overrightarrow{i}}_{RST}(t,\phi )=\left(\begin{array}{c}{i}_R(t,\phi )\\ i_S(t,\phi )\\ i_T(t,\phi )\end{array}\right)=I_M\left(\begin{array}{c}\sin \left(\omega t-\phi \right)\\ \sin \left(\omega t-\theta -\phi \right)\\ \sin \left(\omega t+\theta -\phi \right)\end{array}\right)$$

(1b)

with V_M [V], I_M [A], respectively, symbolizing phase voltage and current magnitudes, ω [rad/s] standing for base angular frequency, $\phi$ [rad] denoting the load angle (i.e., the phase difference between voltage and current vectors), and $\theta =2\pi /3$ [rad]. Considering (1), instantaneous AC-side phase power vector is given by

$${\overrightarrow{p}}_{RST}(t,\phi )=\left(\begin{array}{c}{p}_R(t,\phi )\\ p_S(t,\phi )\\ p_T(t,\phi )\end{array}\right)=\left(\begin{array}{c}{v}_{RN}(t)i_R(t,\phi )\\ v_{SN}(t)i_S(t,\phi )\\ v_{TN}(t)i_T(t,\phi )\end{array}\right)=0.5V_M{I}_M\left(\begin{array}{c}\cos \phi -\cos 2\left(\omega t-{\displaystyle \frac{\phi }{2}}\right)\\ \cos \phi -\cos 2\left(\omega t-{\displaystyle \frac{\phi }{2}}-\theta \right)\\ \cos \phi -\cos 2\left(\omega t-{\displaystyle \frac{\phi }{2}}+\theta \right)\end{array}\right).$$

(2)

As a result, total instantaneous AC-side power is given by

$$p_{RST}(t,\phi )=p_R(t,\phi )+p_S(t,\phi )+p_T(t,\phi )=S\cos \phi \triangleq P_{RST}$$

(3)

with S = 3/2 V_MI_M denoting the total apparent power and is low-frequency ripple free. Considering lossless conversion (for brevity only, without loss of generality), total instantaneous AC-side power P_RST is equal to the absolute value of the load power P_L = V_WZI_L (cf. Figure 1) in steady state due to energy balance. As a result, there is no instantaneous power flow (besides switching frequency-related components) into the DC link in Figure 1.

General three-phase three-level AC-DC conversion topology is depicted in Figure 2 [35]. Here, the DC link consists of two split capacitors (namely, C_DC1 and C_DC2) with corresponding instantaneous voltages vector given by

$${\overrightarrow{v}}_{DC}(t,\phi )=\left(\begin{array}{c}{v}_{DC1}(t,\phi )\\ v_{DC2}(t,\phi )\end{array}\right).$$

(4)

According the previous paragraph outcomes, total instantaneous DC link voltage v_DC is low-frequency-ripple-free since there it does not cope with instantaneous power flow. Yet, this outcome does not imply that each of the split DC link voltages v_DC1, v_DC2 is low-frequency-ripple-free (only their sum is) [36]. According to the voltages Equation (1a), the controller (cf. Figure 1) generates shifted sinusoidal pulse-width modulation (PWM) signals which may be approximated by

$${\overrightarrow{m}}_{RST}(t)=\left(\begin{array}{c}{m}_R(t)\\ m_S(t)\\ m_T(t)\end{array}\right)\approx M(t)\left(\begin{array}{c}\sin \left(\omega t\right)\\ \sin \left(\omega t-\theta \right)\\ \sin \left(\omega t+\theta \right)\end{array}\right)+m_0(t),$$

(5)

where M(t) represents the magnitude of sinusoidal modulating signals and m₀(t) denotes the zero-sequence component [37]. As a result, converter-imposed AC-side voltages (cf. Figure 1) contain zero-sequence constituent v₀(t) imposed by m₀(t),

$${\overrightarrow{v}}_{ABC}(t)=\left(\begin{array}{c}{v}_{AN}(t)\\ v_{BN}(t)\\ v_{CN}(t)\end{array}\right)\approx V_M\left(\begin{array}{c}\sin \left(\omega t\right)\\ \sin \left(\omega t-\theta \right)\\ \sin \left(\omega t+\theta \right)\end{array}\right)+v_0(t).$$

(6)

In general, m₀(t) may include both DC and high-order AC components in order to both equalize average values of the voltages across split DC link capacitors V_DC1, V_DC2 and reduce corresponding voltage ripples Δv_DC1(t), Δv_DC2(t) [29,30]. In some cases, m₀(t) is permitted to include DC component only in steady-state, allowing to equalize split DC link voltages average values without influencing corresponding voltage ripples [35,36,37] (which is the case considered in this paper). It should be emphasized that under certain circumstances, m₀(t) must be kept zero at all time, calling for an external hardware-based equalization circuits [33].

Denoting reference values of average split capacitor voltages as $V_{DC1}^{*}$ and $V_{DC2}^{*}$, respectively, and assuming that

$$\begin{array}{cc}{V}_{DC1}^{*}=V_{DC2}^{*}=0.5V_{DC}^{*},& C_{DC1}=C_{DC2}=C_{DC}\end{array}$$

(7)

with $V_{DC}^{*}$ denoting overall DC link voltage reference value, it was shown in [37] that under the conditions (1), steady-state instantaneous split DC link voltages are given by

$$v_{DC1,2}(t,\phi )\approx V_{DC1,2}^{*}\mp \Delta v_{DC1,2}(t)=0.5V_{DC}^{*}\mp \Delta V(\phi )\cos \left(3\omega t+\alpha (\phi )\right)$$

(8)

with load angle φ-dependent phase shift α and ripple magnitude ΔV. In addition, the following dependencies were obtained in [37] for the case of ω = 100π rad/s base angular frequency,

$$\begin{array}{l}\Delta V(\phi )\approx {\displaystyle \frac{2S}{V_{DC}^{*}{C}_{DC}}}{E}_{AC}^{pu}[V],\\ E_{AC}^{pu}=\left(-84.46{\left|\cos \phi \right|}^4+116.3{\left|\cos \phi \right|}^3-124.1{\left|\cos \phi \right|}^2+9.197\left|\cos \phi \right|+265.1\right)\cdot {10}^{-6}\left[{\displaystyle \frac{J}{VA}}\right],\end{array}$$

(9)

$$\left|\alpha (\phi )\right|\approx \left(-308.1{\left|\cos \phi \right|}^4+410.7{\left|\cos \phi \right|}^3-196.7{\left|\cos \phi \right|}^2+9.883\left|\cos \phi \right|+86.87\right)\cdot {\displaystyle \frac{2\pi }{{360}^{\circ }}}\left[rad\right].$$

(10)

Unfortunately, distinction between leading and lagging power factors was not addressed in [37]. Re-examining the results, phase shift in (10) should be adopted, in general case, as

$$\alpha (\phi )\approx \left\{\begin{array}{cc}\left|\alpha (\phi )\right|,& \phi <0\\ -\left|\alpha (\phi )\right|& \phi >0\end{array}\right..$$

(11)

Hence, operation with lagging power factor (i.e., φ > 0) tends to align the positive peak of the positive split DC link voltage with positive peak of AC-side phase voltage, while operation with leading power factor (i.e., φ < 0) tends to synchronize the negative peak of the positive split DC link voltage with positive grid voltage peak, as shown in Figure 3 for different values of the power factor (PF = cos$\phi$). As a result, DC link capacitance should be sized according to the worst case of AC-side power factor expected value according Figure 3.

3. DC Link Capacitance Sizing

In order to assure correct functionality of the converter in Figure 2,

$$\left|{\overrightarrow{v}}_{RST}(t)\right|\le v_{DC1,2}(t)$$

(12)

must hold instantaneously due to boost AC-to-DC (or buck DC-to-AC) topology of the latter. Combining the expressions of R-phase voltage (cf. (1)) and split DC-link voltage (cf. (7)), boundary condition satisfying (12) is given by

$$0.5V_{DC}^{*}-\Delta V(\phi )\cos \left(3\omega t+\alpha (\phi )\right)=V_M\sin (\omega t).$$

(13)

Equation (13) poses a challenge for obtaining an analytical solution in its original form yet may be solved numerically using any available computational software package. Nevertheless, it is possible to approximate the solution analytically by decomposing both sides of (13) into corresponding second-order Taylor series expansions, resulting in the following quadratic equation,

$$\begin{array}{l}\left({\displaystyle \frac{9}{2}}\Delta V(\phi )+{\displaystyle \frac{V_M}{2}}\right){(\omega t)}^2-\left(3\Delta V(\phi )\cdot \left(2\pi +\alpha (\phi )\right)+{\displaystyle \frac{\pi V_M}{2}}\right)(\omega t)+\\ +{\displaystyle \frac{V_{DC}^{*}}{2}}+\Delta V(\phi )\left({\displaystyle \frac{{(2\pi +\alpha (\phi ))}^2}{2}}-1\right)-V_M\left(1-{\displaystyle \frac{{\pi }^2}{8}}\right)=0.\end{array}$$

(14)

Figure 3 illustrates the accuracy of approximation (14). Since Taylor series expansions are carried out around corresponding peak points, the minimum error occurs when the power factor is zero and leading, while the maximum error arises when the power factor is zero and lagging. For a given range of expected power factors, the capacitance value of split DC link capacitors should be determined according to the lowest leading power factor (or the highest lagging power factor in case inductive-only operation is expected). Such a sizing approach guarantees correct performance within the whole operational power factor range while the proposed approximation provides a reliable method for calculating the minimum required capacitance value.

Boundary condition (13) is attained when the quadratic Equation (14) determinant equals zero, yielding a single solution (see [36] for additional details). Solving, minimum split DC link capacitance value is obtained as (cf. (9) and (10))

$$C_{DC}={\displaystyle \frac{288\cdot S\cdot E_{AC}^{pu}}{V_{DC}^{*}\left(36V_{DC}^{*}+V_M(4{\alpha }^2+4\alpha \pi +{\pi }^2-80)+\sqrt{\Delta }\right)}}$$

(15)

with $∆$ given by

$$\begin{array}{ll}\Delta =& 1296{\left(V_{DC}^{*}\right)}^2+V_{DC}^{*}{V}_M\left(288{\alpha }^2+288\alpha \pi +72{\pi }^2-4608\right)+\\ & +V_M^2\left(16{\alpha }^4+32{\alpha }^3\pi +24{\alpha }^2{\pi }^2+8\alpha {\pi }^3+{\pi }^4-640{\alpha }^2-640\alpha \pi -160{\pi }^2+4096\right).\end{array}$$

(16)

On the other hand, additional requirement should be established in practice in order to bound the maximum value of a split DC link capacitor voltage according to its voltage rating as follows. Denoting the voltage rating of a split DC link capacitor as V_R, the maximum value of a split DC link capacitor voltage should be limited to kV_R with k < 1 in order to provide a safety margin for prolonging the device lifetime. Consequently, the following equation is formed (cf. (8))

$$0.5V_{DC}^{*}+\Delta V(\phi )=k{V}_R,$$

(17)

satisfied by a capacitor valued as (cf. (9))

$$C_{DC}={\displaystyle \frac{S\cdot E_{AC}^{pu}(\phi )}{0.5V_{DC}^{*}(k{V}_R-0.5V_{DC}^{*})}}.$$

(18)

Combining (15) and (18) into

$${\displaystyle \frac{288}{36V_{DC}^{*}+V_M(4{\alpha }^2+4\alpha \pi +{\pi }^2-80)+\sqrt{\Delta }}}={\displaystyle \frac{2}{k{V}_R-0.5V_{DC}^{*}}}.$$

(19)

and solving provides the required reference voltage value $V_{DC}^{*}$. Then, minimum split DC link capacitance value C_DC may be obtained by substituting $V_{DC}^{*}$ into (15) or (18).

4. Validation

In order to support the developed analytical split DC capacitor sizing framework experimentally, grid-connected LC-filter-based, three-phase three-level T-type AC-DC converter prototype depicted in Figure 4a was employed. Corresponding system parameters are summarized in

Table 1. System parameter values.

Parameter	Value	Units
$V_M$	$240\sqrt{2}$	V
$\omega$	$2\pi ·50$	$\mathrm{r}\mathrm{a}\mathrm{d}/\mathrm{s}$
$L_f$	350	$\mathsf{\mu }\mathrm{H}$
$C_f$	10	$\mathsf{\mu }\mathrm{F}$
ESR($L_{f1}$)	50	$\mathrm{m}\mathsf{\Omega }$
ESR($C_f$)	316	$\mathrm{m}\mathsf{\Omega }$
SR	11	kVA
$V_R$	400	V
k	0.94	-
min(PF)	0.5 Leading/Lagging	-

. The converter was run at switching/sampling frequency of 50 kHz by means of the Texas Instruments control card based on the TMS320F28335 Digital Signal Processor. During the experimental framework, the T-type AC-DC converter was fed by a DC source (generating a constant-valued DC voltage v_DC) while supplying a live three-phase AC grid with a set of balanced three-phase currents (cf. (1)) with controlled magnitudes and phase shifts.

The corresponding block diagram of the control system is shown in Figure 4b. In order to create in-phase unity-magnitude signal templates, grid voltages are sampled, Clarke-transformed into αβ domain and finally divided by grid voltage vector magnitude V_M (obtained using amplitude detection block AD). The resulting unity-magnitude templates are multiplied by the desired grid current magnitude $I_M^{*}$ and then delayed in order to impose the desired phase shift φ to create αβ domain current references $i_{\alpha }^{*},i_{\beta }^{*}$. On the other hand, grid currents were sampled, Clarke-transformed into αβ domain and subtracted from αβ domain current references $i_{\alpha }^{*},i_{\beta }^{*}$. Corresponding tracking errors were then processed by PI controllers. The outputs of αβ domain PI controllers were added to normalized αβ domain voltages (created by dividing αβ domain voltages v_α, v_β by 0.5 v_DC). The results were inverse-Clarke-transformed to create the first modulation signals term (at the right-hand side of (5)). Zero-sequence term m₀ (i.e., the second term at the right-hand side of (5)) was generated by processing the difference between sampled split DC link voltages v_DC1, v_DC2 by a P + Notch controller employing a constant proportional gain K followed by a 150 Hz centered notch filter NF₁₅₀ possessing unity DC gain aimed to suppress the triple-mains-frequency ripple (cf. (8)) in order to satisfy the DC-only zero sequence component constraint [35]. The experimental prototype is depicted in Figure 4c. Upon system start-up, the converter is synchronized with the AC grid and then grid-connected with zero-current reference. Then, the desired values of $I_M^{*}$ and phase shift φ are imposed by the control system in order to bring the converter to the desired operating point. Measurements are performed when the system settles, and steady-state is attained.

Considering the range of power factors (both leading and lagging) given by

$$\left|PF\right|\ge 0.5,$$

(20)

split DC link capacitances must be sized considering the lowest expected leading power factor (namely PF = −0.5 or φ = 60°, as discussed in the previous chapter and shown in Figure 3). Simultaneous solution of (15) and (18) with (9) and (10) (employing the values given in Table 1) yields the following values of split DC link voltage reference (19) and split capacitances, respectively. Corresponding graphical solution is depicted in Figure 5 for demonstration purposes. The ’minimum voltage-imposed value’ curve corresponds to Equation (15), while the ’maximum voltage-imposed value’ curve corresponds to (18). The values obtained in (20) are employed in both simulation and experimental frameworks as follows.

$$\begin{array}{cc}{C}_{DC1,2}=440 [\mu F],& V_{DC1,2}^{*}=355[V]\end{array}$$

(21)

Three simulations (PSIM 2025 software was used) and matching experiments were carried out under rated loading S_R (cf. Table 1) under three following power factor values: PF = 0.5 (leading), PF = 1 (unity), PF = 0.5 (lagging) with the former representing the design point (cf. (21)). The results are depicted in Figure 6, Figure 7, Figure 8, Figure 9, Figure 10 and Figure 11. Experimental waveforms were acquired using a 4-channel oscilloscope, hence only two out of three AC-side quantities (i.e., two voltages and two currents) are shown simultaneously while all the three are given in corresponding simulation results. It should also be emphasized that due to the fact that the three-phase mains in the Applied Energy Laboratory (experimental site) is typically polluted with non-negligible harmonic content (well-evident in the experimental waveforms), the currents generated by the inverter also possess noticeable harmonic constituents due to simplified control system adopted (cf. Figure 4b) which does not consider harmonic elimination for brevity. Nevertheless, such characteristics do not affect the proposed methodology feasibility. It is well-evident that all simulation results accurately match their experimental counterparts even though the former consider purely sinusoidal AC-side voltage and currents.

Figure 6 and Figure 7 demonstrate operational waveforms of the system under rated loading with leading power factor of PF = 0.5 (i.e., AC-side currents lead corresponding AC-side voltages by 60°). It is well-evident that under these conditions, a single tangency point between positive part of grid voltages and positive split DC link voltage v_DC1 exists, as indicated by black circles in Figure 7, as expected. On the other hand, split DC link voltages are kept below 376 V (=0.94∙400) at all time. Such a behavior accurately validates the design point (cf. (21)), simultaneously satisfying (15) and (18). Note that even though experimental waveforms of AC-side voltages are slightly distorted (due to harmonic content pollution), split DC link voltages are sinusoidal at triple-grid-frequency. This supports the above-made claim regarding negligible influence of AC-side current harmonic content on split DC-link voltages behavior particular and the proposed methodology feasibility in general. Similar conclusion may be drawn regarding operation under other power factor values as well. It is also evident that positive AC-side voltage peaks and valleys of split DC link voltage v_DC1 are slightly shifted due to nonzero PF and are expected to approach each other in case the value of leading power factor is further decreased (cf. Figure 3). Figure 8 and Figure 9 demonstrate operational waveforms of the system under rated loading with unity power factor (here, AC-side currents are in-phase with corresponding AC-side voltages). It is well-evident that under these conditions no tangency point between positive grid voltage parts and the corresponding split DC link voltage v_DC1 exists, as expected. On the other hand, split DC link voltages are kept below 376 V (=0.94∙400) at all times, as required. It is also evident that positive AC-side voltage peaks are synchronized with instances where v_DC1 = −v_DC2 = 0.5 v_DC. Such a behavior is well in line with performance previously revealed by the Authors in [36]. Figure 10 and Figure 11 demonstrate operational waveforms of the system under rated loading with lagging power factor of PF = 0.5 (i.e., AC-side currents lag corresponding voltages by 60°). It is well-evident that under these conditions no tangency point between positive grid voltages parts and corresponding split DC link voltage v_DC1 exists, as predicted. Split DC link voltages are kept below 376 V (=0.94∙400) at all times, as required. It is also evident that positive AC-side voltage peaks are nearly aligned with those of split DC link voltage v_DC1 due to nonzero PF and are expected to approach each other in case the value of lagging power factor is further decreased (cf. Figure 3). Note that tangency between positive grid voltages and the absolute value of the split DC link voltage v_DC2 is irrelevant. Consequently, operation under near-zero lagging power factor may be considered as “best case” while operation under near-zero leading power factor may be considered as “best case”.

5. Conclusions

A method for estimating the minimum split DC-link capacitance value required in a family of three-level, three-phase bidirectional AC-DC power converters operating with arbitrary power factor under constrained zero-sequence component was proposed and experimentally validated in the paper. The analysis is based on the previously revealed impact of arbitrary power factor operation on the behavior of split DC link voltages. A detailed examination of the distinction between operation with leading and lagging power factor and the corresponding influence on the capacitance sizing process was carried out. The proposed design approach was validated through closely matching simulations and experiments, confirming the accuracy of the developed analytical framework. Future work on the subject includes analysis of system operation under unbalanced AC-side voltages and/or nonlinear AC-side currents under both restricted and non-constrained zero-sequence injection.