COTS Battery Charge Equalizer for Small Satellite Applications

Abstract

This paper describes the design and implementation of a battery equalizer circuit for small satellites, developed under the New Space philosophy exclusively using commercial off-the-shelf (COTS) components. The primary objective is to ensure high reliability for mission-critical power systems while adhering to strict cost constraints. In order to achieve this objective, the design incorporates a robust analog control circuit, thereby avoiding the complexities and potential single-point failures associated with digital controllers. A comprehensive study of various cell-balancing topologies was conducted, leading to the selection, hardware implementation, and comparative analysis of the two most suitable candidates. The results of this study provide a validated, cost-effective, and reliable battery equalizer solution for developers of small satellites.

1. Introduction

The space industry has been transformed in recent decades, driven largely by the adoption of the CubeSat standard [1], which has led to an exponential increase in the number of satellites being launched and planned [2,3]. This trend can be attributed to the emergence of a novel philosophy known as “New Space” in the late 1990s [4]. This concept emphasizes the maintenance of a balanced budget and the acceleration of the development cycles by the use of commercial off-the-shelf (COTS) components, despite recent advances in new technologies for integrated circuits [5,6,7]. Consequently, this has reduced the entry barriers, which has garnered the interest of numerous non-space sectors seeking to undertake the launch of their own microsatellites, who have enabled technological transfer from their areas.

The emergence of the “New Space” industry has also prompted the adoption of commercial 18650 Li-ion battery cells for space applications [8,9]. Despite the adoption of this energy storage option, it should be noted that a group of cells of the same model usually exhibit discrepancies in characteristics such as capacity, internal resistance, or self-discharge [10]. Although a screening process is typically implemented to create matched sets, differential aging can exacerbate these inconsistencies, leading to increased voltage divergence. Thus, the inclusion of a cell equalization circuit in satellites is crucial to ensure voltage balance and promote the safer, more reliable operation of the battery pack.

The objective of this paper is to design a CubeSat battery equalizer circuit for a deep space mission under the New Space philosophy. High reliability was the main aspect of the design, and an analog control circuit was implemented. Moreover, multiple balancing topologies were studied, culminating in the implementation and comparison of the most viable candidates.

The primary contribution of this paper is the implementation of two prototypes of battery equalizers in order to compare them. Furthermore, while it is true that other studies of this type exist, they have all been conducted in the context of electric vehicles. This paper focuses on space applications, where the environment is different, and other challenges need to be considered [11].

The key contributions of this article are outlined below:

• Study of the state of the art: this work included a study of the existing balancing cell methods.
• Implementation of two potential equalizers for space applications. these topologies were implemented with COTS components in order to assure the scalability and the ease of implementation.
• Comparative analysis: a thorough comparative analysis of the chosen equalizer designs was performed.

2. Study of the Existing Battery Cell Balancing Methods

Nowadays, advancements in technology have increased the quantity of equalizer topologies. Many of these new designs are based on FPGAs or microcontrollers, which are used for determining the state of charge (SoC) and state of health (SoH) of battery cells, thereby optimizing the equalization process [12,13]. Despite this, in this study, it was decided to use topologies with an analog design in order to improve the reliability of the final system. These types of topologies can be found in [14,15].

In this study of the existing balancing methods, the equalizers were divided into five groups according to their balancing method:

• Resistor equalization (RE): excess energy is dissipated through resistors.
• Switched capacitor equalization (SCE): these circuits transfer energy by charging and discharging capacitors.
• Switched inductor equalization (SIE): in this case, inductors are used to supply current to discharge cells from the most charged cells.
• Resonant switched capacitor equalization (RSCE): these circuits typically improve SCE performance by incorporating resonance, which reduces switching losses.
• Converter-based equalization (CBE): power converters facilitate energy transfer for equalization.

Another crucial aspect of each balancing method is the energy transfer path during the equalization process. The literature identifies six distinct types of balancing modes:

• Cell-to-resistor (C2R) is associated with passive equalizers, surplus energy is dissipated in resistors and not reused by other cells.
• Adjacent cell-to-cell (AC2C): energy transfer is limited to adjacent cells, often resulting in slower balancing.
• Direct cell-to-cell (DC2C): energy is moved directly between cells.
• Pack-to-Cell (P2C): energy flows from the entire battery pack to cells with the lowest voltage.
• Cell-to-Pack (C2P): this is the inverse of P2C, where the cells with highest voltage charge the entire battery pack.
• Any cell to any cell (AC2AC): energy can be transferred among all cells simultaneously.

Table 1. Balancing methods compilation. For the number of components: switches (SW), resistors (R), inductors (L), capacitors (C), diodes (D), and transformers (T).

Balancing Topology Name		Balancing Method	Balancing Mode	Number of Components
				SWs	Rs	Ls	Cs	Ds	Ts
FRE	Fixed Resistors	RE	C2R	0	n	0	0	0	0
SRE	Switched Resistors	RE	C2R	n	n	0	0	0	0
CSCE	Classical SCE [16]	SCE	AC2C	2n	*	0	n − 1	0	0
CSSCE	Chain-Structured SCE [17]	SCE	AC2C	2n + 4	*	0	n	0	0
DTSCE	Double-Tiered SCE [18]	SCE	AC2C	2n	*	0	n	0	0
DSSCE	Delta-Structured SCE [19]	SCE	AC2C	2n	*	0	½(n2 − n)	0	0
MSSCE	Mesh-Structured SCE [20]	SCE	AC2C	2n	*	0	2n	0	0
SPSSCE	Series–Parallel-Structured SCE [21]	SCE	AC2AC	4n	*	0	n	0	0
PSSCE	Parallel-Structured SCE [22]	SCE	AC2AC	2n	*	0	n	0	0
SSSCE	Star-Structured SCE [23]	SCE	AC2AC	2n	*	0	n − 1	0	0
SMSCE	Switch-Matrix SCE [24]	SCE	AC2AC	2n	*	0	1	0	0
RSCE	Resonant SCE [25]	RSCE	AC2C	2n	*	n − 1	n − 1	0	0
SPSRSCE	Series–Parallel-Structured RSCE [26]	RSCE	AC2AC	4n	*	n	n	0	0
PSRSCE	Parallel-Structured RSCE [27]	RSCE	AC2AC	2n	*	n	n	0	0
SSRSCE	Star-Structured RSCE	RSCE	AC2AC	2n	*	n − 1	n − 1	0	0
MFCBE	Multiwinding Flyback CBE [28]	CBE	P2C	1	0	0	n	n	1
SFCBE	Single Flyback CBE [15]	CBE	P2C	n	0	0	n	n	n

provides an overview of the main equalizer topologies from the literature. All entries are classified according to the aforementioned categories. Furthermore, the number of components needed for the implementation is indicated. Please note that in certain topologies, the number of resistors cannot be determined (‘*’), because it is determined by the final implementation.

After studying all the relevant existing equalizer topologies, a thorough selection process was conducted based on the desired application: a CubeSat operating in the harsh environment of a deep space mission. In this context, designing fault-tolerant circuits, also known as single-point failure-free (SPFF) designs as shown in [29], is critical to ensure mission longevity and prevent premature operational failures. Another critical consideration is efficiency. Deep space missions often experience reduced solar radiation, which directly impacts the available power. Therefore, identifying an optimal balance between efficiency and high reliability is crucial.

Furthermore, the chosen topologies must be suitable for analog control and the use of COTS components, which is a fundamental principle of the New Space philosophy. In CubeSat missions beyond Earth’s orbit, where systems must operate reliably under severe conditions, ensuring fault tolerance using readily available components is critical to the design.

Considering these factors, passive balancing topologies were dismissed. Although they are a viable alternative for low-earth-orbit (LEO) CubeSats, their inherently low efficiency makes them unsuitable for deep space applications.

Within the SCE-based topologies, it is noteworthy that certain versions were not well suited for the purpose of this work. This was due to the fact that the failure of capacitors was considered. Multiple events can degrade the capacitor properties and precipitate a failure [30]. For instance, in the classical SCE (CSCE), where equalization occurs between adjacent cells, a failure in an equalizing branch renders the process incorrect and can lead to cell unbalancing. The same issue applies to the chain-structured SCE (CSSCE), the series–parallel-structured SCE (SPSSCE), and the switch-matrix SCE (SMSCE). A similar, though less severe, phenomenon can be observed in the star-structured SCE (SSSCE), the parallel-structured SCE (PSSCE), and the double-tiered SCE (DTSCE), where some failures can be tolerated. However, if an equalization branch breaks into an open circuit, other topologies could continue the equalization process, as seen with the delta-structured SCE (DSSCE) and the mesh-structured SCE (MSSCE).

For these reasons, this work focused on two equalizer circuits that were easier to implement from an SPFF perspective: the DSSCE and the SFCBE. The following section details the implementation of these two topologies for further study.

3. Implementation of the Selected Balancing Methods

Following the comparative analysis presented in the previous section, two topologies were selected for implementation and experimental evaluation in a four-cell battery balancing circuit: delta-structured switched capacitor equalizer (DSSCE) and single flyback converter-based equalizer (SFCBE). This section details the implementation of these two balancing methods, explaining their operating principles and design considerations.

3.1. Delta-Structured Switched Capacitor Equalizer

This section describes the implementation of a passive balancing method based on a switched capacitor architecture. The principle of operation is based on the periodic connection of adjacent cells through capacitors, allowing the redistribution of the cells’ charge without the need for magnetic components. The Figure 1A shows the electric schematic diagram of the topology.

The main reason for choosing this topology is the ease of converting it into a fault-tolerant circuit. The multiple energy transfer paths allow continuous operation if any transistor or capacitor fails. It is worth noting that it is necessary to place a fuse in series with each switch, so in case of a short-circuit, the affected branch is disconnected, ensuring that the remaining components maintain balance without any problems.

As stated in [19], there are two asymptotic limits that have great importance in the selection of the switching frequency in this balancing method: the slow-switching limit (SSL) and the fast-switching limit (FSL).

On the one hand, in the SSL the capacitors have enough time to fully charge and discharge during each switching period. Its associated resistance R_SSL is dominated by the capacitive elements, and energy losses are mainly due to the finite amount of charge transferred through the balancing capacitors. According to [31], for this specific configuration, this parameter can be calculated with Equation (1).

$$R_{SSL}={\displaystyle \frac{2.88}{C·f_{sw}}}$$

(1)

where 2.88 is the sum of the multiplier coefficient of the capacitors, $C$ is the capacity of the balancing capacitors, and $f_{sw}$ is the switching frequency.

On the other hand, in the FSL the capacitors do not reach full voltage equilibrium during each phase. Its associated impedance R_FSL is governed by the conduction losses across the switches and can be calculated with Equation (2), which was developed in [19].

$$R_{FSL}=5·R_{eq}$$

(2)

where 5 is the double of the sum of the multiplier coefficients of the switches, and $R_{eq}$ is the sum of the ON drain–source resistances of the switches and the measured PCB traces’ resistance.

According to [31], if an efficient design is intended, both impedances must be equal, obtaining Equation (3).

$$C={\displaystyle \frac{2.88}{5·R_{eq}·f_{sw}}}$$

(3)

Through this expression, it is possible to choose an optimal theoretical operating point where neither conduction losses nor switching losses dominate the system. Figure 2 illustrates the R_FSL impedance, as well as several R_SSL impedances as functions of the switching frequency for different C values with R_eq = 190 mΩ. As can be seen at lower frequencies, the energy losses due to energy transfer are higher. Furthermore, it is important to note that at higher frequencies, the switching losses of the system are higher, and the influence of the stray inductances in the real implementation is also greater. Consequently, it is necessary to consider all type of losses in the selection of the optimal operating point. In this particular case, it was determined that a capacity of 60 µF for the balancing capacitor and a frequency of 50 kHz were the optimal values for this implementation.

Table 2. Main components of the design of the DSSCE topology implemented.

Component	Manufacturer	Manufacturer Number
Driver	Texas Instruments (Dallas, TX, USA)	UCC27425QDRQ1
Transformer	Coilcraft (Cary, IL, USA)	DA2320-AL
Transistors	Nexperia (Nijmegen, The Netherlands)	PMV19XNEAR
Balancing capacitors	KYOCERA AVX (Fountain Inn, SC, USA)	12103C106K4Z4A

presents the manufacturer and product number of the main components of the equalizer. It is important to note that the total capacity of the balancing capacitors was achieved by using six 10 µF capacitors in parallel in the indicated model. Consequently, this approach resulted in a substantial decrease in the total ESR of the capacitors.

3.2. Single Flyback Converters Based Equalization

This section outlines the design of the SFCBE topology. This architecture consists of ‘n’ flyback converters, where ‘n’ is the number of battery cells used to transfer energy from the most-charged cells to the less-charged ones. Figure 1B shows an electric schematic diagram of the SFCBE topology.

This topology is not faithfully based on any equalizer in the literature. The main idea is based on the MFCBE topology presented in [32], and a general overview is presented in [15]. In this proposed topology, a single flyback converter was implemented per cell. This choice allowed the use of COTS transformers instead of custom ones. A transformer with one primary winding and one secondary winding with a specific transformer ratio was easier to find than one with multiple secondary windings. Choosing this type of transformer offered additional advantages. For instance, compactness is a key factor in microsatellite applications, and COTS transformers are generally smaller. Another benefit is the precision of the inductance values; the primary and secondary windings of COTS transformers tend to exhibit more consistent inductance, which enables better matching across converters.

When selecting a COTS transformer, it is crucial to consider the nominal input and output voltages of the flyback converters. In this design, the primary winding is connected to the battery voltage, and the secondary winding is connected to the terminals of a battery cell. Consequently, the required turn ratio is defined by the number of cells; in this case, a 4:1 ratio was used.

With this information, a study of the existing commercial transformers was conducted. In

Table 3. COTS transformer compilation.

Manufacturer Number	LP (µH)	Lleak (µH)	Manufacturer	Height (mm)
750311558	300	3	Würth Elektronik	10.54
750311559	175	3	Würth Elektronik	10.54
750313973	40	1	Würth Elektronik	11.43
750311625	9	0.5	Würth Elektronik	12.7
TA7608	2	0.06	Coilcraft	5.97
ZB1050	12.5	0.4	Coilcraft	10
ZA9670	9	0.4	Coilcraft	10
NA5743	4	0.116	Coilcraft	11.43

, a summary of some of the most suitable COTS transformers is presented. The selection of the correct transformer was driven by the primary inductance. This was because discontinuous conduction mode (DCM) was required for this design. This mode ensures the transformer fully discharges its stored energy before the next switching cycle begins, avoiding core saturation. Under this mode, the peak current through the secondary winding in each switching cycle is given by Equation (4).

$$I{s}_{max}={\displaystyle \frac{V_{BAT}·D}{fsw·n·L_P}}$$

(4)

Assuming a preliminary duty cycle of 40% to ensure DCM, it can be deduced that higher primary inductance values require lower switching frequencies. Higher values of frequencies are associated with higher switching loses, so it is critical to find a compromise between frequency and switching losses. Moreover, each transformer has a range of frequencies in which it can operate that must be respected.

According to Table 3 and Figure 3, the only transformer capable of providing the required balancing current at an appropriate switching frequency (250 kHz) was the Würth Elektronik 750311558 (Niedernhall-Waldzimmern, Germany), which had a primary inductance of 300 µH with a leakage inductance of 3 µH.

Concerning the control circuit design, we implemented an analog circuit that enabled the use of dc–dc converters associated with the most discharged cells, more specifically, the cells that had a voltage value that was below the average voltage of all cells.

In

Table 4. Single flyback characteristics.

Parameter	Value	Units
VIN	VBAT	-
VOUT	VBAT/4	-
N	4	-
LP	300	µH
Lleak	3	µH
Frequency	250	kHz

, the main characteristics of the flyback converters implemented for this equalizer are presented, and

Table 5. Single flyback main components.

Parameter	Manufacturer	Manufacturer Number
Driver	Texas Instruments	UCC27624QDRQ1
Transformer	Würth Elektronik	WE Ref: 750311558
Transistor	STMicroelectronics (Geneva, Switzerland)	STL8N6LF6AG
Diode	Nexperia	PMEG40T30ERX

provides the references for the main components in the implementation.

4. Experimental Setup

This section describes the experimental setup used to evaluate the performance of the implemented voltage equalizer topologies. It provides detailed information on the laboratory equipment, battery pack specifications, and developed PCB prototypes. All the test scenarios established to validate each balancing strategy are also introduced, enabling equitable comparison between the proposed implementations.

4.1. Equipment

To conduct the experiments, a controlled temperature of 25 °C in a dry environment was maintained. Moreover, in the tests of both circuits, specialized equipment was employed to ensure the precise control of the testing conditions and high-resolution data acquisition. The voltage of each cell was measured with an Agilent 34410A multimeter (Santa Clara, CA, USA). In addition, in order to automate data acquisition, a Python program was developed in its version 3.13.

4.2. Battery Pack

In order to make this study possible, a battery pack of four Li-ion cells in series was employed. Specifically, we used the B18650CA cell from BAK (Shenzhen, China).

Table 6. Battery characteristics.

Parameter	Value	Unit
Number of cells	4	-
VBAT	10.8–16.8	V
VCELL	2.7–4.2	V
Energy	8.1	Wh
Cell energy	32.4	Wh
Capacity	2250	mAh
Cell capacity	2250	mAh

shows the main parameters of the implemented battery pack.

To have a deeper understanding of the cells used, an electrochemical impedance spectroscopy (EIS) measurement was performed at 25 °C of each cell of the battery. The impedance data were fitted to an equivalent circuit model that is commonly used in the characterization of Li-ion cells, such as in the study presented in [33]. Figure 4 shows a schematic diagram of that model, and Figure 5 shows the data measured from all the cells.

Table 7. Fitted parameters of the EIS measurements.

Parameter	Cell 1	Cell 2	Cell 3	Cell 4	Unit
L	335.549	329.070	344.549	357.609	nH
RS	26.822	27.634	28.308	26.497	mΩ
R1	8.173	3.290	8.021	3.397	mΩ
R2	0.832	0.976	0.855	0.986	mΩ
TCPE1	0.268	1.763	0.238	1.630	-
pCPE1	3.331	8.449	3.102	8.261	-
TCPE2	0.936	0.845	0.981	0.852	-
pCPE2	1.912	0.241	1.727	0.242	-
σW1	1.898	1.785	1.835	1.797	mS·s0.5

presents the fitted parameters that were obtained through the EIS measurements. The resistance value R_S represents the ohmic resistance of the cell. In this instance, the mean value was 27.316 mΩ, which was considered during the design of the balancing circuits. It is important to note that a low R_S indicated that this cell model was suitable for this study. Nevertheless, further analysis is required to confirm its suitability for space applications, as conducted in [33]. The remaining parameters were not considered due to their negligible impact on the final performance of the equalizers.

4.3. PCB Prototypes

To validate and compare the proposed balancing topologies, two cell-balancing prototypes were designed and fabricated. Figure 6 presents the PCBs of the two implementations, and Figure 7 shows the setup for the tests performed.

4.4. Balancing Scenario

To evaluate the performance of the proposed balancing methods, four test scenarios were defined, each with a different initial voltage distribution in the battery cells. These scenarios were carefully selected to represent possible exaggerated imbalance conditions in order to assess the performance of each topology. This range of scenarios enabled a comparison of balancing speed and energy consumption. The initial cell voltages for all scenarios are presented in

Table 8. Initial cell voltages in each scenario.

	Cell 1 [V]	Cell 2 [V]	Cell 3 [V]	Cell 4 [V]
Scenario 1	3.7	3.8	3.9	4
Scenario 2	4	3.7	3.7	4
Scenario 3	3.7	4	4	3.7
Scenario 4	4	3.7	4	3.7

and served as the starting point for the experiments.

In order to facilitate a more intuitive understanding of the initial conditions in each scenario, Figure 8 represents a visual of the cell voltages described in the previous table. Each subplot corresponds to one of the four test scenarios.

5. Results

The following section presents the results of the tests that were carried out in this work. As mentioned before, different scenarios were used for the tests. These tests were conducted in a static scenario, in which the battery was not being charged or discharged. Figure 9 shows the results of all the tests performed. The first column is associated with the DSSCE and the second column with the SFCBE. Each row is associated with a specific scenario. The first row corresponds to the first scenario, and the last row corresponds to the fourth scenario.

In order to provide a more straightforward basis for comparison, the balancing speeds from the graphs in Figure 9 are collected in

Table 9. Time to reach each level of equalization in hours.

	DSSCE			SFCBE
Gap	100 mV	50 mV	20 mV	100 mV	50 mV	20 mV
Scenario 1 [h]	5.617	10.420	18.177	3.855	4.794	5.561
Scenario 2 [h]	1.926	3.320	5.671	3.952	5.081	5.656
Scenario 3 [h]	1.917	4.316	7.928	4.331	5.365	11.653
Scenario 4 [h]	2.702	5.291	10.782	4.368	5.416	6.047

. This table contains the time required for each topology to balance up to a certain voltage difference between the most-charged and the least-charged cell.

As previously demonstrated, the DSSCE exhibits a more rapid balancing rate during the initial stages, where the voltage differences between the cells are more pronounced. However, as the voltages begin to equalize, the SFCBE maintains a more consistent balancing rate through the process. Furthermore, in the initial scenario where the conditions are less favorable for the DSSCE, the SFCBE demonstrates superior performance.

On the other hand, it is worth noting in Figure 9 that the final voltage of the cells after equalization is always higher with the DSSCE than with the SFCBE. This means that the efficiency of the DSSCE is higher, and the losses associated with the equalization method are lower. For a better understanding, in

Table 10. Battery voltage after equalization.

	DSSCE			SFCBE
Gap	100 mV	50 mV	20 mV	100 mV	50 mV	20 mV
Scenario 1 [V]	15.420	15.394	15.386	15.312	15.279	15.268
Scenario 2 [V]	15.428	15.44	15.443	15.264	15.224	15.206
Scenario 3 [V]	15.399	15.399	15.398	15.344	15.322	15.301
Scenario 4 [V]	15.405	15.414	15.412	15.291	15.267	15.253

the battery voltage is shown after the equalization for different cell gaps.

6. Discussion

The experimental results presented in the previous section allow a detailed comparison between the balancing topologies developed in this study. The DSSCE topology has reduced power consumption and achieves faster balancing when significant voltage imbalances are present between the cells. However, it should be noted that the efficacy of the device is reduced as the voltage differences decrease. Moreover, due to the greater number of components employed in this architecture, a larger PCB area is required.

Conversely, the SFCBE topology consumes a greater amount of power. Nevertheless, it performs more efficiently when voltage mismatches are minimal, ensuring a more consistent balancing rate throughout the process. The compact design and reduced component count facilitate a smaller PCB footprint. However, it should be noted that these advantages are accompanied by a reduction in fault tolerance and an increase in design complexity.

Both implementations employ a configuration with four cells in series (4S), which is representative of the most common CubeSat battery packs. As demonstrated in the existing literature [8,34,35], 18650-based batteries with 2S to 4S configurations are utilized to supply regulated 8 V to 16 V buses. It is noteworthy that in certain 6U or larger CubeSats, configurations may extend up to 8S. These are compatible with both of the studied topologies, although they require more components and larger PCB area. Therefore, the selected topologies are well suited for typical CubeSat battery configurations. Nevertheless, scaling beyond this range has the potential to present new challenges, such as temperature variations across the entire battery pack.

The designs presented were adapted for use with 18650 lithium-ion cells. However, the application of these equalizers to other chemistries employed in CubeSats, such as LiPo or NiMH [36], would require adjustments to the operating voltage and internal impedance values. For example, in the case of NiMH cells, they have a lower voltage per cell (approximately 1.2 V per cell). Additionally, NiMH cells have a higher internal impedance, which contributes to increased losses in the equalizer. Consequently, it may be necessary to re-optimize the capacitor values and switching frequency in order to match the new voltage and impedance levels. Concerning LiPo cells, it should be noted that their minimum voltage is higher than that of Li-ion cells (at precisely 3.2 V) and they exhibit a lower internal impedance. For this reason, it would be necessary to adjust the transformer design in order to support lower nominal voltages. Furthermore, the self-discharge of the cells and the maximum charge current could affect the balancing strategies.

Another point to be considered is that, as stated in the ‘Experimental Setup’ Section, the tests were conducted at 25 °C in a dry environment. In the context of deep space exploration, significant temperature fluctuations can be experienced by the cells, which can compromise the performance of the equalizer. As demonstrated in [33,37], Li-ion batteries exhibit increased internal resistance, diminished lithium diffusion, and reduced capacity at low temperatures. In order to mitigate the effects of temperature fluctuations, the use of heaters is the most common solution in the context of space missions. It is possible to ensure that cells are maintained within an operational temperature range by using this method. Consequently, this approach approximates the observed behavior in the tests. However, aside from the effect of temperature, vacuum conditions can also influence the performance of equalization circuitry. In particular, insulation behavior under vacuum conditions must be carefully assessed, as arcing risks or dielectric breakdown between adjacent traces may increase at low pressure if proper spacing is not ensured [38,39,40].

Notwithstanding the absence of specific electromagnetic compatibility (EMC) tests, this aspect is critical in satellite design. Both topologies are likely to produce low electromagnetic interference (EMI) due to their low-frequency switching [41]. In future iterations, the incorporation of shielding should be considered for meeting the ECSS-E-ST-20-07C standard of the European Cooperation for Space Standardization (ECSS) [42], which defines the EMC standards that are applicable to space systems.

Another type of test that was not conducted in this study was the long-term test. However, the reliability of both topologies in extended missions can be pre-evaluated by analyzing potential failure modes under space conditions. On the one hand, in the DSSCE topology, the balancing process depends on the use of ceramic capacitors and MOSFET switches. As discussed in [43], ceramic capacitors are susceptible to microcracking and capacitance loss when they are subjected to prolonged thermal cycling or mechanical stress, particularly in a vacuum. Furthermore, it has been demonstrated that radiation can induce changes in the parameters of MOSFETs [44,45,46], which may consequently affect switching behavior. These effects could lead to a reduction in charge transfer efficiency, slower voltage convergence between cells, and increased power losses due to higher ESR or deficient switching transitions. On the other hand, in the SFCBE topology, apart from the MOSFETs, the flyback transformers are critical components for energy transfer. According to the findings reported in reference [47], radiation exposure can cause variations in core properties. Such degradation may reduce the transformer’s ability to transfer energy efficiently between cells and increase switching stress in the control circuitry. Therefore, the appropriate derating of component, shielding, and environmental qualifications is necessary to prevent such degradations from compromising the long-term balancing performance of both circuits.

While the present study provided experimental validation under controlled laboratory conditions, it is important to note that it represents an intermediate step toward the eventual development of a flight-qualified system. In future lines of this work, the present study provides the knowledge for the selection of the most suitable topology for a battery management system (BMS) of a 6U CubeSat intended for deep space missions. This system is specially designed to operate under low-temperature conditions and harsh radiation environments of deep space. For that reason, a dedicated PCB (see Figure 10) was developed and will undergo environmental qualification campaigns, including thermal vacuum (TVAC), vibration, and total ionizing dose (TID) tests. The experimental tests will facilitate the evaluation of the system’s robustness and reliability under realistic deep space conditions.

7. Conclusions

This article provides an extensive evaluation of two cell-balancing topologies for their use in space applications. DSSCE and the SFCBE architectures were designed, developed, and tested, enabling a comparison of the balancing speed, design complexity, and fault tolerance.

With the information obtained in this work, the DSSCE topology was selected as the most appropriate solution for its integration into a BMS of large CubeSats intended for deep space missions. In those environments, fault tolerance circuits are crucial due to the increased risk of radiation failures. In contrast, the SFCBE topology may be a more appropriate choice for smaller CubeSats operating in LEO, where the environment conditions are less severe, the available space is more limited, and solar irradiance is high.