Numerical Analysis for Cost-Effective Temperature Reduction in High-Power Light-Emitting Diodes Using Thermal via Array

Abstract

The dissipation of excessive heat in high-power light-emitting diodes (LEDs) is essential for maintaining luminous efficiency, color stability, and device lifetime. While the incorporation of thermal vias in substrates is commonly used to improve heat dissipation, increasing their number is difficult in the limited area due to fabrication constraints. In this study, we use finite element analysis to investigate the effects of thermal via configurations on LED performance, including variations in the number of vias, spacing between vias, and their misalignment relative to the LED, arising from manufacturing tolerances. We found that the reduction in LED temperature saturated beyond a certain number of vias. Moreover, heat reduction can be further enhanced by optimizing the spacing between vias under a fixed number of vias. Based on these findings, the design of via configurations can achieve both fabrication feasibility and effective heat dissipation in high-power LEDs.

1. Introduction

Light-emitting diodes (LEDs) have largely replaced traditional light sources due to their high energy efficiency and long lifetime. Thermal management in high-power applications is crucial as the majority of input energy—typically 70–85%—is dissipated as heat [1,2]. Inadequate heat dissipation leads to a self-reinforcing temperature rise, significantly degrading LED performance and reliability [3,4,5,6,7,8]. As high-density LED devices have emerged, the importance of thermal management has become increasingly evident [9,10]. For instance, micro-LED array panels generate continuous heat within confined regions, which can severely impact device performance. In flexible LEDs, the inherently low thermal conductivity of substrate materials imposes additional constraints on thermal management. LEDs integrated on polyimide substrates often lack sufficient thermal conduction layers, resulting in substantial reductions in optical output and overall device performance [11]. The design of high-density LED arrays, including the output power of individual chips, the number of LEDs, and their spatial arrangement, plays a crucial role in achieving effective heat distribution, thereby reducing the overall thermal resistance of the system [12].

Various approaches have been explored to enhance heat dissipation, including the use of high thermal conductivity packaging materials [8,13,14] and external thermal management components such as heat sinks [15,16,17,18], heat pipes [18,19], and active cooling systems [14,20,21]. The heat dissipation performance of these methods strongly depends on power output and device form factor.

Heat sinks, typically composed of highly thermally conductive materials (e.g., aluminum or copper), dissipate heat by increasing the effective surface area exposed to the surrounding air. Radial heat sinks, which feature symmetrically arranged fins around a central axis, have been widely adopted, with key design parameters such as base thickness and fin geometry optimized to enhance thermal dissipation efficiency [15,16,17,18]. In addition, various fin designs, such as staggered, elliptic, or twisted geometries, have been developed to further facilitate effective natural convection cooling [22,23].

Heat pipes enable efficient heat transfer to remote cooling surfaces through the phase change of a working fluid involving evaporation and condensation. In LED devices, they have demonstrated significant reductions in thermal resistance, particularly in compact or enclosed environments. Beyond the conventional cylindrical shape, loop-type or flat-type heat pipes with micro-grooves have been proposed for high-power LEDs [24,25,26]. Moreover, transient modeling of heat pipe behavior has enabled accurate prediction of thermal hysteresis and dryout recovery dynamics [27].

Active cooling systems, such as miniature fans or thermoelectric modules, are commonly employed to dissipate heat using external power. While they offer fast response and localized cooling capability, they are often hindered by relatively low energy efficiency. For example, the coefficient of performance of thermoelectric modules remains significantly below that of traditional refrigeration systems, limiting their use in high-precision applications [28]. Moreover, although hybrid designs integrating phase-change materials or immersion cooling techniques have been proposed, their compact, scalable integration in miniaturized LED systems is elusive [29,30].

In another approach, thermal vias are embedded in substrates to provide efficient heat dissipation pathways. These sub-millimeter-scale vertical holes, fully filled or coated with highly thermally conductive materials, facilitate heat transfer from LEDs to underlying heat management components [31,32]. Thermal vias reduce the thermal resistance of devices by providing direct, high-conductivity pathways from the LED junction to the underlying heat-spreading layers. In contrast, heat sinks, heat pipes, and active cooling techniques are primarily designed to enhance heat dissipation to the ambient environment rather than directly controlling the internal thermal resistance of the system. In terms of cost, thermal vias are considered a cost-effective solution, as they can be implemented using standard substrate fabrication processes without requiring additional components. Also, circuit layouts and substrate dimensions remain unchanged with the implementation of vias, enabling their integration into various device form factors. Therefore, the integration of vias is a practical and scalable thermal management solution in compact, high-power LED devices.

The optimization of via configurations is essential for enhancing heat dissipation efficiency [31,32,33,34,35]. For instance, the heat transfer performance of vias improves when positioned close to heat sources, such as directly beneath LEDs rather than in peripheral regions. However, the number of vias is constrained by the minimum manufacturable feature size of the holes and the required spacing between them. In addition, increasing via density can introduce fabrication complexity, imposing further constraints on their practical implementation. Furthermore, localized heat accumulation caused by low substrate thermal conductivity or weak interlayer adhesion may offset the benefits of increasing via number and density.

In detailed thermal via configuration, parameters such as dimensions, location, number, and even misalignment due to manufacturing tolerances are interdependent and thus require comprehensive analysis. However, previous studies have often addressed these factors individually using simplified models. Furthermore, these parameter studies have rarely been evaluated in relation to the associated fabrication cost and complexity. As discussed later, the marginal thermal gains from increasing the number of vias gradually decrease, which reduces efficiency relative to the increased fabrication complexity.

In this study, we analyze the temperature reduction in high-power LEDs under various thermal via designs using three-dimensional (3D) finite element analysis (FEA). We investigate the peak value and distribution of temperature in the LED and the substrate under various via configurations, including their number, pitch (center-to-center distance), and positional misalignment. We found that the LED temperature saturates as the number of vias increases. For a given number of vias, comprehensively adjusting their pitch further reduces the LED temperature. Misalignment of the via array significantly degrades heat dissipation performance, particularly at lower via densities. This study provides a systemic approach to designing thermal via layouts while accounting for fabrication reliability in high-power LED systems. Such an approach can also be applied as a versatile framework for pixel-level thermal management in a wide range of thermally constrained applications.

2. Methods

A transient 3D thermal analysis was conducted using the Heat Transfer in Solids interface in COMSOL Multiphysics (version 5.2). The governing equation for heat conduction is expressed as:

$$\rho C_{\mathrm{P}}{\displaystyle \frac{\partial T}{\partial t}}=\nabla \cdot \left(k\nabla T\right)+Q$$

(1)

where ρ is the density (kg/m³), C_p is the specific heat capacity (J/kg·K), k is the thermal conductivity (W/m·K), T is the temperature (K), and Q is the volumetric heat generation rate (W/m³). The equation for radiation is expressed as:

$$-n\cdot q=\epsilon \sigma (T_{\mathrm{a}\mathrm{m}\mathrm{b}}^4-T^4)$$

(2)

where T_amb is the ambient temperature (K), q is the heat flux vector, n is the unit outward normal vector, ε is the surface emissivity, and σ is the Stefan–Boltzmann constant (W/m²⋅K⁴). In this study, convection was neglected based on the assumption that heat conduction dominates over convection due to the small size of the LED die, as supported by previous studies [21,36,37,38,39,40]. Figure 1a illustrates the LED module model used in this study. The simulation domains include an LED chip, solder layer, substrate, copper layers, thermal interface material (TIM), and heat sink (Figure 1b). The LED chip with a footprint of 1 × 1 mm², representative of high-power LEDs [32,41], is mounted at the center of the 2.8 × 2.8 mm² substrate with the solder interlayer. Solid copper layers are laminated on the top and bottom surfaces of the substrate (25 μm thick for the top layer and 20 μm thick for the bottom layer). The substrate is attached to the heat sink via TIM. Thermal vias are vertical holes with a diameter of 0.1 mm, fully filled with copper, a design commonly used in high-density printed circuit boards (PCBs) [32]. The detailed material properties and geometric parameters of each component are summarized in

Table 1. Material properties and geometrical parameters of each domain in the simulation.

Category	Material	Width × Depth [mm2]	Height [mm]	Thermal Conductivity [W/(m·K)]
LED Chip	GaN	1 × 1	0.05	130
Solder	60Sn-40Pb	1 × 1	0.025	50
Top Cu layer	Cu	2.8 × 2.8	0.025	400
Substrate	FR4	2.8 × 2.8	0.1	0.3
Bottom Cu layer	Cu	2.8 × 2.8	0.02	400
TIM	Resin-bonded glass fiber board	2.8 × 2.8	0.01	4
Heat Sink	Al	6 × 8	4.5	238

.

The initial temperature for all domains was set to 25 °C. A uniform heat flux of 1.5 × 105 W/m² was applied to the top surface of the LED chip to simulate heat generation. Adiabatic boundary conditions (−n·q = 0) were imposed on the lateral surfaces of all domains except for the heat sink to prevent heat loss. The outer surfaces were subject to surface-to-ambient radiation boundary conditions with an emissivity of 0.85. Two-dimensional temperature distributions were extracted from the top surface of the LED chip (Monitor 1) and the substrate (Monitor 2), as shown in Figure 1b.

To balance computational efficiency and accuracy, a physics-controlled mesh (normal setting) was applied, with locally refined elements in regions of high thermal gradients, particularly around the LED chip and the substrate (Figure 1c). Insufficient mesh refinement in these critical areas can lead to errors in temperature estimation and diminished local resolution. The mesh size in the reference model, including the heat sink, consisted of over 30,000 domain elements and 1000 edge elements. The minimum element quality, based on skewness, was 0.0078, and the average quality was 0.5235, both of which are suitable for stable numerical calculations. Mesh refinement had no noticeable effect on the resulting temperature distribution.

In this study, T_LED is defined as the maximum temperature within the LED chip, and ΔT_LED represents the temperature difference across the chip. Similarly, T_sub and ΔT_sub denote the maximum temperature and the temperature difference within the substrate, respectively. Temperature data were collected after the system reached a steady thermal state. As shown in Figure 2a, T_LED rapidly increased during the initial stage and began to plateau around 600 s, indicating that the thermal equilibrium had been reached. A time point of 1500 s was chosen for analysis to ensure that the system had fully stabilized. Regardless of the presence of thermal vias, T_LED and T_sub were consistently measured on the Monitor 1 and Monitor 2 planes. The lowest temperature within the substrate was observed at the bottom surface of the substrate, remaining at approximately 63–64 °C across all simulation cases, independent of the thermal via configurations (Figure 1b). This indicates that the heat sink serves as the primary heat dissipation pathway under steady-state conditions [27,42]. As a reference case, T_LED and T_sub reached 129 °C in the absence of thermal vias (Figure 2b,c).

3. Results and Discussion

Figure 3 presents a comparative thermal analysis with varying numbers of thermal vias. Thermal via arrays with uniform pitch were placed beneath the LED chip. For via numbers ranging from 1 to 9, the pitch was fixed at 0.4 mm. For 16 and 25 vias, the pitch was reduced to 0.3 mm and 0.2 mm, respectively, considering the LED footprint and via dimensions (Figure 3a).

As shown in Figure 3b,c, the temperatures of both the LED and substrate decreased with the addition of thermal vias. The spatial distribution of the LED temperature on the Monitor 1 plane was represented by the isothermal contours of 97.9−98.4 °C, 75.8−76.1 °C, 70.6−70.9 °C, and 66.3−66.3 °C for 1, 5, 9, and 25 vias, respectively (Figure 3b). Similarly, the spatial distribution of the substrate temperature on the Monitor 2 plane was 97.6−98.4 °C, 75.3−75.7 °C, 70.5−70.8 °C, and 66.2−66.3 °C, respectively (Figure 3c). The minimum temperature was consistently observed at the center of both the LED and substrate.

The full trends in T_LED, ΔT_LED, T_sub, and ΔT_sub as a function of the number of thermal vias are shown in Figure 4. Even a single thermal via substantially reduced the temperature (T_LED: 129 °C → 98.4 °C; T_sub: 129 °C → 98.4 °C). However, heat dissipation saturates beyond a certain number of vias. For instance, increasing the number of vias from 5 to 9 (80% increase) reduced T_LED by approximately 7.3% (76.1 °C → 70.9 °C), whereas increasing from 9 to 16 (77% increase) resulted in only a 3.95% reduction, and from 16 to 25 (56% increase), the reduction was merely 2.5%. For configurations with 16 or 25 vias, the reduced pitch increased via density, and the greater number of vias expanded the total heat transfer area. However, these changes led to a negligible reduction in temperature. The saturation behavior can be understood by considering the effective cross-sectional area available for heat conduction. In the substrate, parallel heat conduction paths are formed by vias and surrounding substrate material in the vertical direction of the module [14,18,32,43,44,45]. Analytical models describing thermal resistance in such parallel heat conduction paths have been established in prior studies [43,44,45,46]. In our case, the effective thermal resistance (R_sub) across the substrate can be expressed as:

$${\displaystyle \frac{1}{R_{\mathrm{s}\mathrm{u}\mathrm{b}}}}={\displaystyle \frac{k_{\mathrm{v}\mathrm{i}\mathrm{a}}\cdot A_{\mathrm{v}\mathrm{i}\mathrm{a}}}{L}}+{\displaystyle \frac{k_{\mathrm{s}\mathrm{u}\mathrm{b}}\cdot A_{\mathrm{s}\mathrm{u}\mathrm{b}}}{L}}$$

(3)

where k_via and k_sub are the thermal conductivities of thermal via (copper) and substrate material (FR4), respectively (in W/m·K); A_via and A_sub are their respective cross-sectional areas (in m²); and L is the heat path length (i.e., substrate thickness, in meters). The large disparity between k_via (400 W/m·K) and k_sub (0.3 W/m·K) results in a significant reduction in R_sub when even a single via is introduced. While the copper fraction continues to increase with the addition of more vias, its incremental contribution to reducing R_sub becomes marginal due to the already-dominant high-conductivity paths. As a result, the rate of decrease in R_sub gradually diminishes. This diminishing, in turn, emphasizes a fundamental trade-off between thermal performance and manufacturing efficiency. Adding vias becomes impractical due to the increasing PCB complexity and fabrication costs, so the via configuration should remain minimal to ensure feasibility. Building on the analytical model that explains the overall saturation trend, finite element simulations can further evaluate local temperature distributions according to specific geometric parameters of vias.

We analyzed the temperature response with respect to the number of thermal vias using a high thermal conductivity substrate, aluminum nitride (AlN) (180 W/m·K), as shown in Figure 5. Due to the significantly higher thermal conductivity of AlN compared to FR4, the presence or number of vias has a relatively minor influence on the overall thermal performance. Both T_LED and T_sub remain around 63 °C, which is comparable to the performance of a 25-via configuration on an FR4 substrate. This result implies that the inherent thermal spreading capability of the AlN substrate effectively dissipates heat even without a large number of vias, indicating minimal thermal bottlenecking within the substrate.

Mechanical fatigue, such as delamination or cracking, typically occurs at interfaces between materials with mismatched coefficients of thermal expansion [46,47]. These defect sites can propagate rapidly under repeated thermal cycling conditions [48]. Therefore, minimizing temperature fluctuations is essential for enhancing reliability. As shown in Figure 6, during the transient heating stages at 100 s and 400 s, the presence of thermal vias substantially reduces the temperature rise compared to the no-via case. Specifically, T_LED decreases from over 110 °C to below 50 °C at 100 s, and from over 130 °C to below 70 °C at 400 s when more than five vias are implemented. The saturation behavior observed in the quasi-steady-state (at 1500 s) is similarly reflected during these transient stages. This reduction in temperature variation is expected to alleviate thermomechanical stress and enhance reliability under thermal cycling conditions.

Temperature distribution as a function of pitch of the thermal vias was evaluated. Here, five- and nine-via configurations were selected as representative cases for optimized design (Figure 7a,c). For each case, the pitch was varied from 0.2 mm to 0.6 mm. In the five-via configuration, the spatial distribution of the LED temperature on the Monitor 1 plane was 75.5−76.1 °C, 75.4−75.8 °C, 75.8−76.1 °C, and 75.8−76.1 °C for 0.2, 0.3, 0.4, and 0.6 mm pitch, respectively (Figure 7b). In the nine-via configuration, this distribution was 70.8−71.3 °C, 70.7−70.8 °C, 70.6−70.9 °C, and 71.0−71.5 °C, respectively (Figure 7d). The general trend in temperature variation across the Monitor 1 plane became smaller with a higher number of vias. The smallest temperature variations occurred at 0.4 mm pitch for the five-via case (0.3 °C) and at 0.3 mm for the nine-via case (0.1 °C). Those values are far improved from the highest values, 0.6 °C and 0.5 °C at a pitch of 0.2 mm and 0.1 mm, respectively.

The full trends in T_LED, ΔT_LED, T_sub, and ΔT_sub as a function of the thermal via pitch are shown in Figure 8. In the five-via configuration, the temperature variations on both the LED and substrate were minimal across all pitches (Figure 8a). Specifically, T_sub remained nearly constant at 76.1 °C for pitches of 0.2 mm, 0.4 mm, and 0.6 mm, with a slight decrease to 75.7 °C at a pitch of 0.3 mm. The corresponding ΔT_sub values were 13.1 °C for 0.2 mm, 0.4 mm, and 0.6 mm and 12.7 °C for 0.3 mm. These results suggest that adjusting the pitch alone does not significantly improve heat dissipation when the overall via density is low.

In contrast, with nine thermal vias, thermal performance became more sensitive to pitch variation (Figure 8b). At pitches of 0.3 mm and 0.4 mm, T_sub reached the lowest value of 70.8 °C, with ΔT_sub decreasing to 7.8 °C, indicating improved heat spreading and more uniform temperature distribution. At a pitch of 0.2 mm, T_sub slightly increased to 71.3 °C, with ΔT_sub of 8.3 °C. Thermal vias located outside the heat-generating area contributed less to heat conduction, despite a higher number of vias. When the pitch increased to 0.6 mm, the outermost vias were positioned outside the LED chip, leading to degraded thermal performance. T_sub rose to 71.6 °C, and ΔT_sub returned to 8.3 °C, offsetting the benefits of additional vias.

The optimal pitch condition varied depending on the number of vias. For example, the five- and nine-via configurations exhibited the best thermal performance at different pitches (0.4 mm and 0.3 mm, respectively). Therefore, the number and pitch of vias are interdependent design parameters, and adjusting one without considering the other may lead to suboptimal thermal behavior.

The thermal sensitivity to misalignment of thermal vias was investigated by laterally shifting the via array away from the center of the LED chip (Figure 9). Two configurations were examined: five vias with a pitch of 0.3 mm and nine vias with a pitch of 0.2 mm. The center of the via array was offset by (0.1 mm, −0.1 mm), (0.2 mm, −0.2 mm), and (0.4 mm, −0.4 mm) relative to the LED center (Figure 9a,c). In the five-via configuration, the spatial distribution of the LED temperature on the Monitor 1 plane ranged from 75.4−75.8 °C, 75.4−76.3 °C, 75.3−76.6 °C, and 75.3−78.1 °C for offset of (0 mm, 0 mm; no offset), (0.1 mm, −0.1 mm), (0.2 mm, −0.2 mm), and (0.4 mm, −0.4 mm), respectively (Figure 9b). In the case of the nine-via configuration, the corresponding distributions were 70.6−70.9 °C, 70.8−71.8 °C, 70.4−72.4 °C, and 70.4−73.9 °C (Figure 9d).

Notably, the nine-via configuration exhibited greater temperature variation under misalignment than the five-via case. Although the variation was smaller with no offset (0.4 °C and 0.3 °C for the five- and nine-via cases, respectively), it increased significantly even with slight misalignment, reaching 0.9 °C and 1.0 °C, respectively at an offset of (0.1 mm, −0.1 mm). This trend deviates from the more uniform temperature distributions observed in the pitch variation results (Figure 6 and Figure 7), where configurations with more vias generally showed better thermal uniformity. This implies that the effective area occupied by the via array, rather than via density, plays a dominant role in determining misalignment tolerance.

Figure 10 shows a comprehensive comparison between the two configurations. For the five-via case, T_LED increased from 75.8 °C (no offset) to 76.3 °C, 76.6 °C, and 78.1 °C as the offset increased (Figure 10a). A similar trend was observed for the nine-via configuration, where T_LED rose from 70.9 °C to 71.8 °C, 72.4 °C, and 73.9 °C (Figure 10b). The overall T_LED value was smaller in the nine-via configuration due to the higher number of vias. However, the rate of ΔT_LED increase was more noticeable in the smaller pitch configurations. In both cases, even slight misalignments, as small as 0.1 mm, significantly degraded thermal performance. Such levels of misalignments fall within the typical tolerance range of surface mount technology processes considering factors such as slippage during placement, solder flow, or thermal expansion during reflow. In such cases, increasing the number of vias can provide a buffer against fabrication tolerances despite the accompanying complexity. It is also important that the effective working area of the via array closely matches the footprint of the LED chip to ensure efficient thermal conduction. Misaligned vias, particularly those placed outside the heat-generating area, resulted in greater degradation of temperature uniformity. This thermal nonuniformity induces asymmetric temperature distributions across the substrate, concentrating thermal stress in localized regions. In addition, thermal shock in the presence of such uneven temperature distributions can significantly elevate local mechanical stress [47]. Consequently, degradation mechanisms such as solder joint fatigue, delamination, or component detachment may be accelerated [48]. It has also been reported that vias with inner void structures due to partial filling exhibit higher sensitivity to such thermal localization [46].

4. Conclusions

We performed a comprehensive thermal analysis of high-power LED modules to evaluate heat dissipation performance as a function of thermal via design, including the number of thermal vias, pitch, and misalignment. The temperatures of the LED and substrate exhibited saturation behavior as the number of thermal vias increased. The optimal via pitch for heat dissipation performance varied depending on the number of thermal vias, emphasizing the need for integrated consideration of pitch and via density. Misalignment of the thermal via array relative to the LED center also resulted in significant increases in both temperature and thermal nonuniformity, particularly for a smaller effective working area of the via array.

We propose a cost-effective and fabrication-reliable design strategy for thermal vias, offering practical guidelines for the scalable design of high-power LED modules. In practical applications, the minimum via diameter and via-to-via spacing are often constrained by standard fabrication limits [49]. Our proposed thermal via design guidelines are fully compatible with these manufacturing constraints. Notably, they achieve effective thermal performance without requiring via configurations that approach the limits of process capabilities. Our results demonstrate that even with relaxed via configurations, substantial heat dissipation is possible due to the saturation behavior in thermal performance. Therefore, the proposed strategy provides a balanced solution between thermal efficiency and fabrication feasibility using conventional, cost-effective processes.

Experimental validation of our proposed concept would be highly desirable for its practical application. Although this study primarily relies on numerical analysis, previous studies on similar thermal via implementations have reported good agreement between simulation and experimental measurements, typically within a 10% error margin when considering manufacturing tolerances [34,35,50].

Importantly, the proposed via configuration strategy can be effectively applied to a wide range of heat dissipation modules, offering consistent thermal performance improvements across various device layouts. Our approach is applicable to a wide range of LED layouts and substrate configurations.