An Efficient Algorithm for Mapping Deep Learning Applications on the NoC Architecture
Abstract
:1. Introduction
2. Related Work
2.1. Machine Learning, Deep Learning, and Neural Networks
2.2. NetworkonChip (NoC)
2.3. Application Mapping on the NetworkonChip (NoC)
3. Multilevel Task Mapping for NN Applications
Algorithm 1: AI application mapping on meshbased NoC. 

3.1. Level 1 Mapping: Region Mapping
Algorithm 2: Neuralnetworklevel mapping on the NoC region. 

3.2. Level 2 Mapping: Neurons Mapping on the Cores
Algorithm 3: Neuron mapping on the NoC core. 

3.3. Discussion about the Proposed Technique
4. Evaluation
4.1. Analytical Model
4.2. Simulation Results
4.2.1. Visual Analysis of Application Mapping
4.2.2. Energy Consumption, Communication Latency, and Throughput Analysis
 1 indicates fourcores architecture.
 2 indicates ninecores architecture.
 3 indicates 16cores architecture.
4.3. Discussion about the Results and Prospective Work
5. Conclusions
Author Contributions
Funding
Conflicts of Interest
References
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AI  Artificial intelligence 
BB  Branch and bound 
BEMAP  BBbased exact mapping 
${B}_{ta.tb}$  Bandwidth between two routers ${t}_{a}$ and ${t}_{b}$ 
CC  Communication cost of the NoC 
DNN  Deep neural network 
DSE  Design space exploration 
DVFS  Dynamic voltage and frequency scaling 
${E}_{Link}$  Link energy consumption 
$La{t}_{avg}$  Average latency 
$L{t}_{b}$  Latency of packet b 
MET  Maximal empty triangle 
n  Number of neurons 
N  Number of processing cores 
${N}_{m}$  Manhattan distance from source to destination tile 
NN  Neural network 
NoC  Networkonchip 
${N}_{x}$  Packets received by the core x 
PSO  Particle swarm optimization 
RL  Reinforcement learning 
SNN  Spiking neural network 
SoC  Systemonchip 
SotAs  Stateoftheart 
${T}_{sim}$  Simulation time 
VLSI  Verylargescale integration 
Article  Mapping Technique  Performance Improvement  AI Application Mapping 

[6]  DVFSbased application mapping  Large power savings  ✗ 
[8]  Multiapplication mapping  18% reduction in latency and energy consumption  ✗ 
[9]  Faulttolerant mapping  9.5% communication energy reductions and 7.94% performance improvement  ✗ 
[10]  Heuristicbased algorithm  Reduction in the maximum average packet latency by 10.42%  ✗ 
[11]  Runtime mapping for hard realtime applications  13% reduction in the energy consumption  ✗ 
[12]  B*treebased simulated annealing algorithm/genetic algorithm  23.45% reduction in power consumption and 24.42% reduction in the latency  ✗ 
[34]  Branchbound (BB)based exact mapping (BEMAP) algorithm  19.93% reduction in energy consumption and 61.10% depletion in network latency  ✗ 
[35]  Comparison of most of the reported application mapping techniques for NoC  Conclusion is provided for NoC application mappingbased on algorithm runtime  ✗ 
[36]  Particle swarm optimization (PSO) algorithm and TABU search  Reduction in average latency by 63% and average energy consumption by 69%  ✓ 
[37]  Combining uneven and search mapping strategies  Up to 64% more energyefficient in comparison with SotAs  ✓ 
[38]  Multilevel genetic algorithm based technique  Reduction in power consumption and delay in comparison with traditional genetic algorithm  ✗ 
Parameter  Value 

NoC type  2D Mesh 
NoC sizes  2 × 2, 3 × 3, 4 × 4 
Embedded applications  Artificial intelligence (neural network) 
Packet length  128 bits (1 flit) 
Mapping algorithm  Multilevel and direct mapping 
Simulation time  1000 s 
Clock frequency  2000 MHz 
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Khan, Z.A.; Abbasi, U.; Kim, S.W. An Efficient Algorithm for Mapping Deep Learning Applications on the NoC Architecture. Appl. Sci. 2022, 12, 3163. https://doi.org/10.3390/app12063163
Khan ZA, Abbasi U, Kim SW. An Efficient Algorithm for Mapping Deep Learning Applications on the NoC Architecture. Applied Sciences. 2022; 12(6):3163. https://doi.org/10.3390/app12063163
Chicago/Turabian StyleKhan, Zeeshan Ali, Ubaid Abbasi, and Sung Won Kim. 2022. "An Efficient Algorithm for Mapping Deep Learning Applications on the NoC Architecture" Applied Sciences 12, no. 6: 3163. https://doi.org/10.3390/app12063163