Performance and Characterization of Additively Manufactured BST Varactor Enhanced by Photonic Thermal Processing

Abstract

The demand for reconfigurable devices for emerging RF and microwave applications has been growing in recent years, with additive manufacturing and photonic thermal treatment presenting new possibilities to supplement conventional fabrication processes to meet this demand. In this paper, we present the realization and analysis of barium–strontium–titanate-(Ba_0.5Sr_0.5TiO₃)-based ferroelectric variable capacitors (varactors), which are additively deposited on top of conventionally fabricated interdigitated capacitors and enhanced by photonic thermal processing. The ferroelectric solution with suspended BST nanoparticles is deposited on the device using an ambient spray pyrolysis method and is sintered at low temperatures using photonic thermal processing by leveraging the high surface-to-volume ratio of the BST nanoparticles. The deposited film is qualitatively characterized using SEM imaging and XRD measurements, while the varactor devices are quantitatively characterized by using high-frequency RF measurements from 300 MHz to 10 GHz under an applied DC bias voltage ranging from 0 V to 50 V. We observe a maximum tunability of 60.6% at 1 GHz under an applied electric field of 25 kV/mm (25 V/μm). These results show promise for the implementation of photonic thermal processing and additive manufacturing as a means to integrate reconfigurable ferroelectric varactors in flexible electronics or tightly packaged on-chip applications, where a limited thermal budget hinders the conventional thermal processing.

1. Introduction

Additive manufacturing (AM), also commonly referred to as 3D printing, has revolutionized the way we create complex structures and components and has become a major cornerstone in research and development in recent years. While the term 3D printing has become almost synonymous with fused deposition modelling (FDM), AM encompasses a large selection of technologies including a wide range of deposition techniques, such as micro dispensing, binder jetting, inkjet printing, aerosol jet, as well as the aforementioned FDM, just to name a few. However, it is also often seamlessly combined with other technologies and techniques, such as localized laser processing, in situ UV curing, micromilling, photonic thermal processing, etc., which are used for the fabrication of complex multidimensional structures and allow for the postprocessing of deposited materials and individual layers [1,2,3,4,5]. These technologies can not only be combined with each other to create new processes or improve upon existing ones, but can, and have been, integrated together with conventional fabrication technologies as part of hybrid co-designs, which leverage the strengths of each set of technologies to address challenges faced by conventional fabrication [2,4,5,6,7]. For example, this hybrid approach has allowed for the incorporation of integrated bypass capacitors into a wideband chip carrier to ensure a clean and stable power source to an amplifier die [6] and the use of unconventional geometries, along with selective material deposition, to address thermal management when packaging amplifiers [7].

Such techniques have already been implemented in the fabrication of other perovskite materials for optoelectronics, where AM has paved the way for the design and fabrication of fully 3D structures for the purpose of improving tailoring to meet specific needs and systems, thus addressing the limitations of the planar structures of conventional fabrication [8,9,10]. This fabrication approach has allowed for greater versatility of design, with some of the main advantages including the ability to generate 3D structures and the design-to-manufacturing flexibility offered by many of these AM techniques. Among the numerous applications of AM in electronics, for the purpose of this work, the main focus is on reconfigurable devices, circuits, and systems, all of which can be realized through various mechanisms such as mechanical microfluidic actuation or by implementing materials such as ferroelectric, ferromagnetic, and meta-materials. The exact mechanism through which each category of material can be reconfigured, or tuned, varies greatly and so does their implementation into functional electronic devices [11,12,13].

This work focuses on ferroelectric materials for reconfigurable device applications, more specifically barium–strontium–titanate (BST), which has received extensive research attention due to its interesting properties. BST, as a ferroelectric material, has a Curie temperature that can be directly modified by changing the Ba:Sr ratio in its stoichiometry. It has both a high dielectric constant and piezoelectric properties, which can be tuned using an external electric field, and displays low dielectric loss tangential losses, all of which can be further tailored by changing the stoichiometry and introducing dopants [6,7,14,15,16,17,18,19,20,21], therefore making BST an attractive material for reconfigurable high-frequency applications. Prior research on BST has focused on the characterization and implementation of devices in various fields including optics, communications, and RF and microwave [6,7,15,16,17,18,19,20,21]. Besides its use for RF electronics, BST shows potential for other applications such as magnetic sensors. The most common way to achieve that is by iron (Fe) doping the BST to exhibit the desired multiferroic and magnetic properties. Both [22,23] examined the effect of Fe doping level on the average crystal size, the expansion of the BST unit cell, the ferroelectric, magnetic, and optical properties, and the dielectric constant and losses up to 1 MHz. Enriching BST’s capabilities to allow the sensing of a magnetic field can lead to the employment of BST in a magnetic field sensor for various applications. In that sense, researchers have also been exploring the sensor applications of magnetic ceramics by using materials such as strontium hexaferrite. For instance, Safronov et al. [24] reproduced biological tissues using ferrogels containing micron-sized magnetic particles and developed a prototype magnetic field magnetoimpedance sensor. Another promising application to magnetic field sensing, demonstrated by Yang et al. [25], for detecting cardiac biomarker myoglobin (Mb) is conducted by using an integrated giant-magnetoimpedance (GMI)-based immunosensor.

Prior work has shown that, among various parameters, the crystalline structure of the deposited BST is a primary contributor, determining the effective dielectric permittivity and tunability. To ensure that the BST films are not in an amorphous state and realize the desired crystalline microstructure, BST films are deposited either at very high temperatures or at lower temperatures and then annealed. The most common annealing method reported in the literature involves the use of rapid thermal annealing (RTA) and high temperature furnace annealing at typical temperatures of 700–850 °C for up to multiple hours. These processing methods, while convenient, pose many limitations for flexible electronics, on-chip, and high-density packaged designs due to the thermal budget. Substantial research has been conducted to address these limitations, including the use of UV-wavelength radiation via excimer laser to improve the quality of low-temperature-deposited BST films and promote crystal grain growth [26,27,28,29]; however, laser annealing has a limited throughput due to spot size limitations, and these studies have required substrate temperatures in the range of 200–300 °C during either BST film deposition or annealing, making them unsuitable for integration with the majority of thermoplastics commonly used in AM packaging and flexible electronics. In the case of AM or BST, some prior works have used inkjet printing on alumina substrates to allow for sintering at temperatures upward of 1150 °C to circumvent thermal budget limitations [30,31]. Ranasingha et al. [32] demonstrate the good performance of sinterless-aerosol-jet-deposited BST nanoparticles, but the performance still falls behind that of sintered BST [32]. This work, therefore, aims to fill a gap in the literature with respect to the low-temperature sintering of BST films with the aid of AM techniques. To realize additively manufactured BST films at low temperatures with a performance comparable to that of fully furnace-sintered films, we leverage the increased radiation absorption of nanoparticles that is due to their high surface-area-to-volume ratio combined with photonic sintering to sinter the surface BST coating without causing a significant temperature increase in both the substrate and the metallization layer underneath. This allows for greater flexibility when integrating ceramic films, which require thermal processing for the best performance, into flexible electronics, complex 3D structures, and high-density electronic packaging designs without a significant thermal budget limitation.

The two main design topologies used for the integration of ferroelectric materials in capacitive devices found in the literature are parallel plate implementations and interdigitated designs [16,33,34]. Parallel plate implementations consist of a metal–insulator–metal (MIM) topology where the ferroelectric material is sandwiched between two electrodes, whereas the interdigitated capacitor (IDC) design consists of a planar metallic structure with multiple overlapping fingers. The MIM topology has the advantage of allowing a large and more uniform electric field concentrated in the active ferroelectric layer; however, it comes with a more complex multilayer fabrication process, a greater dependance on the electrode quality, and is more prone to resonant resistive effects [16,33,35,36]. The IDC topology, on the other hand, consists of a single-layer planar structure typically fabricated directly on top of or underneath the ferroelectric layer. However, due to the resolution limits of conventional photolithography, IDC devices generate a lower electric field when using an equivalent bias voltage compared to a MIM device. This limitation can be addressed by using the high resolution of nanolithography to reduce the finger gap, as shown in [16]; however, this form of lithography adds greater complexity to the fabrication and requires more tools, which are not as readily available as those used for conventional photolithography. For these reasons, we decided to fabricate an IDC design to test the RF performance of our BST films.

In this work, we report the initial results of our study on BST capacitors fabricated with a mix of conventional lithography for the electrode layer and AM techniques, using ambient air spray pyrolysis deposition of suspended BST nanoparticles, which are further enhanced by localized sintering and crystallization via photonic thermal processing. The device performance is evaluated using S-parameter measurements from 300 MHz to 10 GHz under a bias voltage range from 0 V to 50 V, from which the capacitance, tunability, and permittivity are extracted using equations. The deposited films are evaluated qualitatively using SEM imaging and XRD measurements. We demonstrate effective photonic sintering and initial crystallization of the deposited film, which achieves a performance comparable to that of BST devices thermally processed using conventional techniques without the need to expose the electrode and substrate layers to high temperatures for extended periods of time.

2. Materials and Methods

2.1. Capacitor Design and Fabrication

The initial designs of the fabricated devices were taken from [16] and were modified to better suit our fabrication process. The full layout design consisted of devices with four, six, eight, 10, and 14 interdigited fingers, each having a version with 2 μm, 5 μm, 10 μm, and 20 μm finger gaps and each exhibiting both one-port and two-port configurations. In this work, we present the measured results for the eight-finger one-port configuration, as depicted in Figure 1a,b, which has a finger length of L = 400 μm, a finger width of W = 50 μm, and a gap of g = 2 μm. This particular configuration was preferred for a number of reasons. First of all, the one-port configuration is not only easier to measure, but also allows for accurate extraction of the performance parameters. Second, the 2 μm gap is the smallest we could consistently fabricate with conventional lithography methods and, thus, provides the highest electric field under a certain level of applied bias voltage potential. Third, the eight-finger configuration is right in the middle of the range of designs, thus providing a measurement of the median capacitance and operating frequency range. As it can be seen in Figure 1c,d, the complete device consists of the IDC as well as a segment of coplanar waveguide (CPW) line, which serves as a landing pad for our ground–signal–ground (GSG) probes employed for the RF measurement. The CPW line was designed to be longer than its typical design as a compromise to allow for some degree of misalignment during the masking process, which is used during the BST deposition. The complete dimensions for the measured design can be found in

Table 1. A set of key design dimensions for the measured IDC device.

Dimension	Size (μm)
Finger length	400
Finger width	50
Finger gap	2
Interconnect width	50
Feedline width	65
CPW gap	25
Feedline length	500
CPW ground width at IDC region	150

.

The electrodes were fabricated on top of a Pyrex substrate with a thickness of 500 μm by means of conventional cleanroom microfabrication techniques. A lift-off process with positive photoresist was used to pattern the metallization layer, along with RF sputtering, to deposit 300 nm gold electrodes on top of a 30 nm chrome adhesion layer.

2.2. BST Deposition and Thermal Processing

The BST solution was purchased from TPL inc. and it consisted of 50 nm BST particles suspended in an ethylene glycol solution. The particles had a Ba_0.5Sr_0.5TiO₃ stoichiometry and accounted for 49% of the weight of the solution. The solution was deposited using an ambient spray pyrolysis setup, as illustrated in Figure 2. As seen in the diagram, the die with the deposited electrodes was placed on top of a hot plate, which was mounted on a single axis motorized stage. The die was masked using the Kapton tape to cover the feedlines for probing, leaving only the main IDC finger area exposed for deposition, as seen in Figure 1b,d. Before deposition, the solution was placed in a centrifugal planetary mixer (ARE-310 Thinky Mixer) to break down any particle agglomerations and ensure homogeneity. It was then loaded into an Iwata HP-TH2 airbrush with a 0.06 mm nozzle connected to a commercial air compressor set to 35 psi and deposited on the IDC device die. The hot plate was maintained at a temperature of ~100 °C during deposition to begin the curing process and prevent overaccumulation of the liquid solution on the surface. To enhance the repeatability of the deposition process, the spray gun was kept at an approximate angle of 30° and at a height of 10 cm from the hot plate surface, the controller for the stage was set to a speed of 20 mm/s with an acceleration and deceleration of 80 mm/s², and the die passed below the spray region a total of ten times, with five passes in each direction to improve the uniformity of deposition. This process consistently yielded films with a thickness of approximately 18 μm and an average roughness of 2.5 µm. After deposition, the die was left on the hot plate for 2 min to promote the evaporation of most of the solvent before being put into a vacuum oven at 100 °C for 2 h to ensure that any trapped moisture and residual solvent evaporated. Initial attempts to fully cure the films with only the hot plate showed an increased likelihood of surface cracking and delamination of the films due to the rapid and uneven heating, while the sample was under a partially liquid state and occasionally still retained trapped moisture.

After the die was fully cured and dehydrated, the BST nanoparticles that made up the film were thermally processed using a PulseForge photonic thermal processing unit integrated into an nScrypt 3Dn-450-HP additive manufacturing platform. The PulseForge unit uses a flash lamp with a wavelength ranging from 200 nm to 1500 nm to produce high-energy broadband microsecond pulses, covering the UV to near IR range, to irradiate the surface layer and induce rapid transient heating of the top surface. The high surface-to-volume ratio of the BST nanoparticles increased the heat generated by these pulses, leading to high temperatures of the film layer and to the sintering of the nanoparticles, while the short length of the pulses ensured that the rise in temperature of the subsequent metal and substrate layers was mitigated. For the pulses, we used a 10 ms envelope made up of 10 pulses, with 50% duty cycle and a driving voltage of 300 V which generated a total energy of 4.44 J/cm². Because annealing is not a quick process, we exposed the films to a total of 1000 repetitions of the envelope applied over five 200 pulse sessions to allow for the substrate to fully dissipate the heat and for the lamp to cool down and prevent overheating.

The high frequency RF performance of the fabricated devices was measured using a Keysight PNA N5227A (Keysight, Santa Rosa, CA, USA) vector network analyzer (VNA) with built-in bias tees rated for 250VDC and 2A. The GGB Model 40A GSG (GGB Industries Inc., Naples, FL, USA) probes with a 250 μm pitch size rated for 50 V were used and the biasing voltage was provided by a Rohde & Schwarz NGA100 (Rohde & Schwarz USA Inc., Columbia, IN, USA) power supply with a max DC output of 100 V and 2A per channel. A discreet series resistor of 1 MΩ was used between the power supply and the bias tee input as a precaution, serving as a current limiter in the event of a short circuit. Calibration was performed at 0 V bias voltage using a CS-5 calibration substrate and the one-port S-parameter frequency response of the device was measured over the range from 300 MHz to 10 GHz at various bias voltages from 0 V to 50 V. The voltage readout of the NGA100 has an accuracy of ± (<0.02% + 10 mV) and the accuracy of the CS-5 calibration substrate standards is ±0.25%.

The thickness and roughness of the deposited BST layers were measured using a C-BXT Bruker XT-A profiler. The deposited BST films were qualitatively assessed using XRD measurements and SEM imaging. SEM images were taken using a FEI Quanta 200 3D Dual Beam system (FEI Company, Hillsboro, OR, USA) under low vacuum conditions to mitigate electronic charge buildup. Due to the minimum film area required for the XRD measurements, a different sample had to be prepared. A BST film processed under the same processing conditions was deposited on a quarter of a 2-inch silicon wafer and measured using a Bruker D2 Phaser XRD (Bruker, Billerica, MA, USA).

3. Results

3.1. High Frequency S-Parameter Measurments

As we increased the bias voltage applied to the capacitor, the dielectric constant of the BST decreased, in turn reducing the capacitance of the IDC. This decrease in capacitance led to an increase in the frequency at which series resonance occurs, as we can observe from Equation (1). This change in the self-resonance frequency was due to the fact that the contribution for the series inductance in the capacitor equivalent circuit originated from the metallization layer; thus, the inductance should remain largely unchanged in response to the increase in bias voltage [37]. We can observe from Figure 3a that the magnitude of the reflection coefficient increased along with the applied bias voltage, a phenomenon which was due to a decrease in the roll-off of the reactance of the device from the smaller capacitance. Also, as shown in Figure 3b, the device exhibited a series resonance at 9.2 GHz which was observed at 0 V. As seen in the literature [14,15,16,17,18,19,20,21], the dielectric constant of BST under an applied bias voltage should decrease consequently, decreasing the capacitance. From Equation (1), we can observe that, if the inductance remains constant, then, as the bias voltage increases, the capacitance decreases, thus shifting the self-resonance to a higher frequency. As shown in Figure 3a,b, the self-resonance, as given by Equation (1), shifted to a higher frequency when a bias voltage was applied, and it no longer appeared within our measured frequency range.

$$f_{\mathit{res}}={\displaystyle \frac{1}{2\pi \sqrt{\mathit{LC}}}}$$

(1)

3.2. BST Parameter Extraction

From the one-port S₁₁ measurement results shown in Figure 3a,b, we can extract the capacitance C and the series resistance R by using Equations (2)–(5):

$$Z_{11}=Z_0{\displaystyle \frac{1 + S_{11}}{1-S_{11}}}$$

(2)

$$Z_{11}=R+j{(X_L+X}_C)$$

(3)

$$X_C=-{\displaystyle \frac{1}{2\pi \mathit{fC}}}$$

(4)

$$C=-{\displaystyle \frac{1}{2\pi f{X}_C}}$$

(5)

We first converted the measured S₁₁ to Z₁₁ by using Equation (2). Then, from Equation (3), we observe that the real part and imaginary part of Z₁₁ corresponds to the series resistance and the total reactance of the device, respectively. In the frequency range where $X_C\gg X_L$, the total reactance in Equation (3) can be approximated by Equation (4). Equation (5) can then be applied to calculate the capacitance from the imaginary part of Z₁₁.

Figure 4a,b show the real and imaginary parts of the calculated Z₁₁ parameters, respectively. Based on Equation (4), as the bias voltage increased, the capacitance decreased, leading to a larger negative reactance, which can be observed in Figure 4b. As also shown in Figure 4a, when the bias voltage increased, the series impedance decreased to the lower frequency region. This can be explained most likely by a greater contribution of the dielectric losses to the equivalent series resistance (ESR) of the BST varactor device at a lower frequency. At higher frequencies, the resistance contribution from the metallization layer dominated. One can also observe from Figure 4a,b that the effect of the noisy response in Figure 3a at low frequencies for the 40 V and 50 V measurements can be seen prominently in the extracted impedance, but the reactance was only minimally affected.

The calculated capacitance shown in Figure 4c highlights the reduction in capacitance as a function of the bias voltage and it is observed that there was more than a 50% decrease between 0 V and 50 V. This decrease in capacitance was due to the decrease in the dielectric constant of BST as a result of applying an external electric field. This occurred because the applied electric field shifted the titanium ion at the center of the BST crystal structure, reducing its ability to store charge, lowering the effective dielectric constant [16]. The electric field tuning behavior observed is similar to what has been previously reported in the literature for BST exhibiting a similar stoichiometry [20,21,33,34,35]. It is observed in Figure 4d that the calculated capacitances were constant within the low-frequency region.

Based on the calculated capacitance under a certain level of applied bias voltage, Equation (6) can be used to determine the tunability as a function of the bias voltage (x):

$$T\left(x\right)={\displaystyle \frac{C_{Vdc=0} -C_{Vdc=x}}{C_{Vdc=0}}}100$$

(6)

Figure 5a,b present the tunability as a function of bias voltage plotted over different frequency ranges. As it is shown, at each bias voltage, the tunability remained quasi-constant within the low-frequency range, after which the tunability level in terms of percentages started to rapidly change due to the effects of the resonance. At 1 GHz, with a bias voltage of 50 V, which is equivalent to an electric field of 25 kV/mm, a maximum tunability of about 60% was observed, and, even at a relatively low electric field of 7.5 kV/mm, a tunability of about 18% was demonstrated.

The calculated capacitance and Equations (7) and (8) found in [37] can be used to derive the dielectric constant of the IDC device:

$$C=\left({\epsilon }_r+1\right)L\left[\left(N - 3\right)A_1+A_2\right]$$

(7)

$${\epsilon }_r={\displaystyle \frac{C}{L \left[\right(N - 3)A_1+A_2]}}-1$$

(8)

where L is the interdigit finger length in μm, N is the number of fingers, $A_1$ is the capacitance per unit length of the interior fingers, and $A_2$ is the capacitance per unit length of the two exterior fingers. $A_1$ and $A_2$ are functions of the substrate thickness to finger width ratio; however, for our case with no ground plane, their values became 4.409 × 10⁻⁶ pF/um for $A_1$ and 9.92 × 10⁻⁶ pF/um for $A_2$. Equation (7) shows that the capacitance is linearly dependent on the dielectric constant for an IDC device. Therefore, we can expect the plot of the derived dielectric constant to show the same trend as that exhibited by the capacitance, as it can be seen in Figure 6a,b. At 1 GHz, a maximum dielectric constant of 57 with no bias voltage and a minimum of 22 under a 50 V bias were observed.

Lastly, Equation (9) was used to calculate the quality factor Q of the measured IDC, and its inverse can be used to determine the loss tangent.

$$Q={\displaystyle \frac{X_C}{R}}$$

(9)

In Figure 7, a trend whereby the Q factor increased as the bias voltage increased can be observed. This behavior was expected, as, from Equation (9), it can be seen that X_C becomes larger as the capacitance decreases due to the applied electric field.

The loss tangent, as seen in Figure 8a,b, was found to decrease as the applied bias voltage increased, which is consistent with the behavior presented by Muzzupapa et al. [33]. The loss tangent remained below 0.15 throughout the frequency range up to 3 GHz under a 0 V bias and below 0.05 under a 50 V bias, as observed in Figure 8b. We expected this to be the case because of the inverse relationship between the loss tangent (1/Q) and Q. A summary of all key characterization parameters of the BST IDC device at 1 GHz can be found in

Table 2. Key characterization parameters extracted from BST IDC measurements at 1 GHz.

Voltage (V)	E Field (kV/mm)	Capacitance (pF)	Tunability (%)	Dielectric Constant	Q Factor	Loss Tangent (1/Q)	Resonance Frequency (GHz)
0	0	0.932	0.0	57.3	10.9	0.092	9.2
20	10	0.711	23.7	43.5	17.9	0.056	10.5
40	20	0.474	49.2	28.6	31.3	0.032	13.1
50	25	0.367	60.6	22.0	41.7	0.024	14.9

, and a comparison with other works can be found in

Table 3. Comparison of the performances of BST capacitive devices.

Ref.	Deposition Method	Thermal Processing	Tunability (%)	E Field (kV/mm)	C0V (pF)
[18]	PLD *	Furnace	15	4.38	1.00
[32]	Aerosol jet	Sinterless	15	10.00	Not reported
[33]	Sol–gel	RTA	40	16.70	0.15
This work	Spray pyrolysis	Photonic sintering	60	25.00	0.93

* Plasma laser deposition.

.

3.3. SEM Imaging and XRD Measurements

The SEM images shown in Figure 9a–d were taken from the BST film on the measured IDC device. Figure 9a shows the entire IDC device, depicting the BST film completely covering the IDC finger region as well as the slight misalignment offset during deposition as a result of the Kapton masking tape placement. As shown in Figure 9b–d, the as-deposited BST nanoparticles agglomerated into clusters, which were then sintered via photonic thermal processing. While the individual nanoparticles were originally 50 nm, the average size of the sintered crystals was observed to be roughly 500 nm.

The results of the two-theta scan of the thermally processed film, as seen in Figure 10a, show that all the Ba_0.5Sr_0.5TiO₃ crystal orientations were present with a clear preference for the (110) orientation. All peaks corresponding to the BST and to the Si wafer were analyzed with X’pert HighScore and labeled accordingly, with the small unlabeled peaks belonging to the Kβ radiation. The comparison of the (110) peak between the as-deposited film and the film after the thermal processing in Figure 10b shows that the peak slightly shifted to a lower angle and its intensity increased after thermal processing, suggesting an induced change in the lattice parameter. The XRD peak of the as-deposited film slightly shifted to the right from the BST (110) peak, a phenomenon which suggests residual compressive stress [38]. This residual stress was released as the peak for the thermally annealed sample returned to the anticipated peak position after the photonic thermal processing. From this, it can be inferred that stress relaxation occurred.

4. Discussion

In this work, we fabricate and characterize reconfigurable BST IDC devices using a mix of conventional microfabrication and AM techniques. We sintered the deposited films at low temperatures by using photonic thermal processing, thus allowing for the direct heating of the top surface while minimizing the effect on the metallization layer and substrate. No delamination was observed after processing and film metrology verification using XRD and SEM, demonstrating that thermal processing caused sintering of the deposited nanoparticles and reduced the residual compressive stress in as-deposited samples. Device characterization using S-parameter measurements showed a good performance, with a maximum measured tunability of 60.6% at an applied electric field of 25 kV/mm and an acceptable loss tangent on par with those reported in prior works. The results presented here show promising initial results for the hybrid implementation of photonic thermal processing and AM with conventional fabrication to produce high-frequency reconfigurable ferroelectric varactors, which can potentially be integrated into tightly packaged and on-chip configurations where the thermal budget may limit the compatibility of in-situ thermal processing.

Future work includes the optimization of BST film deposition and thermal processing, and implementation and integration of BST reconfigurable devices into functional RF circuit modules. The current deposition and photonic thermal sintering processes are still being improved and refined. Further optimization of the photonic pulses will be investigated to balance film quality improvement and heat generated on the substrate to increase compatibility with low thermal budget substrates such as thermoplastics used in AM. For the deposition, a compressed nitrogen with a regulator will be employed in place of the commercial air compressor currently used, as the latter cannot maintain a constant 35 psi pressure throughout the entire spray process. This should help improve the uniformity of each deposited layer, thus allowing for fewer layers to be deposited to achieve complete coverage and reduce layer roughness.