# Impact of Bias Temperature Instabilities on the Performance of Logic Inverter Circuits Using Different SiC Transistor Technologies

^{1}

^{2}

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## Abstract

**:**

## 1. Introduction

## 2. Charge Trapping and Model Calibration

_{2}[9,10,11,12], Si/HK [13,14,15,16] and SiC/SiO

_{2}material systems [17]. BTI typically evolves as a drift of the threshold voltage with operation time and is characterized at higher gate voltages to accelerate $\u2206{V}_{\mathrm{th}}$ degradation. The origin of the observed $\u2206{V}_{\mathrm{th}}$ lies in charge trapping at interface traps and oxide defects [18,19].

**left**), and (ii) AC-MSM measurements to characterize the operation of the transistors in switching applications, see Figure 3 (

**right**). In the last case, a short AC stress during a time around 100 ms is applied repeatedly. At the last AC cycle of the signal, the stress is interrupted (${t}_{\mathrm{AC},\mathrm{interrupt}}$). Then a $\u2206{V}_{\mathrm{th}}$ recovery trace is extracted for a time equal to 10 ms considering a fixed ${I}_{\mathrm{D}}$ = 1 mA through the channel of the device.

## 3. Compact Modeling of BTI for Circuit Simulations

## 4. Results and Discussion

**(left)**. With this circuit, we can efficiently verify our approach and implementation to determine the BTI impact in the propagation delay ${t}_{\mathrm{D}}$ considering only one transistor. The values are extracted as the time difference when ${V}_{\mathrm{in}}$ and ${V}_{\mathrm{out}}$ are equal to ${V}_{\mathrm{DD}}$/2, as we show in Figure 9

**(right)**. Each value of the delay time distribution ${t}_{\mathrm{D}}$ represents the aging of the inverter circuit for each $\u2206{V}_{\mathrm{th}}$ or, equivalently, for a certain degradation of the device with time.

## 5. Conclusions

## Author Contributions

## Funding

## Acknowledgments

## Conflicts of Interest

## References

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**Figure 1.**Schematic of the potential energy surfaces of our physical defect model and the corresponding model parameters required to calculate the charge trapping at defects. The model is based on non-radiative multi-phonon (NMP) theory to calculate the transition times at single defects corresponding to charge transfer reactions.

**Figure 2.**The prediction of the two-state model is shown versus power-law like functions for the three technologies evaluated in this work: T1 (

**top-left**), T2 (

**top-right**) and T3 (

**bottom**). As can be seen, our simulations nicely replicate the experimental data, while the power-law (black) significantly deviates from the experimental data. The measurement delay for recording ${V}_{\mathrm{G}}$ after stress for this setup is ${t}_{\mathrm{read}}$ = 1 μs.

**Figure 3.**Schematic of the MSM measurement sequences of the input signals that are applied to the gate terminal of the transistors. The $\u2206{V}_{\mathrm{th}}$ values are extracted considering, (

**left**) a long-term DC PBTI degradation where a constant stress bias is applied before the recovery phase is recorded, and (

**right**) a short-term AC $\u2206{V}_{\mathrm{th}}$ is measured at different time points (${t}_{\mathrm{AC},\mathrm{interrupt}}$) at which the short AC stress is interrupted [22].

**Figure 4.**Comparison between simulation and experimentally $\u2206{V}_{\mathrm{th}}$ extracted values for T1. The simulations nicely reproduce the measured data set $\u2206{V}_{\mathrm{th}}$.

**Figure 5.**Similar measurement sequence as shown in Figure 4 is presented here for T2. Again our model agrees well with the experimental data.

**Figure 6.**Also the data recorded employing T3 can be reconstructed at high accuracy by our physical computer models.

**Figure 7.**The BTI impact on the transistors is represented by adding a voltage source with a value equal to $\u2206{V}_{\mathrm{th}}$ to the gate of the devices implemented in the Spice simulator. $\u2206{V}_{\mathrm{th}}$ values are extracted from the accurate physical defect trapping model.

**Figure 8.**Simulation process flow using open-source simulator ngspice, to analyze the BTI impact on the inverter circuits performance. The spice simulator uses the data from the reliability simulator Comphy to modify the initial net-list of the circuit. It launches simulations to extract the aged circuit parameters for long operation time. Each simulation (step 3) corresponds to an inevitable degradation of the transistors for a specific time (step 2).

**Figure 9.**Schematic of the resistivity load inverter used as simple test circuit with $R=0.5\mathrm{k}\mathsf{\Omega}$, ${V}_{\mathrm{DD}}=20\mathrm{V}$ (

**left**) and propagation delay time ${t}_{\mathrm{D}}$ extraction at T = 298 K (

**right**). The latter is defined as the time difference when the output ${V}_{\mathrm{out}}$ and input voltage ${V}_{\mathrm{in}}$ equals ${V}_{\mathrm{DD}}$/2.

**Figure 10.**Threshold voltage drift ($\u2206{V}_{\mathrm{th}}$) behavior extracted employing Comphy for the different SiC power MOSFETs used in this work, i.e., T1, T2 and T3 at room temperature (T = 298 K), for an AC input signal with duty cycle = $0.5$, f = 50 kHz and a stress time equal to ${t}_{\mathrm{str}}$ = 100 ms. A comparison of the extracted values when the recovery phase is considered and omitted is shown (

**left**). A more detailed representation of the short-term AC stress case is depicted (

**right**).

**Figure 11.**The impact of BTI on the propagation delay time for the resistivity load inverter circuit based on T1 (

**left**), T2 (

**center**), and T3 devices (

**right**) is shown. For the three technologies, after ten years of the operating time, ${t}_{\mathrm{D}}$ is overestimated around by 2–4 ns if the recovery phase in the AC input signal is omitted. The results show a BTI impact less significant on T3 than in the other ones.

**Figure 12.**Schematic representation of the pseudo-D CMOS inverter circuit using commercially available SiC power MOSFETs. We analyze the BTI impact on the circuit performance considering the degradation of the ${V}_{\mathrm{th}}$ of the transistors.

**Figure 13.**Extracted signal propagation delay for the pseudo-CMOS inverter circuit considering the impact of BTI for ten years of operating time. A comparison of the results when simple power-law-like functions and physical models are used is shown (

**left**). While N1 and N3 have no to impact on ${t}_{\mathrm{D}}$, the propagation delay is affected by N2 and N4 in a similar way (

**right**).

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**MDPI and ACS Style**

Hernandez, Y.; Stampfer, B.; Grasser, T.; Waltl, M.
Impact of Bias Temperature Instabilities on the Performance of Logic Inverter Circuits Using Different SiC Transistor Technologies. *Crystals* **2021**, *11*, 1150.
https://doi.org/10.3390/cryst11091150

**AMA Style**

Hernandez Y, Stampfer B, Grasser T, Waltl M.
Impact of Bias Temperature Instabilities on the Performance of Logic Inverter Circuits Using Different SiC Transistor Technologies. *Crystals*. 2021; 11(9):1150.
https://doi.org/10.3390/cryst11091150

**Chicago/Turabian Style**

Hernandez, Yoanlys, Bernhard Stampfer, Tibor Grasser, and Michael Waltl.
2021. "Impact of Bias Temperature Instabilities on the Performance of Logic Inverter Circuits Using Different SiC Transistor Technologies" *Crystals* 11, no. 9: 1150.
https://doi.org/10.3390/cryst11091150