# The Impact of Interfacial Charge Trapping on the Reproducibility of Measurements of Silicon Carbide MOSFET Device Parameters

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## Abstract

**:**

## 1. Introduction

## 2. Materials and Methods

## 3. Results

#### 3.1. Threshold Voltage Dynamics after Short Gate Pulses

#### 3.2. Drain-Source Current Voltage Characteristics and On-State Resistance

#### 3.3. Device Preconditioning

## 4. Discussion

## 5. Conclusions

## Author Contributions

## Funding

## Acknowledgments

## Conflicts of Interest

## Abbreviations

SiC | silicon carbide |

Si | silicon |

MOSFET | metal-oxide-semiconductor field-effect transistor |

BTI | bias temperature instability |

## Appendix A. Sweeped IV-Curves at High Drain-Source Voltage

**Figure A1.**Fast gate voltage sweeps from different initial gate voltages up to $15\mathrm{V}$ within $5\mathsf{\mu}\mathrm{s}$ at a drain-source voltage of $800\mathrm{V}$ at $25{}^{\circ}\mathrm{C}$ and the corresponding smoothed data lines based on robust local regression smoothing (RLRS). While the IV-curves of the initial sweep voltages $0\mathrm{V}$ and $-3\mathrm{V}$ coincide, the IV-curves corresponding to voltages of $-5\mathrm{V}$ and $-7\mathrm{V}$ are shifted towards lower gate voltages indicating a transient threshold voltage shift.

## Appendix B. Base Voltage Dependence of the Drain-Source Current

**Figure A2.**The normalized change of the drain-source current ${I}_{\mathrm{DS}}$ for different delay times ${t}_{\mathrm{D}}$ of (

**a**) device A, (

**b**) device B, (

**c**) device C, and (

**d**) device D. The quantities $\Delta {I}_{\mathrm{DS}}\left({t}_{\mathrm{D}}\right)$ and $\Delta {I}_{\mathrm{DS}}\left({V}_{\mathrm{base}}\right)$ describe the maximum induced change in the drain-source current, whereby the former describes the change due to increasing the delay time of $7\mathsf{\mu}\mathrm{s}$ and the latter expresses the change due to lowering the base voltage relatively to $-0.25\mathrm{V}$.

## Appendix C. Correlation between Change in Drain-Source Current and the Threshold Voltage Shift

**Figure A3.**Correlation between the measured change in drain-source current normalized to the first readout and the threshold voltage shift during a $15\mathrm{V}$ pulse with a base voltage of $-12\mathrm{V}$. The red lines indicate linear fits. The shown quantity $\rho $ is the Pearson correlation coefficient indicating strong linear correlation for all devices. The subfigures (

**a**)–(

**d**) correspond to the respective devices A–D. For the condition ${V}_{\mathrm{DS}}\ll {V}_{\mathrm{GS}}-{V}_{\mathrm{th}}$, the drain-source current follows ${I}_{\mathrm{DS}}\propto {V}_{\mathrm{GS}}-{V}_{\mathrm{th}}$, implying a linear relationship between the drain-source current and the threshold voltage shift. As the data satisfies both the condition and the linear relationship, it can be concluded that the observed change of the drain-source current indeed originates from the transient threshold voltage shift.

## References

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**Figure 1.**(

**a**) The shift of the threshold voltage during a measurement over time of all devices A–D. Note that the threshold voltage is continuously applied to the gate (constant ${I}_{\mathrm{DS}}=1\mathrm{m}\mathrm{A}$) triggering electron trapping. (

**b**) Gate signal of a $70\mathsf{\mu}\mathrm{s}$ pulse from ${V}_{\mathrm{base}}=-12\mathrm{V}$ to ${V}_{\mathrm{high}}=6\mathrm{V}$ and a signal proportional to the corresponding drain-source current. Arrows indicate the measurement delay time ${t}_{\mathrm{D}}$ and the integration time ${t}_{\mathrm{I}}$ exemplarily for one out of several readouts. The current signal decreases monotonously during the pulse. The inset shows the same for a silicon MOSFET for comparison, where this effect is negligible.

**Figure 2.**The recovery traces of the threshold voltage shift, respectively after a positive $18\mathrm{V}$ ($\Delta {V}_{\mathrm{th}}>0$) or a negative $-12\mathrm{V}$ ($\Delta {V}_{\mathrm{th}}<0$) gate pulse. The pulse length ${t}_{\mathrm{pulse}}$ was varied between $100\mathrm{n}\mathrm{s}$ and $100\mathrm{m}\mathrm{s}$. The subfigures (

**a**–

**d**) correspond to the respective devices A–D. The inset in (

**a**) illustrates the measurement scheme consisting of an exemplary negative pulse followed by a continuous measurement of the threshold voltage.

**Figure 3.**The pulse length dependence of the threshold voltage shift at the shortest measured recovery time of $1.8\mathsf{\mu}\mathrm{s}$ of the tested devices A–D for the two pulse voltages of (

**a**) $-12\mathrm{V}$ and (

**b**) $18\mathrm{V}$. The full data set is shown in Figure 2.

**Figure 4.**The pulse voltage dependence of the threshold voltage shift at the shortest measured recovery time of $1.8\mathsf{\mu}\mathrm{s}$ of the tested devices A–D for the two pulse lengths (

**a**) $1\mathsf{\mu}\mathrm{s}$ and (

**b**) $100\mathrm{m}\mathrm{s}$. The full data set is shown in Figure 2.

**Figure 5.**The recovery time necessary to reach a threshold voltage shift lower than a certain limit in dependence on the pulse voltage for a pulse length of (

**a**) $1\mathsf{\mu}\mathrm{s}$, a limit of $50\mathrm{m}\mathrm{V}$ and for a pulse length of (

**b**) $100\mathrm{m}\mathrm{s}$ and a limit of $200\mathrm{m}\mathrm{V}$. The full data set is shown in Figure 2.

**Figure 6.**The drain-source current ${I}_{\mathrm{DS}}$, transconductance ${g}_{\mathrm{m}}$ and on-state resistance ${R}_{\mathrm{DS},\mathrm{on}}$ for a measurement delay of $7\mathsf{\mu}\mathrm{s}$ and two different base voltages ${V}_{\mathrm{base}}$ with an off-state time of $1\mathrm{m}\mathrm{s}$. The subfigures (

**a**–

**d**) correspond to the respective devices A–D. The drain-source voltage ${V}_{\mathrm{DS}}$ was set to $1\mathrm{V}$, except for device B (${V}_{\mathrm{DS}}=0.5\mathrm{V}$). A lower base voltage yields a higher drain-source current.

**Figure 7.**The drain-source current ${I}_{\mathrm{DS}}$, transconductance ${g}_{\mathrm{m}}$, and on-state resistance ${R}_{\mathrm{DS},\mathrm{on}}$ for a base voltage of of $-14\mathrm{V}$ and two different delay times ${t}_{\mathrm{D}}$ with an off-state time of $1\mathrm{m}\mathrm{s}$. The subfigures (

**a**–

**d**) correspond to the respective devices A–D. The drain-source voltage ${V}_{\mathrm{DS}}$ was set to $1\mathrm{V}$, except for device B (${V}_{\mathrm{DS}}=0.5\mathrm{V}$). A longer delay time yields a lower drain-source current.

**Figure 8.**The recovery traces of the threshold voltage shift without preconditioning ($0\mathrm{s}$) and with preconditioning pulses of lengths between $1\mathsf{\mu}\mathrm{s}$ and $10\mathrm{s}$ measured with device A. The subfigures (

**a**–

**d**) correspond to different preconditioning voltages ${V}_{\mathrm{prec}}$ between $-3\mathrm{V}$ and $-12\mathrm{V}$. The inset in (

**a**) illustrates the measurement scheme consisting of the stress pulse ($20\mathrm{V}$ for $1\mathrm{s}$) followed by the preconditiong pulse. Except for the case of the $-3\mathrm{V}$ preconditioning with pulse lengths between $1\mathsf{\mu}\mathrm{s}$ and $100\mathsf{\mu}\mathrm{s}$, all preconditioning pulses are strong enough to change the sign of the threshold voltage shift.

**Figure 9.**Required recovery time after preconditioning to return to a threshold voltage shift below $100\mathrm{m}\mathrm{V}$ as a function of the preconditioning time. The raw measurement data is shown in Figure 8.

**Table 1.**Overview of selected datasheet values and properties of the four different devices. The shown quantities are the maximum drain-source voltage ${V}_{\left(\mathrm{BR}\right)\mathrm{DSS}}$, the threshold voltage ${V}_{\mathrm{th}}$, the minimum and maximum gate-source voltage ratings ${V}_{\mathrm{GS},\mathrm{min}}$ and ${V}_{\mathrm{GS},\mathrm{max}}$, the input capacitance ${C}_{\mathrm{iss}}$, the design type, and a figure of merit.

Label | ${\mathit{V}}_{\left(\mathbf{BR}\right)\mathbf{DSS}}$ [V] | ${\mathit{V}}_{\mathbf{th}}$ [V] | ${\mathit{V}}_{\mathbf{GS},\mathbf{min}}$ [V] | ${\mathit{V}}_{\mathbf{GS},\mathbf{max}}$ [V] | ${\mathit{C}}_{\mathbf{iss}}$ [pF] | Design | ${\left({\mathit{C}}_{\mathbf{iss}}{\mathit{R}}_{\mathbf{DS},\mathbf{on}}\right)}^{-1}$ [ns${}^{-1}$] |
---|---|---|---|---|---|---|---|

A | 1200 | 3.5–5.7 | −7 | 23 | 182 | trench | 16 |

B | 1200 | 2.7–5.6 | −4 | 22 | 398 | trench | 16 |

C | 1200 | 1.8–N/A | −10 | 25 | 290 | planar | 7 |

D | 1200 | 2.0–4.0 | −10 | 25 | 259 | planar | 14 |

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**MDPI and ACS Style**

Feil, M.W.; Huerner, A.; Puschkarsky, K.; Schleich, C.; Aichinger, T.; Gustin, W.; Reisinger, H.; Grasser, T.
The Impact of Interfacial Charge Trapping on the Reproducibility of Measurements of Silicon Carbide MOSFET Device Parameters. *Crystals* **2020**, *10*, 1143.
https://doi.org/10.3390/cryst10121143

**AMA Style**

Feil MW, Huerner A, Puschkarsky K, Schleich C, Aichinger T, Gustin W, Reisinger H, Grasser T.
The Impact of Interfacial Charge Trapping on the Reproducibility of Measurements of Silicon Carbide MOSFET Device Parameters. *Crystals*. 2020; 10(12):1143.
https://doi.org/10.3390/cryst10121143

**Chicago/Turabian Style**

Feil, Maximilian W., Andreas Huerner, Katja Puschkarsky, Christian Schleich, Thomas Aichinger, Wolfgang Gustin, Hans Reisinger, and Tibor Grasser.
2020. "The Impact of Interfacial Charge Trapping on the Reproducibility of Measurements of Silicon Carbide MOSFET Device Parameters" *Crystals* 10, no. 12: 1143.
https://doi.org/10.3390/cryst10121143