Fabrication of SWCNT-Graphene Field-Effect Transistors ^†

Abstract

Graphene and single-walled carbon nanotube (SWCNT) have been widely studied because of their extraordinary electrical, thermal, mechanical, and optical properties. This paper describes a novel and flexible method to fabricate all-carbon field-effect transistors (FETs). The fabrication process begins with assembling graphene grown by chemical vapor deposition (CVD) on a silicon chip with SiO₂ as the dielectric layer and n-doped Si substrate as the gate. Next, an atomic force microscopy (AFM)-based mechanical cutting method is utilized to cut the graphene into interdigitated electrodes with nanogaps, which serve as the source and drain. Lastly, SWCNTs are assembled on the graphene interdigitated electrodes by dielectrophoresis to form the conductive channel. The electrical properties of the thus-fabricated SWCNT-graphene FETs are investigated and their FET behavior is confirmed. The current method effectively integrates SWCNTs and graphene in nanoelectronic devices, and presents a new method to build all-carbon electronic devices.

1. Introduction

The sp2 carbon hexagonal crystal structure of graphene is a two-dimensional plane structure which is only a single atomic layer thick and considered the materia prima for other forms of carbon [1]. Due to its excellent electronic [2,3] and mechanical [4] properties, graphene has been used as a structure material in field-effect transistors (FETs) [5,6], super capacitors [7], and various sensors [8]. In particular, graphene has been demonstrated to be an excellent candidate for electrodes in all-carbon electronic devices [9,10] because of its low resistivity, high thermal and chemical stability, appropriate work function, and good optical transparency.

Similar to graphene, single-walled carbon nanotube (SWCNT) is also of great interest due to its exceptional electrical, thermal, and mechanical properties. Thus far, extensive research has been conducted to explore the use of SWCNT in FETs and sensors [11,12]. The work function of SWCNT is 4.7–5.05 eV [13,14], and 4.6–4.91 eV [15,16] for graphene. There is a low contact resistance between SWCNT and graphene, which is attributed to their similar work functions. This characteristic is beneficial to the fabrication of high-performance electronics. When SWCNT is used as a semiconducting material in nanoelectronic devices, graphene electrodes have the inherent advantages when compared to metal electrodes. As a first step towards all-carbon-based electronics, the effective integration of SWCNT and graphene in nanoelectronic devices represents an engineering advancement that is important for both scientific study and practical applications.

In the development of all-carbon devices, Cao et al. developed a method to form all-SWCNT devices through layer-by-layer transfer printing of a SWCNT network, though the devices exhibited poor on-off ratios [17]. Subsequently, Li et al., introduced a technique to integrate directly-grown CNTs with reduced graphene oxide electrodes, and the result indicated the gate dependence characteristic was weak [9]. Both techniques require a rigorous experimental environment and extremely expensive support equipment. In addition, deposition of a catalyst is necessary, which can potentially damage or dope the sample. The present paper describes a direct and novel method to fabricate all-carbon FETs. Firstly, graphene grown by chemical vapor deposition (CVD) is assembled on a silicon chip with a 300 nm thick SiO₂ dielectric layer and n-doped Si substrate as the gate through the bubbling method. Secondly, an atomic force microscopy (AFM)-based mechanical cutting method is utilized to cut the graphene into interdigitated electrodes with nanogaps, which serve as the source and drain. This method provides a useful platform to examine the properties of materials at the nanometer, and even the molecular scale which are placed in the nanogaps. Finally, SWCNTs are assembled onto the graphene interdigitated electrodes using dielectrophoresis and serve as the conductive channel. Electrical characterizations indicate the SWCNT-graphene FET exhibits p-type semiconductor properties, which can provide a new method to fabricate all-carbon electronic devices.

2. Materials and Feature Analysis

2.1. Preparation and Assembly of Graphene

CVD-based methods have previously realized the production of large-area continuous graphene films with excellent electronic properties. Here, the graphene is first grown by CVD on a Pt substrate and then assembled onto a microchip through the bubbling method [18]. Figure 1 demonstrates the attachment of a hexagonal graphene to a pair of microelectrodes. The Au microelectrodes are used to form electrical connections with the external characterization equipment in the study.

Figure 1. Optical image of a hexagonal graphene assembled onto a pair of microelectrodes.

Figure 1. Optical image of a hexagonal graphene assembled onto a pair of microelectrodes.

2.2. Choosing the Cutting Force

A separate study was carried out to determine the cutting force required to machine the assembled graphene. Preferably, the cutting force should be high enough to cut through the graphene while having a minimal impact on the substrate underneath. In the study, the graphene is machined by an AFM-based mechanical cutting method using a custom-designed manipulation software. The cutting tool is a diamond-coating AFM tip (DDESP-10) with a tip radius of 35 nm.

In the graphene cutting process, the normal forces (F_N) imposed on the graphene can be determined by:

$$F_N=c_N{S}_Z{V}_N$$

(1)

where $c_N$ is the calibrated normal spring constant of the AFM tip (42 N/m), $S_Z$ is the PSD sensitivity (54 nm/V) obtained from the force curve, and $V_N$ is the vertical deflection signal of the position-sensitive detector (PSD). $F_N$ is adjusted by changing $V_N$.

The relationship between the cutting depth and the normal force is derived as followed. The relationship between $A_H$ and $F_N$ is evaluated as:

$$F_N=p{A}_H$$

(2)

where p is the yield average pressure of fabricated materials in the vertical direction and $A_H$ is the horizontal projected area of the interface between the AFM tip and the surface. The horizontal projected area can be determined by:

$$A_H\approx \text{π}RD$$

(3)

where D is the cutting depth and R is the radius of the AFM tip. Combining Equation (3) and Equation (2) yields:

$$D=k{F}_N$$

(4)

where $k=1/\text{π}Rp$.

From Equation (4), it can be concluded that the cutting depth is linearly proportional to the normal force. An experimental study is carried out to verify this linear relationship.

The graphene sample is assembled onto a microchip, and the thickness of the graphene is measured to be about 4.3 nm, as shown in Figure 2. The reason the overall graphene thickness is larger than a pure graphene monolayer is due to residual polymethyl methacrylate (PMMA) in the assembly process of the graphene [18]. The graphene is cut at various $V_N$ of 6, 7, 8, and 9 V at the same cutting velocity of 2 μm/s. $F_N$ at $V_N$ of 6, 7, 8, and 9 V are 13.6, 15.88, 18.14, and 20.4 μN, respectively. Figure 3 demonstrates the experimental result. Figure 3c indicates the relationship between the cutting depth and the normal force is indeed linear. Based on the thickness of the graphene sample and this linear relationship, the appropriate cutting force for machining graphene can be determined. For example, when the normal force is 15.88 μN, the cutting depth is 4.9 nm, as shown in Figure 3c. At this cutting depth, the 4.3 nm thick graphene sample shown in Figure 2a is cut through. There is a minimal impact on the 300 nm thick SiO₂ dielectric layer, which is used in subsequent experiments. Figure 4 demonstrates the effect of the cutting velocity. Different cutting velocities of 2, 4, 6, 8, and 10 μm/s with a fixed normal force of 15.88 μN are investigated. No specific relationship is observed between the cutting depth and the cutting velocity, as shown in Figure 4c. For the subsequent experiments, the cutting velocity was selected according to the length of the graphene to be machined.

Figure 2. (a) Height image of the graphene in AFM tapping mode and (b) height analysis trace along the white line in (a).

Figure 2. (a) Height image of the graphene in AFM tapping mode and (b) height analysis trace along the white line in (a).

Figure 3. (a) Height image of the graphene before cutting; (b) height image of the graphene after cutting at different normal forces of 13.6 μN (I), 15.88 μN (II), 18.14 μN (III), and 20.4 μN (IV) with a cutting velocity of 2 μm/s; and (c) the cut depth versus the normal force.

Figure 3. (a) Height image of the graphene before cutting; (b) height image of the graphene after cutting at different normal forces of 13.6 μN (I), 15.88 μN (II), 18.14 μN (III), and 20.4 μN (IV) with a cutting velocity of 2 μm/s; and (c) the cut depth versus the normal force.

Figure 4. (a) Height image of the graphene before cutting; (b) height image of the graphene after cutting at cutting velocities of 2 μm/s (I), 4 μm/s (II), 6 μm/s (III), 8 μm/s (IV), and 10 μm/s (V) with normal force of 15.88 μN; and (c) the cut depth versus the cutting velocity.

Figure 4. (a) Height image of the graphene before cutting; (b) height image of the graphene after cutting at cutting velocities of 2 μm/s (I), 4 μm/s (II), 6 μm/s (III), 8 μm/s (IV), and 10 μm/s (V) with normal force of 15.88 μN; and (c) the cut depth versus the cutting velocity.

2.3. Designing the Cutting Path

A cutting path of the AFM tip is designed to convert the continuous graphene into interdigitated electrodes. The hexagonal graphene assembled on the gold electrodes is shown in Figure 5a. The cutting path shown in Figure 5b consists of the following two steps: (1) the graphene on both sides of the Au electrodes is first cut through to reduce the width of the grapheme; (2) the resulting graphene ribbon is then cut along a zigzag path to achieve the interdigitated electrodes, as shown in Figure 5c.

Figure 5. The cutting path design. (a) Graphene assembled on microelectrodes; (b) sequence of cutting paths; and (c) structure of the graphene interdigitated electrodes.

Figure 5. The cutting path design. (a) Graphene assembled on microelectrodes; (b) sequence of cutting paths; and (c) structure of the graphene interdigitated electrodes.

2.4. Effects of Defects on the Electrical Properties of Graphene

As an electrode material, graphene consists of fabrication-induced structural defects that can significantly affect its electronic properties and the performance of graphene-based devices. Therefore, a thorough study of the defects in graphene is critically important before the fabrication of the graphene electrodes. Direct observation of the topological defects in graphene is quite rare [19,20]. In these studies, the location of the induced defect is not well controlled, and complicated experimental methods are needed. There is a need to develop a reliable methodology through which graphene defects can be induced in a controlled manner and examined at the same time. In this study, an AFM-based mechanical cutting method is developed to induce graphene defects at specific locations and analyze these defects at the same time.

Figure 6 shows the formation and analysis of line defects in graphene. An AFM image of the pristine graphene before defect induction is shown in Figure 6a. The I-V curve of this graphene is shown in Figure 6b. In order to better evaluate the effect of defects, we first cut the graphene into a 2 μm ribbon, as shown in Figure 6c. Defects in the form of a single scratch, and then two line scratches, are induced in the graphene ribbon, as shown in Figure 6e,g. The electrical resistance of the graphene samples shown in Figure 6b,d,f,h are 0.51, 1.39, 1.63, and 2.22 kΩ, respectively. Based on these measurements, it can be concluded that a graphene ribbon with line defects exhibits electrical degradation. The fabrication-induced structural defects in the graphene give rise to lattice disturbance which can affect the electronic properties of the graphene due to Anderson localization [21], which is consistent with the theoretical prediction of the influence of defects on the electrical properties of graphene.

Figure 6. Electrical characterization of graphene with and without line defects. (a) AFM image of graphene before defects are induced; (b) I-V curve before defects are induced; (c) AFM image of 2 μm wide graphene ribbon; (d) I-V curve of 2 μm wide graphene ribbon. (e) AFM image of graphene after first defect is induced in the graphene ribbon. The red ellipse indicates the location of the defect; (f) I-V curve after first defect is induced in the graphene ribbon; (g) AFM image of graphene after second defect is induced; and (h) I-V curve after second defect is induced.

Figure 6. Electrical characterization of graphene with and without line defects. (a) AFM image of graphene before defects are induced; (b) I-V curve before defects are induced; (c) AFM image of 2 μm wide graphene ribbon; (d) I-V curve of 2 μm wide graphene ribbon. (e) AFM image of graphene after first defect is induced in the graphene ribbon. The red ellipse indicates the location of the defect; (f) I-V curve after first defect is induced in the graphene ribbon; (g) AFM image of graphene after second defect is induced; and (h) I-V curve after second defect is induced.

2.5. SWCNT Suspension Preparation and Dielectrophoretic Assembly

High-quality SWCNT suspension is prepared for assembling SWCNTs on graphene electrodes. The dispersion and purification methods of the suspension have been described in our previous publication [22].

Dielectrophoresis [23] has been employed in many electric field-driven alignment processes. In the present study, an alternating current (AC) voltage is applied to the graphene interdigitated electrodes to generate a homogenous electric field in the electrode gap. When a drop of the SWCNT suspension is deposited in the gap, differences in the dielectric permittivity of the SWCNTs and the surrounding medium give rise to a dielectrophoretic force that moves and aligns the deposited SWCNTs following the electric field direction between the electrodes.

3. Fabrication and Characterization of SWCNT-Graphene FET

The fabrication process of the SWCNT-graphene FET is as follows: graphene is first assembled on a silicon chip with a 300-nm thick SiO₂ as the dielectric layer and an n-doped Si substrate as the gate. Next, the AFM-based mechanical cutting method is used to cut the graphene into interdigitated electrodes. They serve as the source and drain of the FET. Finally, SWCNTs are assembled on the graphene interdigitated electrodes by dielectrophoresis to form the conductive channel. The schematic of SWCNT-graphene FET is shown in Figure 7.

Figure 7. Schematic of the SWCNT-graphene FET.

Figure 7. Schematic of the SWCNT-graphene FET.

3.1. Characterization of Graphene Interdigitated Electrodes

The I-V curve of the pristine graphene assembled on the microchip as shown in Figure 8a is shown in Figure 8b. The source voltage ranges from −1 to 1 V at 10 mV steps. It can be observed that the I-V curve is linear. The electrical resistance is about 0.88 kΩ, which represents a combination of the electrical resistance of the following components: graphene, Au electrodes, the contact between graphene and Au electrodes, and the contact between Au electrodes and the conductive tip used for the measurement. Figure 8c demonstrates a graphene ribbon with a width of 9.5 μm, fabricated according to the cutting step 1 in Figure 5b. Its I-V curve is shown in Figure 8d. It can be seen that the I-V curve is linear as well. The corresponding electrical resistance of the ribbon is about 1 kΩ, which is higher than that of the pristine graphene shown in Figure 8a. This result verifies that when the width of a graphene sample decreases, its resistance increases.

The graphene ribbon is cut through along a zigzag path into two interdigitated electrodes, as displayed in Figure 8e. Figure 8f demonstrates the absence of current flow between the graphene electrodes, proving that the graphene ribbon is cut through completely. The smallest nanogap width between the graphene interdigitated electrodes is 94 nm. The average width is 97 nm and the standard deviation (SD) is 3.6 nm. The widths of the smallest and largest electrode fingers are 1.1 μm and 1.8 μm, respectively. The graphene interdigitated electrodes with a nanogap can be used to characterize the electrical properties of any nanoscale material placed in the nanogap.

Figure 8. Height image of the graphene ribbon. (a) AFM image before cutting; (b) I-V curve before cutting; (c) AFM image after the first cut. The width of the graphene ribbon between the electrodes is 9.5 μm; (d) I-V curve after the first cut; (e) AFM image after interdigitated electrodes are formed; and (f) I-V curve after interdigitated electrodes are formed.

Figure 8. Height image of the graphene ribbon. (a) AFM image before cutting; (b) I-V curve before cutting; (c) AFM image after the first cut. The width of the graphene ribbon between the electrodes is 9.5 μm; (d) I-V curve after the first cut; (e) AFM image after interdigitated electrodes are formed; and (f) I-V curve after interdigitated electrodes are formed.

3.2. Assembly of SWCNT on Graphene Interdigitated Electrodes by Dielectrophoresis

After the fabrication of the graphene interdigitated electrodes, SWCNTs are assembled onto the electrodes by dielectrophoresis to form a conductive channel. If the external electric field used in the dielectrophoresis process is nonhomogenous, the SWCNTs will experience a dielectrophoretic force, as defined by the following equation [24]:

$$F=\text{π}{r}^{2}l{\text{ε}}_m{R}_e\left[f_{cm}\right]\nabla E_{rms}^2/6$$

(5)

where r is the radius of the SWCNTs, l is the length the SWCNTs, $R_e\left[f_{cm}\right]$ is the real part of the Clausius-Mossotti factor $f_{cm}$, and $\nabla E_{rms}$ is the gradient of the root mean square value of the external electric field. The Clausius-Mossotti factor $f_{cm}$ can be determined by:

$$f_{cm}=({\text{ε}}_p^{*}-{\text{ε}}_m^{*})/(({\text{ε}}_p^{*}-{\text{ε}}_m^{*})A_L+{\text{ε}}_m^{*})$$

(6)

$${\text{ε}}^{*}=\text{ε}-j\text{σ}/\text{ω}$$

(7)

where ${\text{ε}}^{*}$ is the complex permittivity that consists of the physical permittivity ε, conductivity σ, and the angular velocity ω of the external electric field. The subscripts p and m represent the particle and the medium, respectively. $A_L$ is the depolarization factor along the long axis.

For SWCNT, the dielectrophoretic force is determined by the real part of the Clausius-Mossotti factor $f_{cm}$ and $\nabla E_{rms}^2$. $R_e\left[f_{cm}\right]$ mainly contributes to the magnitude of the dielectrophoretic force while $\nabla E_{rms}^2$ determines both the magnitude and the direction of the dielectrophoretic force. Once the particle, medium, and angular velocity of the external electric field are defined, the dielectrophoretic force is proportional to $\nabla E_{rms}^2$ as described in Equation (5).

To better understand the assembly process of SWCNTs between the graphene interdigitated electrodes described above, the electric field and $\nabla E_{rms}^2$ distribution generated by the electrodes is simulated by COMSOL Multiphysics coupling software. Figure 9a shows the potential and direction of the electric field and $\nabla E_{rms}^2$ distribution. The white arrows indicate the direction of the electric field. The black arrows indicate the direction of $\nabla E_{rms}^2$, which mainly point towards the corner of the graphene interdigitated electrode gap according to the simulation. This result implies that the direction of the dielectrophoretic force points towards the corners of the graphene interdigitated electrode gap. Figure 9b shows the contour map of the $\nabla E_{rms}^2$ magnitude. It can be seen that $\nabla E_{rms}^2$ is mainly concentrated in the corners of the electrode gap, and the largest dielectrophoretic force experienced by the SWCNTs is therefore also at the corners of the electrode gap according to the simulation.

In the assembly process of SWCNTs by dielectrophoresis, control parameters, such as the alignment voltage, frequency, and duration, must be closely regulated and monitored. Accordingly, an electrophoresis assembly system is developed to carry out the assembly process. In this process, one 2 μL drop of diluted SWCNT solution is placed on the graphene electrode chip using a pipette. Then an AC voltage is applied to the graphene electrodes at a frequency of 1 MHz and peak-to-peak voltage of 10 V by an arbitrary function generator (Escort, Taipei, Taiwan) to generate a dielectrophoretic force to assemble and align the SWCNTs in the graphene interdigitated electrodes gap. After 3–5 s, the AC voltage is switched off. The actual number of SWCNTs assembled in the nanogap is affected by the time the AC voltage is applied. After alignment, the electrode chip is tilted at 45° angle and slowly rinsed by deionized water for about 50 s to move the remains of sodium dodecyl sulfate. Then, the chip dried at room temperature.

The completed SWCNT-graphene FET is shown in Figure 10. From Figure 10a, it can be seen that all SWCNTs are distributed between the graphene interdigitated electrodes. The diameter of the SWCNT is about 2.5 nm, and the length of the SWCNT is from 180 nm to 1.2 μm, as shown in Figure 10b. It can be seen that the SWCNTs are mostly distributed around the corners of the graphene electrodes, and the experimental and simulation results agree well. In order to prove that the SWCNTs are constrained to the nanogaps and not extended all the way to Au electrodes, the SEM image of the area between the Au electrodes is shown in Figure 11. In this all-carbon FET fabricated by assembled SWCNTs on graphene interdigitated electrodes, the only pathway for charge transport is through the junctions between the graphene and SWCNTs. The SWCNTs do not have any physical connection with the Au electrodes, and the Au electrodes are only used to form electrical connections with the external electronics for measurement.

Figure 9. Numerical simulation of potential, electric field, and $\nabla E_{rms}^2$ distribution generated by an external AC voltage. (a) Potential and direction of electric field and $\nabla E_{rms}^2$ distribution and (b) $\nabla E_{rms}^2$ magnitude distribution.

Figure 9. Numerical simulation of potential, electric field, and $\nabla E_{rms}^2$ distribution generated by an external AC voltage. (a) Potential and direction of electric field and $\nabla E_{rms}^2$ distribution and (b) $\nabla E_{rms}^2$ magnitude distribution.

Figure 10. (a) AFM image of SWCNT-graphene FET and (b) partial enlargement figure of (a).

Figure 10. (a) AFM image of SWCNT-graphene FET and (b) partial enlargement figure of (a).

Figure 11. SEM image of SWCNT-graphene FET.

Figure 11. SEM image of SWCNT-graphene FET.

3.3. SWCNT-Graphene FETs Characteristic Test

The electrical characteristics of the SWCNT-graphene FET are investigated after the assembly. The FET characterization system is built as shown in Figure 12. Three metal needle probes serve as the electrical contacts to the FET. The I-V curves are collected by an Agilent 4155C semiconductor parameter analyzer (Agilent, Tokyo, Japan). Figure 13 shows the characterization results of the SWCNT-graphene FET at room temperature. The gate voltage varies from −16 to 16 V, and the source-drain voltage varies from −1 to 1 V at 10 mV steps. The source-drain current decreases gradually as the gate voltage is raised from −16 to +16 V, demonstrating an effective physical assembly and electrical connection between the SWCNTs and graphene, and indicating a p-type behavior in the device channel. When the source-drain voltage is −1 V, and the gate voltage is +16 V, the source-drain current is lower than −1000 nA. When the gate voltage is −16 V, the source-drain current is about −2535 nA at a source-drain voltage of −1 V. The low on-off ratio in this device indicates the presence of metallic SWNTs in the conductive channel, which are not modulated by the gate voltage. It is noted that the performance of the FET could be potentially improved by an electrical burning process to remove the metallic SWCNTs [25]. The structure of the graphene electrodes and length of the conductive channel can be changed by selecting the appropriate AFM tip and designing different cutting paths, which can then be used to investigate the variation of I-V curves and further improve the quality of the FET.

Figure 12. SWCNT-graphene FET electrical characterization system.

Figure 12. SWCNT-graphene FET electrical characterization system.

Figure 13. SWCNT-graphene FET electrical characteristics.

Figure 13. SWCNT-graphene FET electrical characteristics.

4. Conclusions

In this paper, graphene grown by CVD is assembled onto a Au microelectrode chip through the bubbling method. An AFM-based mechanical cutting method is then used to cut the assembled graphene first into a ribbon, and then into interdigitated electrodes with a nanogap. The electrical properties of the graphene ribbon are measured after each cut. As the width of the ribbon decreases, the resistance increases. The width of the nanogap between the graphene interdigitated electrodes is 94 nm. The widths of the smallest and largest electrode are 1.1 μm and 1.8 μm, respectively. The graphene interdigitated electrodes with a nanogap have the potential to be used to probe macromolecules in the one hundred nanometers range [26]. By selecting the appropriate AFM tip, cutting force, and number of cutting passes, the width of the graphene electrodes and nanogap can be further reduced to increase the density of the electrodes and increase the sensitivity and response time of a molecular sensor based on the graphene electrodes. On this basis, SWCNTs are assembled onto graphene interdigitated electrodes using dielectrophoresis for the first time. The SWCNTs are concentrated around the corners of the interdigitated electrodes, as predicted by numerical simulation. Preliminary verification indicates the SWCNT-graphene FET exhibits p-type behavior, which presents a new approach to build all-carbon electronic devices.