Design of a Dual-Band Low-Noise Amplifier with a Novel Matching Structure

Abstract

This paper proposes a method for designing a dual-band low-noise amplifier (DB-LNA) using a new improved complex impedance dual-band transformer (IDBT). This complex IDBT is composed of parallel-coupled lines and two sections of series microstrip lines. The parallel-coupled lines are used to complete the transformation from complex impedances at two different frequencies to a pair of conjugate complex impedances, meanwhile eliminating the need for DC blocking capacitors. The transformation to real impedances is achieved by series microstrip lines at dual frequency points. A single-stage DB-LNA was designed using the BFP840ESD transistor in combination with the proposed IDBT. The fabrication and testing of the Printed Circuit Board (PCB) were then completed. The measured results of the proposed 2.4/5.5 GHz DB-LNA show an S21 parameter of 20.3/14.7 dB, an S11 of −29.8/−20.3 dB, an S22 of −15.2/−16.4 dB, and a noise figure (NF) of 1.6/1.6 dB. The whole DB-LNA has a simple structure, low cost, and excellent performance and is easy to tune.

1. Introduction

With the advancement of wireless technology, wireless local area networks (WLANs) are playing an increasingly crucial role in people’s lives. Concurrently, as WLAN standards continue to proliferate, multi-band, multi-functional, and cost-effective WLAN devices are demanded to enhance both device integration and user convenience. Meanwhile, for the convenience of communication device usage, 5 GHz band WLANs must be back-ward-compatible with the 2.4 GHz band [1]. WLAN communication performance is significantly influenced by the LNA in the RF front-end. Therefore, LNAs are required by dual-band WLANs to support simultaneous dual-band operation.

Over the years, numerous DB-LNA design structures have been proposed, including parallel [1], switch-tunable [2], broadband [3], and concurrent configurations [4,5,6,7,8,9,10,11]. Among these, the concurrent DB-LNA topology (illustrated in Figure 1) is composed of an input matching network (IMN), an output matching network (OMN), a dual-band bias network, and a transistor. This configuration offers key advantages, such as simultaneous operation across two distinct frequency bands, enabling effective amplification of in-band signals while suppressing out-of-band interference. However, concurrent DB-LNAs also present significant challenges: (1) complex matching network design, requiring precise dual-frequency impedance matching within a single channel; (2) degraded in-band noise performance and limited gain in target frequency bands; and (3) excessive discrete components, where parasitic effects from externally soldered DC-blocking capacitors compromise IMN/OMN performance. The core challenge lies in the matching circuit design. Early approaches leveraged traditional microstrip line theory [12,13,14,15], while later advancements incorporated parallel-coupled lines [16,17,18,19]. Recent systematic studies [12,13,14,15,16,17,18,19] have focused on IDBTs as a key innovation, conducting multidimensional optimizations to address these limitations.

Therefore, a novel IDBT structure based on parallel-coupled lines and microstrip lines is proposed in this paper. The DC-blocking capacitor is eliminated by the inherent characteristic of parallel-coupled lines in this IDBT structure, thus reducing parasitic parameter effects. Meanwhile, no microstrip stubs are included, which not only simplifies the overall design but also contributes to the realization of a more compact transformer structure. The theoretical analysis and detailed parameter calculation of this transformer structure have been comprehensively conducted. In this study, the design and measurement of a DB-LNA are implemented using both the proposed IDBT structure and discrete components, specifically the Infineon BFP840ESD transistor. The amplifier is fabricated through Rogers 4350B PCB board-level processing, with comprehensive experimental characterization subsequently performed.

2. Design Theory and Analysis

This section consists of the following parts:

• First of all, the IDBT proposed for adoption in this paper will be introduced as a whole.
• Secondly, the relevant theory of parallel-coupled lines will be introduced to theoretically prove the feasibility of the design.
• Thirdly, the calculation method of the two-section series microstrip lines in Part II will be introduced.
• Finally, the implementation method of low NF in the DB-LNA will be analyzed.

2.1. Complex IDBT

The schematic diagram of the new complex IDBT used in this article is shown in Figure 2. The structure consists of Part I and Part II. Part I includes a section of parallel-coupled lines with electrical length θ₃ and odd–even characteristic impedance Z_oo and Z_oe. Part II includes two sections of series microstrip transmission lines with characteristic impedances Z₁ and Z₂, respectively, and electrical lengths θ₁ and θ₂. All connections in the entire structure are realized using gradient microstrip lines of length L_T. In Figure 2, Z_L represents the complex impedance from the transistor gate or drain, denoted as Z_L1 and Z_L2 at two different frequencies f₁ and f₂ (f₁ < f₂). It is assumed that Z_L1 = R_L1 + jX_L1 @ f₁ and Z_L2 = R_L2 + jX_L2 @ f₂ will have different complex values at different frequencies in most cases, so R_L1 and R_L2, and X_L1 and X_L2 are not equal and are independent of frequency. Part I transforms Z_L1 and Z_L2 at frequencies f₁ and f₂ into a pair of conjugate impedance values Z_in1 and Z_in2 through parallel-coupled lines. Part II converts the conjugate Z_in1 and Z_in2 into Z₀ at both frequencies through two sections of series microstrip transmission lines.

2.2. Parallel-Coupled Line Theory

As shown in Figure 3, when ports 2 and 4 of the structure are open-circuited, the parallel-coupled line structure is equivalent to a two-port device, and the corresponding impedance matrix equation can be represented by Equation (1):

$${\displaystyle {\{}_{V_3 = Z_{31}{I}_1 + Z_{33}{I}_3}^{V_1 = Z_{11}{I}_1 + Z_{13}{I}_3}}$$

(1)

Then its ABCD matrix is given by Equation (2):

$$[{}_C{}^A_D^B]=\left[{}_{{\displaystyle \frac{2j}{(Z_{oe}-Z_{oo})\csc {\theta }_2}}}{}^{{\displaystyle \frac{(Z_{oe}+Z_{oo})\cot {\theta }_2}{(Z_{oe}-Z_{oo})\csc {\theta }_2}}} \left.{}_{{\displaystyle \frac{(Z_{oe}+Z_{oo})\cot {\theta }_2}{(Z_{oe}-Z_{oo})\csc {\theta }_2}}}{}^{{\displaystyle \frac{j}{2}}{\displaystyle \frac{Z_{oe}^2+Z_{oo}^2-2Z_{oe}{Z}_{oo}({\cos }^2{\theta }_2+{\csc }^2{\theta }_2)}{(Z_{oe}-Z_{oo})\csc {\theta }_2}}}\right]\right.$$

(2)

In Figure 2, after the transformation by the Part I parallel-coupled line, the conjugate impedance obtained can be expressed as Equation (3):

$$Z_{in2}=R_{in1}-j{X}_{in1}=Z_{in1}^{*}$$

(3)

Here, the asterisk (*) in Equation (3) represents the conjugate complex impedance.

The parallel-coupled line can simultaneously transform Z_L1 and Z_L2 at two frequencies into Z_in1 and Z_in2, which are conjugate to each other. The relevant calculation process is presented in Equations (4a) and (4b) as follows:

$$R_{in1}={\displaystyle \frac{A_1(R_{L1}+j{X}_{L1})+B_1}{C_1(R_{L1}+j{X}_{L1})+D_1}}$$

(4a)

$$R_{in2}={\displaystyle \frac{A_2(R_{L2}+j{X}_{L2})+B_2}{C_2(R_{L2}+j{X}_{L2})+D_2}}$$

(4b)

Then, combining Equations (2) and (4), we can obtain Equations (5a) and (5b):

$$(Z_{oe}+Z_{oo})(R_{in1}-R_{L1})\cot \theta =2R_{in1}{X}_{L1}$$

(5a)

$$\begin{array}{l}2(Z_{oe}+Z_{oo})\cot \theta X_{L1}+[Z_{oe}^2+Z_{oo}^2\\ -Z_{oe}{Z}_{oo}({\cos }_{\theta }^2+{\csc }_{\theta }^2)]=4R_{in1}{R}_{L1}\end{array}$$

(5b)

At the two frequencies f₁ and f₂, by simultaneously solving Equation (5), we can obtain a set of simple analytical design equations for the even-mode and odd-mode characteristic impedances of the parallel-coupled line, as shown in Equation (6):

$$Z_{oo}={\displaystyle \frac{R_{in1}{X}_{L1}\tan {\theta }_3}{R_{in1}-R_{L1}}}(1\pm \sqrt{1-{\displaystyle \frac{2}{1+{\cos }_{{\theta }_3}^2+{\csc }_{{\theta }_3}^2}}})$$

(6a)

$$Z_{oe}={\displaystyle \frac{2R_{in1}{X}_{L1}\tan {\theta }_3}{(R_{in1}-R_{L1})}}-Z_{oo}$$

(6b)

In Equation (6), “$\pm$” needs to be flexibly selected according to the actual situation.

Here, the electrical length of the parallel-coupled line can be expressed as Equation (7):

$${\theta }_3 | f_1={\displaystyle \frac{\pi }{1+p}}$$

(7)

In Equation (7), p = f₂/f₁. Assume (f₁ < f₂). In this way, based on Equations (6) and (7), the even-mode and odd-mode impedances and the electrical length related to the parallel-coupled lines can be obtained.

2.3. Design of Two-Section Microstrip Transmission Lines in Part II

In Figure 2, the parameters of the parallel-coupled lines are determined, transforming the load impedance into a pair of conjugate complex impedance values, which are to be transformed into the desired impedance by two sections of microstrip lines in Part II. Thus, we can obtain the following Expression (8):

$$Z_0=Z_1{\displaystyle \frac{Z_{ina}+j{Z}_1\tan ({\theta }_1)}{Z_1+j{Z}_{ina}\tan ({\theta }_1)}}$$

(8a)

$$Z_{ina}=Z_2{\displaystyle \frac{Z_{in}+j{Z}_2\tan ({\theta }_2)}{Z_2+j{Z}_{in}\tan ({\theta }_2)}}$$

(8b)

Assuming that at frequency f₁, Z_in1 = R_in1 + jX_in1, Equation (8) can be rewritten as follows:

$$\begin{array}{l}{Z}_0{X}_{in1}(Z_1\tan ({\theta }_2 | f_2)+Z_2\tan ({\theta }_1 | f_1))+Z_1{Z}_2{R}_{in1}\\ -Z_1{Z}_2{Z}_0-\tan ({\theta }_1 | f_1)\tan ({\theta }_2 | f_2)(R_{in1}{Z}_1^2-Z_0{Z}_2^2)=0\end{array}$$

(9a)

$$\begin{array}{l}{Z}_0{R}_{in1}(Z_1\tan ({\theta }_2 | f_2)+Z_2\tan ({\theta }_1 | f_1))\\ -Z_1^2{Z}_2\tan ({\theta }_1 | f_1)-Z_1{Z}_2^2\tan ({\theta }_2 | f_2)-Z_1{Z}_2{Z}_{in1}\\ +X_{in1}\tan ({\theta }_1 | f_1)\tan ({\theta }_2 | f_2)=0\end{array}$$

(9b)

Expressions (9) correspond to two frequencies, resulting in four variables for the two equations. Generally, such equations can only be solved by numerical methods or optimization algorithms. Due to the conjugate relationship of Z_in, similar to [13,14], the following Equation (10) can be obtained:

$$\tan ({\theta }_1 | f_1)\pm \tan ({\theta }_1 | f_1)=0$$

(10a)

$$\tan ({\theta }_2 | f_2)\pm \tan ({\theta }_2 | f_2)=0$$

(10b)

Further assume that θ = βl. Substituting this into Equation (10), we can obtain the roots of l₁ and l₂. Similarly to the analysis in [14], considering the area, we choose Equation (11):

$$l_1=l_2={\displaystyle \frac{\pi }{{\beta }_a+{\beta }_b}}=l$$

(11)

Let us further define a = tan(β_al). Considering the requirement for a small area, in the minimum case, the following Expression (12) can be listed:

$$Z_1^4+b{Z}_1^3+c{Z}_1^2+d{Z}_1+e=0$$

(12)

$$b={\displaystyle \frac{2a{R}_0{X}_{in}}{R_0-R_{in}}}$$

(12a)

$$c={\displaystyle \frac{R_0{R}_{in}(X_{in}^2-{(R_0-R_{in})}^2)-X_{in}^2{R}_0^2{(1+a^2)}^2}{a^2{R}_{in}(R_{in}-R_0)}}$$

(12b)

$$d={\displaystyle \frac{2a{R}_0^3{X}_{in}}{R_{in}-R_0}}$$

(12c)

$$e={\displaystyle \frac{R_0^3(R_{in}^2+X_{in}^2-R_0{R}_{in})}{R_0-R_{in}}}$$

(12d)

Based on Equation (12), it is easy to solve this fourth-order equation, thereby obtaining the value of Z₁. Then, according to Formula (9), the impedance values and electrical lengths of the two-section microstrip transmission lines in Part II can be determined.

2.4. Implementation of Low NF in the DB-LNA

The basic definition of the NF is the ratio of the signal-to-noise ratio at the amplifier input to that at the output. The NF is an important indicator for LNAs. For a single-stage amplifier, the NF [3] can be expressed as Equation (13):

$$F=F_{\min }+{\displaystyle \frac{4r_n\left|{\mathrm{\Gamma }}_s-{\mathrm{\Gamma }}_{opt}\right|}{(1-{\left|{\mathrm{\Gamma }}_s\right|}^2){\left|1+{\mathrm{\Gamma }}_{opt}\right|}^2}}$$

(13)

Here, F_min is the minimum NF of the transistor, Г_opt is the source reflection coefficient for obtaining the minimum NF, and r_n is the normalized noise resistance. These three parameters are all noise parameters of the transistor. Г_s is the actual source reflection coefficient of the amplifier; F_min is a function of the transistor operating current and frequency, and for each F_min there is a corresponding Г_opt. For LNAs, the role of the IMN is to achieve equal-value matching between the source impedance and the input impedance corresponding to the minimum NF of the transistor. The OMN needs to achieve conjugate matching between the output impedance and the load impedance to achieve high gain, which is also a relatively difficult goal. The dual-band IMN proposed in this paper achieves equal-value matching at two frequency points simultaneously to obtain a low NF, while the OMN realizes conjugate matching at both frequencies concurrently to achieve high gain.

The above approach is summarized in the flowchart in Figure 4a. And Figure 4 plots the simulated available gain (G_A) and NF circles at 2.4 GHz (b) and 5.5 GHz (c). At 2.4 GHz (a), the Г_opt is matched to 0.1∠−124° through the parallel-coupled line and then matched to 0.07∠175° through L₂ and matched to 50 Ω through L₁ to achieve a minimum NF = 0.8 dB, with G_A = 20.9 dB. Similarly, at 5.5 GHz, the Г_opt is matched to 50 Ω through the parallel-coupled line and L₂ and L₁ to achieve a minimum NF = 0.9 dB, with G_A = 16.4 dB. Figure 4d depicts the process of dual-frequency impedance matching. Similarly to input matching, the OMN conjugately matches the value of Ga_opt to 50 Ω at 2.4 GHz and 5.5 GHz, respectively, aiming to achieve maximum power transfer.

3. Implementation and Measurement

Based on the above theoretical analysis, the 2.4/5.5 GHz DB-LNA has been fabricated. Based on the Infineon heterojunction bipolar transistor BFP840ESD, the IDBT analyzed in Part II is utilized as the IMN and OMN structures, and a bias circuit is designed for it. Figure 5 shows the complete circuit diagram (a) and the physical picture (b). Rogers 4350B board material is used, with a thickness of 0.762 mm, a dielectric constant of 3.66, and a dielectric loss tangent of 0.0037. The resistors, capacitors, and inductors are from Panasonic’s ERJ3GEYJ series and Murata’s GRM1885C1H series and LQG18HN series, respectively. The fabricated PCB with dimensions of 85 mm × 16 mm is physically demonstrated in Figure 5b; the bias circuit, IMN, OMN, etc., are all marked.

As can be seen from Figure 6, the EM simulated insertion losses of the IMN are 2.5 dB and 1.4 dB at 2.4 GHz and 5.5 GHz. In the measurement, the S-parameters of this DB- LNA were measured by a 3656B network analyzer (Siglent SNA5000A), and its noise was analyzed by a spectrum analyzer (Siglent SSA5000A). A vector network analyzer (N5244A) and a power sensor (U2021XA) were utilized to measure the linearity. The simulated and measured performances are shown in Figure 7, from which it can be seen that it can cover frequency ranges of 2.33–2.46 GHz and 5.43–5.58 GHz. Meanwhile, the corresponding S11 values are −29.8 dB and −20.3 dB, the corresponding S22 values are −15.2 dB and −16.4 dB, the corresponding S21 values are 20.3 dB and 14.7 dB, and the corresponding NF values are 1.6 dB and 1.6 dB. In the operating frequency bands, the stability factor is greater than 1.1, indicating that it is absolutely stable within the operating frequency bands. The linearity of the DB-LNA is checked by feeding one tone with RFpower from −100 dBm to 0 dBm, with the 2.4 GHz and 5.5 GHz power gain and P1dB illustrated in Figure 8a,b. The dependence of IIP3 on frequency is also depicted in Figure 8c. Due to the parallel-coupled line configuration, the developed LNA exhibits good linearity within the design frequency band.

The proposed DB-LNA in this work was designed, simulated, and measured. For the actual design, the measured results are shown in

Table 1. Performance comparison of DB-LNAs.

Ref.	Frequency (GHz)	S11 (dB)	S22 (dB)	S21 (dB)	NF (dB)	Size (mm2)	Power (mW)	Technology
[4]	2.4	−11.3	−24.6	33.84	0.946	-	-	GaAs MMIC
	5.75	−17.4	−11.1	20	0.493
[5]	2.4	−10	−8	20	2.2	1.5 × 1	37.8	GaAs MMIC
	5	−7	−6	15	2.0
[6]	2.45	−20	-	22	1.5	30 × 30	7.5	HMIC
	5.2	−21	-	12	1.6
[7]	2.3–2.5	−8.5	-	3–12.2	0.5–5	55 × 60	41.25	HMIC
	4.2–4.6	−15	-	9.5–12.9	2.5–5
[8]	2.44	−10.5	-	7.15	4.34	-	35.1	HMIC
	5.25	−15.9	-	7.8	4.69
[9]	2.4	−25	-	11.6	3.96	120 × 34	56	HMIC
	5.7	−12	-	8.9	2.89
This Work	2.33–2.46	−29.8	−15.2	20.3	1.6	16 × 85	39.3	HMIC
	5.43–5.58	−20.3	−16.4	14.7	1.6

. Due to the limitation of the technique and manufacture, some deviations exist between the simulation and measurement.

4. Conclusions

In this paper, a low-cost, board-level DB-LNA featuring a novel matching structure with simplified architecture is presented. A hybrid matching network combining parallel-coupled lines and microstrip lines is utilized in the design, and the inherent DC-blocking characteristics of the coupled lines are leveraged to eliminate external blocking capacitors. Reliability is improved by avoiding solder joint effects and parasitic parameters through this approach. Measured results show excellent performance, with dual-band operation at 2.4/5.5 GHz, S21 > 14 dB, and NF < 1.7 dB. The proposed DB-LNA exhibits strong potential for WLAN applications.