Performance Improvement of Wireless Power Transfer System for Sustainable EV Charging Using Dead-Time Integrated Pulse Density Modulation Approach

Abstract

The recent developments in electric vehicle (EV) necessities the requirement of a human intervention free charging system for safe and reliable operation. Wireless power transfer (WPT) technology shows promising options to automate the charging process with user convenience. However, the operation of the WPT system is designed to operate at a high-frequency (HF) range, which requires proper control and modulation technique to improve the performance of power electronic modules. This paper proposes a dead-time (DT) integrated Pulse Density Modulation (PDM) technique to provide better control with minimal voltage and current ripples at the switches. The proposed technique is investigated using a LCC-LCL compensated WPT system, which predominantly affects the high-frequency voltage and current ripples. The performance analysis is studied at different density conditions to explore the impact of the integrated PDM approach. Moreover, the PDM technique gives better control over the power transfer at different levels of load requirement. The simulation and experimental analysis was performed for a 3.7 kW WPT prototype test system under different modes of operation of the high-frequency power converters. Both the simulated and experimental results demonstrate that the proposed PDM technique effectively enhances the efficiency of the HF inverter while significantly reducing output current ripples, power dissipation and improving the overall WPT system efficiency to 92%, and leading to a reduction in the power loss in the range of 10% to 20%. This leads to improved overall system control and performance.

1. Introduction

The world’s energy use, which mostly comes from fossil fuels, is going up at the same time as when more green energy sources are being used. Making the use of electric vehicles and other environmentally friendly options a top goal is important for lowering our reliance on fossil fuels and repairing the damage they have caused [1,2]. Electric vehicles have been developed as a possible good alternative to standard vehicles with internal combustion engines as the world moves towards more sustainable energy solutions in the transportation sector [3,4]. Quick and easy charging options are very important for promoting the widespread use of EVs [5,6]. The utilization of WPT technology has garnered considerable attention as a feasible resolution that offers the extra advantage of cordless charging while still ensuring optimal levels of efficiency and security [7,8]. The wireless power transfer transmission state facilitates the flow of electrical energy from the power supply to the load without the need for direct electrical contact. The power conversion in the WPT system is achieved by the mutual induction of coils through a magnetic field. The interconnected pairs of inductor coils demonstrate high-frequency resonance [9,10].

The power output can vary from milliwatts to megawatts, the working frequency can range from kilohertz to megahertz, and the distance between the coils for air separation can range from several meters to a few millimeters [11,12]. There have been big improvements to the WPT method over the last ten years because it is safe and easy to use [13,14]. In contrast to wired power transmission, this method avoids problems like wire friction and wear and tear. In addition to being safe and easy to use, WPT can be used in biomedical systems, information networks, consumer electronics, and electric vehicles [15,16]. A wireless charging system could help people who are worried about their EV’s range and encourage more people to buy EVs. A lot of problems with wires and charging dangers can be fixed with WPT technology. WPT-enabled electric vehicles will improve range while decreasing battery capacity because they can be charged while the vehicle is static or moving [17,18]. Since the WPT system does not involve touching, there is a clear separation between the cause and the burden. This feature can also make automated charging easier by removing the need for human input.

The workflow block diagram of a WPT charger for EVs is shown in Figure 1. In this system, a high-frequency inverter converts the pulsated direct current into a high-frequency alternating current [19,20], which is wirelessly delivered to the vehicle’s receiver unit, powering the electric vehicle’s battery through the WPT coil. The system does not require physical connections and relies on the efficient transfer of electrical power from a fixed charger to an EV. The WPT system also looks good, are safe in bad weather, and supports high-power levels for fast chargers [21,22], which cuts down on the time it takes to charge a battery.

The research on a wireless power transfer system for the EV charger focuses on developing innovative HF inverter structures [23], compensation strategies [24], coil configurations [25], control algorithms [26], and shielding methods [27]. The most direct approach to controlling the power flow is adjusting the voltage of the inverter on the primary side and including a power switch with a high-frequency control, which makes inactive parts smaller but increases switching losses. Pulse Width Modulation (PWM) techniques play a crucial role in reducing switching losses in WPT, enabling efficient energy transmission over different distances. By managing proper dead times to prevent current overlap, using soft switching techniques like ZVS/ZCS, and adjusting the duration of pulses dynamically, the optimal power delivery, while maintaining resonance in the WPT system, is ensured [28]. PDM is a digital modulation technique that produces more accurate analog signals by varying the density of pulses within fixed time intervals, while ensuring high-fidelity representation of signal amplitudes and minimizing unwanted noise compared to PWM. It is commonly used in high-frequency inverters for precise control of power delivery in applications like the WPT EV charger and motor control [29,30].

Integrating PWM control into FPGA hardware for a wireless power transfer system for an EV charger provides accurate modulation and fast processing, which are crucial for effective and dependable power transmission. This technology offers the versatility to dynamically alter settings, guaranteeing superior performance in comparison to conventional solutions based on microcontrollers [31].

However, the complex features of implementing it at the system and device levels, including dead time, have not been fully investigated. The investigation of the dead-time phenomenon is very necessary in grid-connected inverters. An essential determinant of the WPT system performance is the dead time of the inverter [32]. During the dead time in a voltage source inverter phase leg, both the upper and lower side switches are turned off, allowing the current to freewheel through the diodes [33]. However, such a blanking period can affect the reflexibility, power quality, and losses of the system. The inverter delay time refers to the duration between a control signal being applied to the inverter and the commencement of power transmission [34]. This delay can vary due to several factors, including control algorithms, switching frequencies, and inherent system dynamics [35].

In a high-frequency WPT system, the ratio of the dead time to the operational period becomes more prominent. The DT impact leads to problems such as voltage distortion, current ripples, phase errors, harmonic production, and a decline in control performance. The failure to adequately manage dead-time issues can lead to waveform distortions [36]. The fluctuations in the voltage output of the inverter are commonly known as Voltage Polarity Reversal (VPR) or notch [37,38]. A wireless power transfer system requires efficient dead-time management to optimize efficiency and minimize power losses. Dynamic algorithms can adjust switching intervals to balance losses and currents, ensuring reliable and efficient wireless power transmission. This task requires analyzing switching events and adjusting parameters to improve system reliability. A detailed theoretical examination of isolated bidirectional converters and VPR is available [39]. In [40], switch commutations in the series resonant converter and VPR mitigation are explored. Reference [41] examines how dead time affects wireless power transfer Dual Active Bridge (DAB) configurations and provides a control approach to eradicate them. Dead-time effects on WPT inverters are examined in reference [42], focusing on switching losses.

The inverter delay time, a critical aspect of the system, impacts performance metrics, including power transfer efficiency, power quality, voltage, and current harmonics. It is important to note that this delay affects not only the system’s efficiency but also its overall safety and compliance with electromagnetic interference (EMI) standards [43]. To design a WPT charger for an electric vehicle with dead-time management, it is necessary to consider several standards such as SAE J2954 [44], IEEE 2030.1.1, IEC 61980, and ISO 15118 [45] These standards ensure safety, efficiency, and interoperability, while also adhering to local regulations for electrical safety, electromagnetic compatibility, and energy efficiency. After identifying challenges with Pulse Width Modulation in achieving soft-switching at light loads, Pulse Density Modulation emerged as a solution. PWM faces difficulty due to narrowing pulse widths at light loads, leading to potential hard-switching issues. In contrast, PDM adjusts output voltage by varying pulse density within a fixed control period, without altering pulse width. To mitigate risks associated with simultaneous switching, the following novel techniques are proposed for PDM implementation in HF inverters for WPT EV chargers:

• Insertion of dead time in the PDM control technique for HF inverters in WPT EV chargers.
• Effect of dead time in PDM is analyzed; variation in dead time leads to a reduction in the current ripple.
• Dead time and pulse redistribution to reduce current fluctuations, promoting efficient output voltage regulation and enabling zero voltage switching operation in inverters.

This paper analyses the performance of a wireless power transfer system for EV charging, focusing on the high-frequency inverter delay time in the PDM control technique. The study uses experimental procedures, data acquisition, and analysis to assess the impact of inverter delay time on system performance over the PWM control. Section 2 of the paper delves into the detailed analysis of dead-time effects in switching characteristics, particularly within the context of PDM implementation. It explores how dead time influences the performance of fundamental components in LCC-LCL WPT resonant networks, providing comprehensive modeling and calculation insights from Section 3. In Section 4, the study implements these findings through MATLAB 2023a simulations, ensuring the accuracy and reliability of the results. These simulations are further validated using FPGA-based hardware implementation, comparing and contrasting the outcomes obtained from both approaches in Section 5. Finally, Section 6 synthesizes the conclusions drawn from the simulation and hardware experiments, offering insights into the practical implications and potential applications of the study’s findings.

2. Switching Characteristics of a WPT HF Inverter

The SS, SP, PS, and PP topologies in the WPT system have varying complexity, resonance behavior, and efficiency. The DS-LCC and DS-LCL configurations offer design flexibility but may increase complexity. The LCC-LCL topology combines LCC and LCL advantages, offering robust resonance characteristics, efficient power transfer, and reduced load sensitivity. It is preferred for its balanced performance and flexibility in WPT applications. The LCC-LCL WPT system is used for DT analysis. The circuit of the LCC-LCL WPT structure is given in Figure 2.

The LCC-LCL topology consists of few resonant devices; L_1t, C_t1, C_t2 and L_r, C_r are the primary and secondary compensation parameters. V_idc and I_idc represent the DC input voltage and current on the primary side, while V_ldc and I_idc denote the DC output voltage and current on the secondary side across the load R_L. L₁ and L₂ are the self-inductances of the transmitting and receiving coils, respectively, with M being the mutual inductance between them. S₁–S₄ are the MOSFETs, D₁–D₄ are the body diodes, and D₅ to D₈ are the receiver side bridge rectifier diodes. The primary and secondary HF inverter voltages and currents are denoted as U_1xy, U_2pq, i₁, and i₂ respectively. The LCC-LCL compensation inductances and capacitors, and the dc load, are assumed to be purely resistive. The conventional WPT system illustration transforms into a Z_r equivalent circuit, featuring MOSFET switches (S₁–S₄) of the full-bridge inverter, connected across phase legs, as shown in Figure 3.

There are several common control approaches used on full-bridge inverters, such as PWM and PDM, which are essential control methods in the WPT system for the efficient delivery of power and the management of inverters. PWM regulates the amplitude of the output voltage by adjusting the breadth of pulses within a fixed-frequency waveform. This method is extensively used due to its simplicity and efficacy in regulating power levels and maintaining resonance in WPT applications. PDM, in contrast, modulates the density or distribution of pulses within a fixed time period, providing a higher degree of resolution and the potential for lower switching losses than PWM. PDM is advantageous in situations that necessitate precise control over power delivery while simultaneously minimizing electromagnetic interference. PWM and PDM techniques are both instrumental in the optimization of efficiency and performance in the WPT system, thereby addressing a wide range of operational challenges and application requirements.

2.1. Pulse Density Modulation

The gate pulse waveforms for PWM and PDM are illustrated in Figure 4a without dead time and Figure 4b with dead time inserted. The output voltage is regulated by PWM, which maintains a consistent frequency by adjusting the pulse breadth. In order to attain the intended voltage levels, this modulation technique modifies the duty cycle. Conversely, PDM regulates its RMS output voltage by selectively omitting specific pulses in accordance with a predetermined control sequence, rather than by modifying pulse breadth. By applying the magnitude density (D) balance principle, it is possible to determine the RMS value of the fundamental component of U_1xy.

$$U_{1xy}={\displaystyle \frac{2\sqrt{2}}{\pi }}D{V}_{idc},$$

(1)

It is crucial to guarantee that the pulses in PDM are uniformly distributed in order to reduce power fluctuations within the system. This requirement implies that PDM cannot be accomplished by solely eliminating pulses from the original sequence. Figure 5 illustrates a PDM logic circuit that consists of a hardware-based dead-time integrated logic-based pulse generator. The trigger pulse signal with a frequency of f_sw and a specified pulse density of D is one of the input signals to this system. The pulse generator generates two reference pulses, U_xref and U_yref, by operating at a frequency that is twice the switching frequency f_sw. Following their passage through the dead-time generator, these pulses are transformed into two pairs of complementary driving signals, each of which includes a dead-time constant (t_d).

The average power transfer of the WPT system with PDM can be regulated by adjusting D and t_d, according to

$$\mathrm{P}={\displaystyle \frac{2\sqrt{2}}{\pi }}(D\times {\displaystyle \frac{td}{T}})V_{idc}\left|I_{idc}\right|\cos \phi ,$$

(2)

In the WPT system, using PDM, current and power fluctuations occur due to skipped pulses. However, applying PWM reduces sending voltage perturbations by half. This is achieved by doubling the accumulator’s trigger frequency, accounting for both the rising and falling edges of the input pulse. Understanding the impact of dead time is crucial for analyzing the characteristics of switching with and without it. The effects of dead time on output voltage and currents will be discussed in the next section.

2.2. Characteristics of Switching with Zero Dead-Time

The operation of the switching characteristics using the equivalent circuit shown in Figure 3, with an inverter with zero dead time, is given in Figure 6. While this is not feasible in practice, it provides a foundation for further analysis. In Figure 6a, the waveform G_i represents the gate pulses of the MOSFET switches S₁ to S₄. U_xo and U_yo represent the voltages at the poles of the inverter phase legs, while U_xy represents the square-wave voltage across the inverter phase legs. The red dashed sine wave U_xy is the primary element of the inverter’s output voltage. The blue sine wave ixy represents the sinusoidal current flowing through the load impedance, with the phase angle (ϕ) between the basic voltage component and the sinusoidal current.

Figure 6b represents the current flow path (red dashed line) according to the switch transition states of operation of the high-frequency inverter, as explained in

Table 1. Switch transition table for without dead time.

Transition State	Switch Condition	Current Flow	Output Voltage
State 1 (t0–t1)	S1, S4-ON & S2, S3-OFF	(+) Vidc-S1-Loadx-Loady-S4-(−) Vidc	Uxy = +Vidc.
State 2 (t1–t2)	S1, S4-OFF & S2, S3-OFF	(+) Vidc-S3-Loady-Loadx-S2-(−) Vidc	Uxy = −Vidc.

with the current flow direction and the output voltage.

2.3. Characteristics of Switching with Dead Time

The DT is the period among the swapping events of complementary MOSFETs in an inverter leg. During this interval, both MOSFETs are OFF, and the current flows through their body diodes. If the current reverses during the dead time, the pole voltages also reverse, causing a notch in the inverter output that adversely affects the system’s output voltage. It has been determined that notches in the inverter output can be avoided by satisfying the notch equation defined by Equation (3).

$$|{\theta }_v-\varphi |\ge {\displaystyle \frac{{\delta }_{t_d}}{2}},$$

(3)

The angle θ_v represents the difference between the square wave voltage and its fundamental component. It is calculated as θ_v = α/2 using the standard phase-shift control technique, where α is the phase-shift angle between the inverter phase legs. The symbol δ_td represents the angle of dead time, as defined by

$${\delta }_{t_d}=2\pi \times f_{sw}\times t_d,$$

(4)

t_d is the dead time in seconds and f_sw is the switching frequency in Hz. Please note that the phase-shift angle (α) and phase angle (ϕ) are assumed to be ≥0, and the phase-shift control between the inverter legs is defined to result in a full duty cycle at the output at 0° phase shift and zero duty cycle at 180° phase shift. The WPT system aims to maintain the desired output voltage/current levels; hence, ϕ and α operating conditions were chosen to study the notch behavior. The corresponding switching characteristics with the dead time and the generation of a signal will be explained in switch transition states, as shown in Figure 7.

Figure 7a represents the gate pulses, leg voltages, output voltages, and current wave forms. In Figure 7a, the switch transition states of operation of the high-frequency inverter are explained as the current flow path (red dashed line) direction and the output voltage according to

Table 2. Switch transition table for with dead time.

Transition State	Switch Condition	Current Flow	Output Voltage
State 1 (t0–t1)	S1, S2, S3, S4-OFF	(−) Vidc-D2-Loadx-Loady-D3-(+) Vidc	Uxy = −Vidc.
State 2 (t1–t2)	S1, S4-ON & S2, S3-OFF	(+) Vidc-S1-Loadx-Loady-S4-(−) Vidc	Uxy = +Vidc.
State 3 (t2–t3)	S1, S2, S3, S4-OFF	(−) Vidc-D2-Loadx-Loady-D3-(+) Vidc	Uxy = −Vidc.
State 4 (t3–t4)	S1, S2, S3, S4-OFF	(−) Vidc-D4-Loady-Loadx-D1-(+) Vidc	Uxy = +Vidc.
State 5 (t4–t5)	S1, S4-OFF & S2, S3-ON	(+) Vidc-S3-Loady-Loadx-S2-(−) Vidc	Uxy = −Vidc.
State 6 (t5–t6)	S1, S2, S3, S4-OFF	(−) Vidc-D4-Loady-Loadx-D1-(+) Vidc	Uxy = +Vidc.

.

Dead time in two-phase inverters with MOSFET’s is crucial for efficient operation and generating distortion in output waveform. However, it can introduce challenges in high efficiency and power transfer, as deviations from rectangular pulses affect effective energy transfer. The next section addresses the impact of dead time in fundamental parameters and modeling of the resonant network.

3. Effects of Dead Time on the Fundamental Components

From the previous section, WPT system’s switching states are caused by the current flow direction changes during dead time. These alterations cause MOSFET body diodes to conduct, causing unwanted inverter output switching. When the current polarity changes during dead time, the pole voltages change, disrupting the inverter output’s volt-second integral. This affects the square-wave voltage’s basic element and harmonic dispersion.

3.1. Theoretical Derivation of the HF Inverter Output Voltage in WPT

This section describes the mathematical equations for the inverter waveform with the notch and evaluates its impact on the fundamental component and harmonics. A traditional HF inverter output voltage and current waveform with notch is given in Figure 8.

The output voltage of the inverter is expressed as a Fourier series form:

$$U_{xy}=x_0+\sum _{n=1}^{\mathrm{\infty }}\left(x_n\cos n\omega t+y_n\sin n\omega t\right)$$

(5)

The Fourier coefficient, x₀ = 0, x_n = 0 (for all even values of n,), and y_n are estimated as follows due to the waveform’s half-wave and odd symmetry:

$$y_n={\displaystyle \frac{1}{\pi }}{\int }_0^{2\pi }{f}_{\left(x\right)}\sin n\omega t d\omega t,$$

(6)

Here, f(x) is the periodic function (wave form U_xy) represented in Figure 8. By solving (5), the following equation is given:

$$\begin{gathered} y_n={\displaystyle \frac{V_{idc}}{n\pi }}[2\cos \left(n{\delta }_1\right)+\cos \left(n{\delta }_2\right)+\cos \left(n{\delta }_3\right)-\cos \left(n{\delta }_4\right)-\cos \left(n{\delta }_5\right)+ \\ 2\cos \left(n{\delta }_6\right)-\cos \left(n{\delta }_7\right)-\cos \left(n{\delta }_8\right)+\cos \left(n{\delta }_9\right)+\cos \left(n{\delta }_{10}\right)], \end{gathered}$$

(7)

The angle δ_i is determined by the operating circumstances of phase angle (ϕ), phase shift (α), and dead-time angle (δ_td). In Figure 8, the notch appears twice in the square waveform half-cycle.

$$\begin{gathered} U_{{xy}_n}={\displaystyle \frac{y_n}{\sqrt{2}}}={\displaystyle \frac{V_{idc}}{\sqrt{2}n\pi }}[-2\cos \left(n{\delta }_1\right)+\cos \left(n{\delta }_2\right)+\cos \left(n{\delta }_3\right)-\cos \left(n{\delta }_4\right)- \\ \cos \left(n{\delta }_5\right)+2\cos \left(n{\delta }_6\right)-\cos \left(n{\delta }_7\right)-\cos \left(n{\delta }_8\right)+\cos \left(n{\delta }_9\right)+\cos \left(n{\delta }_{10}\right)], \end{gathered}$$

(8)

$$U_{{xy}_n}={\displaystyle \frac{V_{\mathrm{i}\mathrm{d}\mathrm{c}}}{\sqrt{2}n\pi }}{c}_{{\delta }_i}$$

(9)

The above mathematical expressions are used to find the output parameters for the load-connected HF inverter leg equivalent circuit shown in Figure 3. By using Equations (8) and (9), we can analyze how dead time affects the fundamental output voltage and its harmonics in a HF inverter used for WPT. This analysis considers both PDM and PWM controls. Figure 9a,b show that the theoretical predictions match the actual results quite well. Specifically, Figure 9b demonstrates how varying dead time impacts the fundamental component of the HF inverter voltage in an LCC-LCL resonant circuit. The results indicate that the fundamental component values change depending on the different density and dead time used in both PDM and PWM control methods. The loss of inverter at 0.8 density PDM is ~6.0% for a DT of 1 μs, as shown in Figure 9b. Inverter duty cycle loss is approximately 8% at 85 kHz operating frequency with the same DT value. As the working frequency increases, the fundamental component of the inverter decreases, causing the DT effect. According to the harmonic order, for the given operating condition, the inverter output notch raises the voltage, which decreases the higher-order harmonics and lowers the lower-order harmonics. Moreover, it is evident from comparing Figure 9a,b that changing the density of PDM of the inverter can regulate its harmonic content. The resonant network suppresses higher order harmonics by allowing just the inverter’s fundamental component to couple with the secondary.

However, inverter square-wave harmonic content may increase MOSFET switch switching losses and thermal pressures. Should the voltage/current strains brought on by the notch surpass the acceptable bounds, the MOSFET switch could sustain irreversible damage. In the forthcoming section, we will delve into the essential considerations of selecting the resonance compensation network and accurately calculating its parameters, taking into account the significant influence of dead time. Furthermore, the overall system efficiency will be impacted by the rise in the switching losses. The loss of essential component affects the features of the WPT system as well as this, and will be covered in the next section.

3.2. Modeling of Resonance Compensation Network for WPT

From Figure 2, selecting the compensation topology and deriving the value of the components for the LCC-LCL WPT system can achieve high efficiency and reliable power transfer, even when considering the effects of dead time in PDM. The LCC-LCL topology is a hybrid resonant converter that combines series and parallel resonance strengths. It consists of an LCC network and an LCL network, creating a robust resonant tank for efficient power transfer and improved voltage regulation. The LCC stage shapes the resonant frequency and control voltage, reducing switching losses and electromagnetic interference. The LCL stage refines power delivery, ensuring minimal harmonic distortion and improved load regulation. Figure 10 reflects the equivalent circuit of a magnetic resonance WPT EV charger with LCC-LCL compensation networks.

The primary inductor (L₁), resonant inductors (L_t), and capacitors (C_t1 and C_t2) form the resonant tank circuit on the transmitter side, generating the high-frequency AC signal. The mutual inductance (L_M) between L₁ and the equivalent secondary inductor (L_2e) enables energy transfer. On the receiver side, the capacitor (C_re), inductor (L_re), and load resistance (R_Le) form the resonant circuit that captures and converts the transmitted power. The input voltage (U₁) drives the circuit, creating an input current (I_xy) that induces a magnetic field in L_t, coupling to L_2e. The load current (I_L) and voltage (V_Ldc) are delivered to R_Le, representing the transferred power. Proper component selection and tuning achieve high efficiency and reliable power transfer, accounting for the dead-time effects in PDM.

The mutual inductance represents the coupling between the primary and secondary coils in a WPT system. The value of mutual inductance depends on the geometry of the coils, their distance, and their orientation. The mutual inductance (L_M) between two coils can be expressed as

$$L_M=k\sqrt{L_1{L}_2},$$

(10)

where k is the coupling coefficient (ranges from 0 to 1, with 1 being perfect coupling). The coupling coefficient (k) is defined as

$$k={\displaystyle \frac{L_M}{\sqrt{L_1{L}_2}}},$$

(11)

In a static wireless EV charging system, parallel compensation involves capacitors across the stator coil terminals. These compensation capacitors are carefully placed in series and parallel on the transmitter and receiver. Source compensation aims to remove the current–voltage phase mismatches, output current ripples, and reduce the reactive power drawn from the source. In the WPT system, the primary and secondary resonant frequencies are identical. The resonant frequency for the primary side LCC network (L_t, C_t1, and C_t2) can be found using the series and parallel combinations of the inductors and capacitors. For a series–parallel combination,

$${\displaystyle \frac{1}{{⍵}_{r1}^2}}=L_t(C_{t1}+C_{t2}),$$

(12)

$${⍵}_{r1}={\displaystyle \frac{1}{\sqrt{L_t(C_{t1}+C_{t2})}}}$$

(13)

The primary side resonant frequency (f_r1) is

$$f_{r1}={\displaystyle \frac{{⍵}_{r1}}{2\pi }}={\displaystyle \frac{1}{2\pi \sqrt{L_t\left(C_{t1}+C_{t2}\right)}}},$$

(14)

The resonant frequency for the secondary side LCL network (L_2e, C_re, L_re) can be found using the series and parallel combinations of the inductors and capacitors. For a series–parallel combination,

$${\displaystyle \frac{1}{{⍵}_{r2}^2}}=L_{2e}(C_{re}+{\displaystyle \frac{L_{re}}{L_{re}+L_{2e}}})$$

(15)

$${⍵}_{r2}={\displaystyle \frac{1}{\sqrt{L_{2e}(C_{re}+\frac{L_{re}}{L_{re}+L_{2e}})}}}$$

(16)

The secondary side resonant frequency (f_r2) is

$$f_{r2}={\displaystyle \frac{{⍵}_{r2}}{2\pi }}={\displaystyle \frac{1}{2\pi \sqrt{L_{2e}(C_{re}+\frac{L_{re}}{L_{re}+L_{2e}})}}}$$

(17)

In order to eliminate the reactance in Equation (15), the secondary tank must resonate at a specific angular frequency (ω₀).

$${\mathrm{⍵}}_0={⍵}_{r1}={⍵}_{r2}={\displaystyle \frac{1}{\sqrt{L_t(C_{t1}+C_{t2})}}}={\displaystyle \frac{1}{\sqrt{L_{2e}(C_{re}+\frac{L_{re}}{L_{re}+L_{2e}})}}}$$

(18)

Dead-time analysis considers the mutually connected state with the first harmonic approximation (FHA). Calculate the RMS primary-side AC voltage from Expression (9) U_1xy, as

$$U_{1\mathrm{x}\mathrm{y}}={\displaystyle \frac{V_{\mathrm{i}\mathrm{d}\mathrm{c}}}{\sqrt{2n\pi }}}{C}_{\delta i},$$

(19)

where C_δi is determined in Section 3.1 and depends on the operating conditions of α and ϕ. The AC voltage and current at the input of the secondary rectifier are described as follows:

$$U_{2\mathrm{p}\mathrm{q}}={\displaystyle \frac{2\sqrt{2}}{\pi }}{V}_{\mathrm{l}\mathrm{d}\mathrm{c}},$$

(20)

$$i_2={\displaystyle \frac{\pi }{2\sqrt{2}}}{I}_{\mathrm{l}\mathrm{d}\mathrm{c}}$$

(21)

U_2pq and i₂ are the AC voltage at the input to secondary rectifier and the current streaming through the receiver coil. The equivalent load resistance at the input of the diode rectifier is written as

$$R_{Le}={\displaystyle \frac{8R_L{L}_t}{{\pi }^2{L}_r}},$$

(22)

$$L_{t1}=L_{t1}(1-k)$$

(23)

$$L_m={kL}_{t1}$$

(24)

$$L_{2e}=L_t$$

(25)

$$C_{re}={\displaystyle \frac{C_{t1}{L}_r}{L_t}}$$

(26)

$$L_{re}={\displaystyle \frac{L_{r1}{L}_{t1}}{L_r}}$$

(27)

From the above Expression (18), the design value for the inductor L_t1 capacitors C_t1 and C_t2 in the primary resonant network is

$$L_{t1}={\displaystyle \frac{2\sqrt{2}}{\pi }}\times {\displaystyle \frac{V_{ldc}}{{⍵}_0^2{I}_{Rload}}}\times {\displaystyle \frac{L_r}{L_t}},$$

(28)

$$C_{t1}={\displaystyle \frac{1}{{⍵}_0^2{L}_{t1}}}+{\displaystyle \frac{1}{{⍵}_0^2\left(\right(1-k\left)L_t\right)}}$$

(29)

$$C_{t2}={\displaystyle \frac{1}{{⍵}_0^2(L_t-L_{t1})}}$$

(30)

The transmitter side impedance of the WPT is expressed as

$$Z_{\mathrm{t}}={j\omega L}_{\mathrm{t}}+\left({\displaystyle \frac{1}{j\omega C_{\mathrm{r}2}}}+j\omega L_1\left|\right|\left({\displaystyle \frac{1}{j\omega C_{\mathrm{t}1}}}\right)\right),$$

(31)

$$Z_{\mathrm{t}}={j\omega L}_{\mathrm{t}}+{\displaystyle \frac{1}{j\omega C_{\mathrm{r}2}}}+{\displaystyle \frac{L_1}{j\omega C_{\mathrm{t}1}}}$$

(32)

The receiver side impedance of the WPT is derived as

$$Z_{\mathrm{s}\mathrm{e}\mathrm{c}}=R_{\mathrm{L}\mathrm{e}}+{j\omega L}_{2\mathrm{e}}+{\displaystyle \frac{1}{{j\omega C}_{\mathrm{r}\mathrm{e}}}}+{j\omega L}_{\mathrm{r}\mathrm{e}}$$

(33)

The receiver side impedance reflected on transmitter side impedance is defined as

$$Z_{\mathrm{r}\mathrm{e}\mathrm{f}\mathrm{l}\mathrm{e}\mathrm{c}\mathrm{t}}={\displaystyle \frac{Z_{sec}}{k^2}}$$

(34)

The total input impedance, when combined with the primary side impedance and the reflected impedance:

$$Z_{\mathrm{i}\mathrm{n}}=Z_t+Z_{\mathrm{r}\mathrm{e}\mathrm{f}\mathrm{l}\mathrm{e}\mathrm{c}\mathrm{t}}$$

(35)

The input impedance Zin seen by the source U1:

$$Z_{\mathrm{i}\mathrm{n}}={j\omega L}_{\mathrm{t}}+{\displaystyle \frac{1}{{j\omega C}_{\mathrm{t}2}}}+{\displaystyle \frac{L_1}{j\omega C_{\mathrm{t}1}}}+{\displaystyle \frac{Z_{sec}}{k^2}}$$

(36)

The load impedance:

$$Z_{\mathrm{l}\mathrm{o}\mathrm{a}\mathrm{d}}=Z_{sec}$$

(37)

$$Z_{\mathrm{l}\mathrm{o}\mathrm{a}\mathrm{d}}=R_{\mathrm{L}\mathrm{e}}+{j\omega L}_{2\mathrm{e}}+{\displaystyle \frac{1}{{j\omega C}_{\mathrm{r}\mathrm{e}}}}+{j\omega L}_{\mathrm{r}\mathrm{e}}$$

(38)

A mesh-based analysis results in

$$U_{1\mathrm{x}\mathrm{y}}=\left({j\omega L}_{\mathrm{t}}+{\displaystyle \frac{1}{{j\omega C}_{\mathrm{t}2}}}+{\displaystyle \frac{L_1}{j\omega C_{\mathrm{t}1}}}+{\displaystyle \frac{Z_{sec}}{k^2}}\right)I_{\mathrm{x}\mathrm{y}}$$

(39)

$$U_{2\mathrm{p}\mathrm{q}}=-\left(R_{\mathrm{L}\mathrm{e}}+{j\omega L}_{2\mathrm{e}}+{\displaystyle \frac{1}{{j\omega C}_{\mathrm{r}\mathrm{e}}}}+{j\omega L}_{\mathrm{r}\mathrm{e}}\right)I_2$$

(40)

The overall WPT efficiency:

$$\mathsf{\eta }={\displaystyle \frac{P_L}{P_{in}}}={\displaystyle \frac{I_L^2{R}_{Le}}{U_1{I}_{xy}\cos \phi }}$$

(41)

The transconductance gain:

$$G_m={\displaystyle \frac{I_{ldc}}{U_{1xy}}}={\displaystyle \frac{{j\omega L}_M}{Z_{in}{Z}_{sec}}}$$

(42)

The voltage gain:

$$G_v={\displaystyle \frac{V_{Ldc}}{U_{1xy}}}={\displaystyle \frac{{j\omega L}_M{R}_{Le}}{Z_{in}{Z}_{sec}}}$$

(43)

The current gain:

$$G_i={\displaystyle \frac{I_{Ldc}}{I_{xy}}}={\displaystyle \frac{{j\omega L}_M}{Z_{sec}}}$$

(44)

I_L is the load current and V_ldc is the load voltage. Using Equations (21)–(28), the parameters for the LCC-LCL resonant compensation network are calculated and shown in

Table 3. LCC-LCL resonant compensation design parameters values.

Symbol	Designed Value
Lt	74.56 µH
Ct1	5.05 nF
Ct2	6.26 nF
Lr	36.3 µH
Cr	10.05 nF

. These parameters are used in the subsequent simulation and experiment, as illustrated in Figure 3. A detailed analysis of these findings is provided in Section 4.

4. Dead-Time Effects in WPT System via Simulation and Experimental

The behavior of dead time involved in the PDM-based controlled LCC-LCL WPT system is designed and simulated in MATLAB/Simulink 2023a software as per the schematic circuit diagram given in Figure 2. For the simulation design, the compensation network values were referred from Table 3 and WPT design values were referred from

Table 4. Design parameters values of WPT.

Parameter	Label	Value
Input DC voltage Primary coil	Vidc	325 V
Transmitter coil self-Inductance	L1	74.56 µH
Mutual inductance	LM	15.95 µH
Receiver coil self-inductance	L2	85.45 µH
Output equivalent resistance	Rload	22 Ω
Output filter capacitance	Co	22 µF
Operating switching frequency	fsw	85,000 Hz
Coupling coefficient	k	0.2
Distance between transmitter to receiver coil	d	180 mm

. The theoretical model is verified through simulations, and the output parameters are validated through the WPT prototype experimental setup shown in Figure 11 using the parameters values given in Table 4. The WPT system is made up of ONSEMI NTHL080N120SC1 SiC 1200 V/35 A MOSFET, and full-bridge arrangement modules are driven by Texas Instruments (Dallas, TX, USA) UCC27531A gate-drivers (Fall Time 7 ns, Rise Time 15 ns, Turn-Off and ON delay time 17 ns). Selecting an appropriate dead time as a percentage of the switching period (T) helps standardize its selection across different frequencies. For low-frequency applications (20 kHz–100 kHz), the dead time typically ranges from 1% to 15% of T. In medium-frequency applications (100 kHz–500 kHz), the dead time usually falls between 1% and 25% of T. For high-frequency applications (500 kHz–1 MHz), the dead time generally ranges from 5% to 20% of T. To ensure safe operation of the MOSFET inverter at a switching frequency of 85 kHz, the chosen dead time values of 0.5 μs, 1.0 μs, 1.5 μs, and 2.0 μs should be selected based on these percentages. In order to supply the full-bridge inverter, gate pulses from a Spartan-6 FPGA control board are utilized. The analysis shows how the dead time affects system sensitivity under a constant operating frequency of 85 KHz, with a resistive load of 22 Ω and different PDM density level of (D = 0.2, 0.5, 0.8), assuming the unity power factor.

The LCC-LCL topology is the where the main capacitor’s correct value is not affected by the load impedance. The fact that C_o is dependent on R_L makes it hard to use in real life. There is a link between the secondary capacitor and the monoresonant compensation network that changes how the system works. The primary-side and secondary-side LCC-LCL compensation parameters were assembled with Celem Power Capacitors CSP 120/200 conduction-cooled capacitors according to the intended values in Table 3. The secondary side rectifier uses 600 V/100 A APT2X101DQ60 J (Mouser Electronics, Mansfield, TX, USA) ultrafast phase-leg rectifiers.

5. Analysis of Simulation and Experimental Results

The design optimization and efficiency predictions are facilitated by the powerful instrument of MATLAB simulation, which is capable of modeling and evaluating the performance of WPT EV chargers. The subsequent step in the hardware results analysis is to test the tangible WPT charger to ensure that it complies with the design specifications and functions efficiently in real-world charging scenarios.

5.1. Simulation Results and Discussions

The MATLAB simulation results are discussed in this section as graphical representation. Figure 12 illustrates the effect of various dead-time values (500 ms, 1000 ms, 1500 ms, and 2000 ms) of the switching gate pulses for the WPT HF inverter and the corresponding output voltage and current waveforms. As the dead time increases, the inverter’s output characteristics decreases, demonstrating variations in the voltage and current profiles. The focus is on the dead-time impact with constant operating frequency, mutual inductance, and load. When comparing the theoretical analysis from Figure 9 and the simulated results, the fundamental output voltages of the HF inverter for WPT shows 3% to 5% minimal variation for the different harmonics order.

The simulation results of the input gate pulses with different dead time values, output voltages, and current wave forms of HF inverter WPT with PDM (D = 0.2) control are given in Figure 13.

The HF inverter WPT simulation results of input gate pulses with different dead time values, output voltages, and current wave forms for PDM (D = 0.5) control are given in Figure 14.

Figure 13, Figure 14 and Figure 15 shows how the dead-time intervals affect the WPT system HF inverter PDM switching gate pulses at different densities (D) 0.2, 0.5, and 0.8; output voltage; and current waveforms. The top-row sub-diagrams display HF inverter switching gate pulses with 500 ms, 1000 ms, 1500 ms, and 2000 ms dead-time settings. Shoot-through is prevented by widening the spacing between complimentary MOSFET switching occurrences as dead time grows. The central diagram shows the HF inverter output voltage (magenta) and current (orange) over time, with arrows showing precise moments corresponding to detailed waveforms in the bottom row. The bottom-row insight show a single cycle of HF inverter output voltage and current waveforms with notch when dead time is inserted. The waveforms show the trade-off between shoot-through and waveform integrity and efficiency. The probability of waveform aberrations and shoot-through is shown without dead-time. Intermediate dead times (0.5 µs to 1.0 µs) minimize risk and maintain waveform quality. However, excessive dead-time (1.5 µs to 2.0 µs) might cause notching and inefficiency. From the simulation results, the inverter voltage, current, input DC power, output AC power, transmitter and receiver coil power, and output dc load power are observed, and the current ripples are calculated for different dead-time values and PDM density levels. This analysis shows how dead-time intervals affect HF inverter switching and output in a WPT system. Using Equations (39)–(41), the parameters are derived and shown graphically below for easy understanding.

Figure 16 illustrates the performance comparison of Pulse Density Modulation at a density of 0.8 and 0.5, along with Pulse Width Modulation at duty cycle 50%, across different metrics, while the dead time increases from 0% to 20% in the 85 kHz WPT system. Comparing Figure 16a–d, we observe that the reduction in the inverter duty cycle due to dead time impacts the DC voltage gain and transconductance gain of the system.

As dead time increases, all input DC voltage gains diminish, as shown Figure 16a. PDM with D = 0.8 has the most gain, while PWM has the lowest. Figure 16b indicates that PDM D = 0.8 initially has a greater input DC current gain, but it drops drastically after a 15% dead period. The PWM has a little current amplification advantage at most dead moments, but the PDM with a density of 0.5 has similar patterns.

All approaches show a drop in input AC voltage gain as dead time increases, as shown in Figure 16c. PDM D = 0.8 consistently yields the highest gain, while PDM D = 0.5 and PWM perform similarly, with PWM slightly outperforming at longer dead times. Figure 16d shows that all techniques enhance transconductance as dead time increases.

PDM D = 0.8 has the highest values, especially for longer dead times, while PWM has the lowest. As dead time rises, the input DC power decreases, as shown in Figure 16e. The PDM D = 0.8 arrangement offers the highest power at shorter dead times but rapidly diminishes after 10%. However, PWM uses the least electricity. As dead time rises, all DC power output loads decrease, as shown Figure 16f. PDM with a duty cycle of 0.8 reduces power by 15% of the dead time, while PWM has the lowest power.

Dead time is negatively correlated with transmitter AC power, as shown in Figure 16g. It shows that PDM D = 0.8 produces the maximum power, especially at lower dead times, while PWM produces the least. As dead time increases, the receiver AC power drops, as shown in Figure 16h. PDM D = 0.8 has the highest power for most dead periods, while PWM has the lowest. PDM with D = 0.8 often preserves better gains and power levels than PDM with D = 0.5 and Pulse Width Modulation. PWM performs the worst in several metrics as dead time increases.

Higher dead-time hurts all performance indicators; however, the degree depends on modulation methods. From the above graphical analysis, the impact of dead time in the WPT EV charger performance parameters are calculated and tabulated for PMW and PDM control, as shown in

Table 5. Performance parameters values of WPT.

Parameters	Control Technique	Without Dead Time	Dead Time in (%)
			1	5	10	15	20
Power dissipation	PWM	0.400	0.955	1.145	1.395	1.500	1.555
	PDM (D = 0.5)	0.342	0.481	1.130	1.365	1.425	1.470
	PDM (D = 0.8)	0.300	0.700	1.245	1.220	1.325	1.540
Transfer efficiency	PWM	86.1%	84.3%	89.7%	93.8%	95.5%	96.8%
	PDM (D = 0.5)	86.7%	84.4%	89.2%	92.7%	94.1%	98.4%
	PDM (D = 0.8)	80.7%	81.3%	82.2%	82.8%	84.2%	84.4%
Overall efficiency	PWM	88.4%	85.5%	62.2%	50.8%	46.4%	30.3%
	PDM (D = 0.5)	90.2%	88.3%	63.6%	55.8%	52.3%	37.6%
	PDM (D = 0.8)	92.2%	89.4%	66.3%	64.2%	61.1%	50.4%
Color scale		Lowest	-	-	-	-	Highest

.

Table 5 presents a comparison of the performance of the Pulse Width Modulation and Pulse Density Modulation control approaches for the WPT HF inverter. The comparison is performed for PDM densities of 0.5 and 0.8 both with and without dead time. It demonstrates that PDM typically leads to reduced power dissipation and increased transfer efficiency in comparison to the PWM control technique. Furthermore, PDM demonstrates superior efficiency compared to PWM as dead time increases, emphasizing its ability to minimize power loss and enhance performance.

5.2. Expermental Results and Discussions

Figure 17a illustrates the voltage and current waveforms of a HF inverter used in WPT, showing smooth voltage transitions and a current waveform with a noticeable ripple. Figure 17b displays the PWM control signals, highlighting the gate pulses and the resulting inverter current waveform.

Figure 18 illustrates notch occurrence when the voltage is predominantly increasing in width, when the dead time increases, and when a current waveform has decreasing ripples.

Figure 19 consists of (a), (c), (e), and represents the inverter output voltage and current for different PDM densities of 0.2, 0.5, and 0.8. As shown in Figure 19b,d,f, each result illustrates the high-frequency inverter switching gate pulses with the respective densities (D = 0.2, 0.5, 0.8) without dead time inserted.

From Figure 20, the presence of a PDM of 0.2 results in a noticeable effect of increasing dead time and affects the higher frequency of voltage. The notch width also increases, which causes a substantial amount of harmonic distortion in the output signal.

From Figure 21, the presence of a PDM of 0.5 results in a noticeable effect of increasing dead time and affects the higher frequency of voltage. The notch width also increases, which cause a substantial amount of harmonic distortion in the output signal.

From Figure 22, the presence of a PDM of 0.8 results in a noticeable effect of increasing dead time and affects the higher frequency of voltage. The notch width also increases, which cause a substantial amount of harmonic distortion in the output signal.

The recurring notches and its width increases are observed in Figure 20, Figure 21 and Figure 22. When dead time increases, that leads to temporary conduction through the MOSFET body diodes. These notches, along with the accompanying current waveform fluctuations, illustrate the influence of dead time on the current flow, causing directional changes and transient disruptions. Such disturbances adversely affect the overall performance and efficiency of the WPT system. This underscores the critical need for precise dead-time management to minimize these disruptions and ensure stable, efficient power transfer. Comparing PWM-controlled inverter results with PDM control results, less current ripples are observed. Figure 23 illustrates current ripple variations for PWM and PDM at different dead times from the experimental and simulation output.

It shows that the current ripple decreases as dead time increases for a 50% duty cycle in PWM control. Similarly, it decreases with increasing dead time across all pulse densities, with the most significant reduction observed at lower pulse densities like 20% in PDM control. As dead time increases, the current at the rectifier input reduces from ~18 to ~10 due to parasitic components, as observed in experimental waveforms. The MATLAB analysis aligns well with experimental findings. Additionally, the study compares inverter output voltage harmonics with and without notches at full duty cycle. Notching reduces lower-order harmonics while elevating higher-order harmonics under the specified operating conditions. Harmonic levels are adjustable by varying the inverter phase-angle and duty cycle. However, increased harmonics may escalate switching losses and stress on MOSFET switches, potentially causing permanent damage and impacting overall system efficiency.

Table 6. Performance values comparison of PWM and PDM control techniques in HF inverters of WPT with and without dead time.

Control Technique		HF Inverter Voltage Gain	Current Ripple Ratio	HF Inverter Efficiency
Without dead time	PWM [36]	1.25	2.50	89.5
	PDM [42]	1.30	1.80	90.2
With dead time (1 µs)	PWM	1.06	2.05	86.5
	PDM (0.5)	1.19	1.96	86.7
	PDM (0.8)	1.25	1.95	89.5

compares the performance of PWM and PDM control techniques in HF inverters, highlighting the impact of dead time of 1µs on the voltage gain, current ripple ratio, and efficiency. Notably, PDM with dead time shows a significant improvement in the efficiency and current ripple ratio compared to other configurations. Comparing the results of PDM and PWM implementations reveals that PDM offers better performance in terms of efficiency and stability to the HF WPT inverter for EV charging applications.

Table 6 validates that PDM techniques outperform PWM in HF inverter applications, achieving higher voltage gain and efficiency with lower current ripple ratios compared with other papers in the literature. Additionally, implementing dead time improves overall performance, with PDM (0.8 µs) showing the best results.

6. Conclusions

This work addresses the PDM control technique used in wireless transmission to reduce the impact of and maximize power over the PWM control. The impact of dead time in HF inverters shows the variations in the current direction during VPR occurrence, reducing the inverter output voltage by up to 5%. Notches affected the HF inverter, the fundamental component of the voltage, and impacted the harmonic spectrum but reduced the current ripples by 10%. The prediction of notches in the HF inverter voltage is performed using the notch equation, allowing harmonic control through various combinations of input dead time and pulse density. Dead-time effects can be lessened with the help of compensation topologies such as the LCC-LCL, which also generally enhances system performance, efficiency, and power quality by reducing the current ripples and reducing the power dissipation from 20% to 10% for increasing dead-time values. The study finds that dead time lowers the power delivered to the load, increasing the transconductance gains. A prototype 3.7 kW WPT system with a maximum efficiency of 92% was used to compare the experimental results and validation results with the theoretical expectations. Further, future work will focus on optimizing PDM techniques for investigating an adaptive control strategy to dynamically adjust for varying load conditions and environmental factors with improved dead-time management in WPT EV systems.