# 2 kW Dual-Output Isolated DC/DC Converter Based on Current Doubler and Step-Down Chopper

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## Abstract

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## 1. Introduction

_{2}emissions, which are the cause of global warming, originate from the transportation sector [1]. To reduce such emissions, the automotive industry has introduced motor-driven vehicles such as electric vehicles (EVs), plug-in hybrid vehicles (PHVs), and fuel cell vehicles (FCVs) into the market, the sales of which continue to increase [2]. In September 2020, the state of California announced a plan to ban the sale of new gasoline-driven vehicles in 2035. Accordingly, the sale of motor-driven vehicles is expected to accelerate in the future. Isolated DC/DC converters are used as auxiliary power for these motor-driven vehicles, with the power supply for the motor drive as the input [3,4]. The capacity and power consumption of auxiliary power is expected to increase in the future in response to the electrification of traditionally mechanical functions, such as steering and reclining mechanisms, as well as the increase in comfort-enhancing electrical components such as seat heaters [5,6]. The increased capacity leads to an increase in the conduction loss, and changing the conventional 12 V auxiliary power to 48 V has been proposed to reduce this loss [7,8]. However, as loads that require a 12 V power supply still exist, the mixing of the two load systems, namely 48 and 12 V, continues to be necessary. At present, several methods are available to realize the two systems’ auxiliary power; for example, installing two isolated DC/DC converters with the power supply input for the motor drive or inserting a non-isolated bidirectional DC/DC converter for 48 and 12 V in a 48 V system [9]. However, these methods exhibit problems such as an increased size owing to the installation of two units and reduced efficiency as a result of the two power conversions. To overcome these issues, we propose a novel dual-output isolated DC/DC converter, which includes an integrated circuit of a current doubler and step-down chopper on the secondary side and outputs both 48 V and 12 V [10]. Since the secondary side of the proposed circuit is an integrated circuit and there is no need to convert voltage twice to generate 12 V, the proposed circuit is expected to have a smaller size and higher efficiency although the control method becomes more complex. As our previous studies were based on simulations or a downsized prototype, no actual device testing has yet been performed with power for automotive applications.

## 2. Circuit Configuration and Operation Principle

#### 2.1. Circuit Configuration

_{in}and two output voltages V

_{out1}and V

_{out2}. The input/output isolation is realized by a high-frequency transformer. An H-bridge inverter consisting of S1–S4 is connected on the primary side of the transformer. A current doubler consisting of L11, L12, D1, D2, and C1 (Figure 2a) as well as an interleaved step-down chopper consisting of S5, S6, D1, D2, L21, L22, and C2 (Figure 2b) are connected on the secondary side of the transformer to form an integrated circuit. D1 and D2 are included in both circuits, thereby reducing the number of components. The H-bridge inverter and high-frequency transformer have conventional simple configurations, and the two outputs are achieved solely with the secondary side circuit.

#### 2.2. Operation Principle

_{in}, 0, and −V

_{in}, and these voltages are applied on the primary side of the transformer. This circuit includes six operation modes based on the combination of the transformer secondary side voltage level V

_{txs}, which is transformed according to the turns ratio N1:N2, and the on–off states of S5 and S6.

_{txs}, S5, and S6, as well as the corresponding operation modes. In Table 1, “1”, “0”, or “−1” for V

_{txs}represent a voltage of a positive value, 0, or a negative among the three levels, respectively. Moreover, “-” for S5 and S6 indicates that it is irrelevant whether it is on or off. The reason for this irrelevance is that in these cases, a current flows from the source to the drain in S5 or S6; the current passes through the body diode even in the off state.

_{txs}, the switching states of S5 and S6, the inductor currents on the current doubler side I

_{L11}and I

_{L12}, and the inductor currents on the step-down chopper side I

_{L21}and I

_{L22}.

- The operation of the secondary side circuit in each mode is described below.
- Mode 1: V
_{txs}is positive and S5 is off (Figure 4a).

- L11 is charged by V
_{txs}and L12, L21, and L22 discharge.- Mode 2: V
_{txs}is positive and S5 is on (Figure 4b).

- As S5 is turned on, both L11 and L21 are charged by V
_{txs}, whereas L12 and L22 still discharge.- Mode 3: V
_{txs}is 0 (Figure 4c).

- When V
_{txs}is 0, there is no power, and therefore, L11, L12, L21, and L22 all discharge.- Mode 4: V
_{txs}is negative and S6 is off (Figure 4d).

- L12 is charged by V
_{txs}and L11, L21, and L22 discharge.- Mode 5: V
_{txs}is negative and S6 is on (Figure 4e).

- As S6 is turned on, L12 as well as L22 are charged. L11 and L21 still discharge.
- Mode 6: V
_{txs}is 0 (Figure 4f).

- As in Mode 3, as V
_{txs}is 0, L11, L12, L21, and L22 discharge.

_{out1}and V

_{out2}; the output currents I

_{out1}and I

_{out2}; the output average inductor currents $\overline{{I}_{L11}}$, $\overline{{I}_{L12}}$, $\overline{{I}_{L21}}$, and $\overline{{I}_{L22}}$; the inductor current ripple factors γ

_{L11}, γ

_{L12}, γ

_{L21}, and γ

_{L22}; and the capacitor ripple currents Δi

_{c1}and Δi

_{c2}. In this case, d

_{1}and d

_{2}in the equations are duty ratios for the period in which V

_{txs}is positive or negative and for the period of Mode 2 or Mode 5, respectively, as illustrated in Figure 3. L

_{1}and L

_{2}are the inductance values of L11 or L12 and L21 or L22, respectively. R

_{1}and R

_{2}are the load resistance values of the current doubler and step-down chopper outputs, respectively. Moreover, T is the time of one cycle.

_{in}is constant, V

_{out}

_{1}and V

_{out}

_{2}are only dependent on the duty ratio corresponding to each of these. That is, the switching of S1 to S4 controls V

_{out1}, and that of S5 and S6 controls V

_{out}

_{2}. This means that V

_{out1}and V

_{out2}can be controlled independently; however, this is only possible when the circuit operates with the six operation modes described above. This means that the following condition must be satisfied:

_{1}> d

_{2}.

_{1}≦ d

_{2}), S5 and S6 are always on, while the transformer is transmitting power from the primary side to the secondary side (when V

_{txs}is positive or negative). Consequently, there will be no means of controlling V

_{out2}and the dual-output converter cannot perform its function.

## 3. Actual Device Testing

#### 3.1. Main Circuit Configuration

_{out1}was 48 V, and the output voltage on the step-down chopper side V

_{out2}was 12 V. The switching frequency was 400 kHz, as described previously. For the FPGA to generate control signals, XC7K70T-1FBG484C (Xilinx) with a clock cycle of 5 ns (200 MHz frequency) was used to obtain a sufficient time resolution for switching at 400 kHz (2.5 μs per cycle) to be obtained. A SiC MOSFET SCT3030AL (ROHM) with a short switching transition time was used for S1 to S6 considering the switching loss at 400 kHz. A SiC Schottky barrier diode FFSH4065A (ON Semiconductor) with an extremely short reverse recovery time was used for D1 and D2. Owing to the large current value in the secondary side circuit, S5, S6, D1, and D2 were connected in parallel and a snubber circuit was provided in light of the surge voltage in the off state. The transformer turns ratio was set to 4:2. The inductance values on the current doubler sides L11 and L12 were set to 15 μH, whereas those on the step-down chopper side L21 and L22 were set to 3 μH, considering the relationship among the ripple current amplitude, wire diameter, and core size. The output capacitor on the current doubler side C1 was set to 44 μF by connecting two 22 μF ceramic capacitors in parallel, whereas that on the step-down chopper side C2 was set to 188 μF by connecting four 47 μF ceramic capacitors in parallel. Because the experimental circuit was constructed with the aim of operating at 400 kHz and 2 kW, the selected switching devices as well as the designed transformers and inductors had plenty of room in terms of the breakdown voltage, current capacity, and saturation magnetic flux density.

#### 3.2. Control Circuit Configuration

_{out1}. In particular, the deviation between the divided voltage of V

_{out1}, denoted by V

_{fb1}, and the voltage command value V

_{out1}* was input to the PI calculation unit. Subsequently, the output of the PI calculation unit was compared with the 400 kHz sawtooth wave synchronized with the S1 gate signal. The time corresponding to the pulse width of the comparison result was the phase-shift quantity.

_{out2}, denoted by V

_{fb2}, and the voltage command value V

_{out2}*. Thereafter, the PI-calculated signal of this difference was compared with the 800 kHz sawtooth wave synchronized with the S1 gate signal. In this case, by setting the frequency of the sawtooth wave to twice the switching frequency, the pulse signal after comparison simultaneously generated the interleaved S5 and S6 switching signals. Subsequently, the inverted AND (NAND) of this pulse signal and the H-bridge inverter switching signal was created to enable the assigned switching of S5 when V

_{txs}was positive and that of S6 when V

_{txs}was negative, as demonstrated in Table 1 and Figure 3. For the modes in Table 1, in which the switching states of S5 and S6 were irrelevant, S5 and S6 were turned on to prevent loss owing to a current flow to the body diode.

#### 3.3. Operation Points

_{out1}between 200 and 1400 W using an inductive resistance of 8 Ω. There were four operation points for the output power on the step-down chopper side P

_{out2}between 150 and 500 W using a non-inductive resistance of 1 Ω. These 20 operation points in total were numbered from #01 to #20. An additional operation point #21 was set for an output of 2 kW, with output power on the current doubler side of 1421 W and output power on the step-down chopper side of 588 W. Based on these operation points, the measurements were performed as described in the following, where the numbers shown in Figure 8 are used to indicate the operation points.

#### 3.4. Voltage Target Value Response Characteristics

_{out1}and V

_{out2}, and the output currents I

_{out1}and I

_{out2}from power-on to the steady state at operation point #21 with a total output power of 2058 W. As indicated in Figure 9, both the voltage and current took less than 1 s from power-on to settling, demonstrating the ability to control two different voltages at an output of 2 kW. The settled voltage values were 48.9 V for V

_{out1}and 12.4 V for V

_{out2}. These were shifted from their command values of 48 and 12 V, which was caused by an error in the voltage dividing resistance ratio. In the steady state, the ripple voltage was ±1.3 V for both V

_{out1}and V

_{out2}, whereas the ripple current was ±0.8 A for I

_{out1}and ±1.6 A for I

_{out2}. The reason for the larger value of the ripple current I

_{out2}compared to I

_{out1}is that TCP303 (Tektronix), which was used to measure I

_{out2}, has a lower resolution than TCP312A (Tektronix), which was used to measure I

_{out1}.

#### 3.5. Operating Waveforms

_{txp}, V

_{txs}, I

_{txp}, I

_{txs}, V

_{gs5}, V

_{gs6}, V

_{ds5}, V

_{ds6}, V

_{diode1}, V

_{diode2}, I

_{L11}, I

_{L12}, I

_{L21}, and I

_{L22}. V

_{txp}is the transformer primary side voltage, I

_{txp}and I

_{txs}are the transformer primary and secondary side currents, V

_{gs5}and V

_{gs6}are the gate-source voltages of S5 and S6, V

_{ds5}and V

_{ds6}are the drain-source voltages of S5 and S6, and V

_{diode1}and V

_{diode2}are the voltages across D1 and D2, respectively. In our setup, the oscilloscope had four channels and could not measure all waveforms simultaneously. Therefore, one channel was used to measure the I

_{txp}waveform constantly as the trigger channel to synchronize the results of multiple measurements. The measurements were performed at four operation points: #01, where both P

_{out1}and P

_{out2}were minimized; #05, where only P

_{out1}was maximized based on #01; #16, where only P

_{out2}was maximized in the same manner; and #20, where both P

_{out1}and P

_{out2}were maximized. As can be observed from Figure 10, the operation proceeded at 2.5 μs (400 kHz) per cycle at all four operation points and there were indeed six operation modes, as described in Table 1 and Figure 3. These results confirm that the proposed circuit behaved as designed. Meanwhile, surges and associated ringing appeared in the secondary side circuit voltage at all operation points. The ringing frequencies were approximately 15 and 60 MHz, and these were considered as resonances owing to the transformer leakage inductance and the parasitic capacitance of S5 and S6 and D1 and D2, respectively. Noise was also observed at these frequencies in V

_{gs5}and V

_{gs6}, indicating that high-frequency noise propagated in the entire secondary side circuit.

#### 3.6. Detailed Operation Modes

_{txp}, V

_{txs}, I

_{txp}, I

_{txs}, V

_{gs5}, V

_{gs6}, V

_{ds5}, V

_{ds6}, V

_{diode1}, and V

_{diode2}for a half period at three operation points, namely #01, #05, and #16, in an enlarged view. This half period corresponded to the ideal operation modes 1, 2, and 3, as previously described in Table 1, Figure 3 and Figure 4. Although the behavior varied slightly depending on the operation point, there were nine modes for the measured waveforms in total, which are divided by t

_{n}(n = 1 to 11) in Figure 11. In addition to the ideal operation modes 1, 2, and 3, six additional modes for state transitions were present. Table 5 displays the possible detailed operation modes for each operation point, and Figure 12 depicts the current path of the secondary side circuit in each operation mode. The operation in each mode is described below based on Figure 11 and Figure 12.

_{txp}started to increase. Furthermore, S5, S6, D1, and D2 were in the on-state. The currents flowed from the source to the drain in S5 and from the drain to the source in S6, and a negative current flowed in the transformer. Because both ends of the transformer were connected to GND, a voltage was generated at V

_{txs}corresponding to L di/dt of the current path, but not corresponding to V

_{txp}.

- 2.

_{gs5}was turned off and the current flowing to S5 was commutated to the body diode. This mode continued until the current in the body diode became zero. Accordingly, a larger S5 current (larger output power) meant that this mode would last longer. In the case of #01, where V

_{gs5}was turned off, no current flowed from the source to the drain in S5; therefore, this mode did not exist for #01. In the cases of #05 and #16, owing to the different operation points, the commutated S5 body diode current flowed in different paths (Figure 12b,c).

_{txp}was generated at V

_{txs}yet. Therefore, when the duty ratio was constant for V

_{txp}, when this mode was longer (the output power was larger), the duty ratio d

_{1}for V

_{txs}was smaller. Because d

_{1}was proportional to the output voltage V

_{out1}(Table 2), it attempted to take a constant value when V

_{out1}was constant. As a result, the duty ratio for V

_{txp}increased as the output power increased.

- 3.

_{txs}started to rise. This V

_{txs}acted as a power source to charge C

_{ds5}(Figure 12d,f). This charging current was the peak current of I

_{txs}and the current change generated a surge voltage at V

_{ds5}. As described later, this noise propagated to the entire secondary side circuit, including V

_{gs5}and V

_{gs6}. A larger P

_{out2}resulted in a larger rate of change in the current. Therefore, the peak surge voltage was greater for #16 than for #01 and #05. Moreover, because the L21 current (D1 current) in the previous mode was small for #01 and #05, the charging current for C

_{ds5}flowed to not only L21, but also to D1, causing the charging (t

_{3}< t < t

_{4}) and discharging (t

_{4}< t < t

_{5}) of the D1 parasitic capacitance C

_{D1}(Figure 12d,e). This charging and discharging generated a voltage of approximately 70 V at V

_{diode1}. However, for #16, the D1 current in the previous mode was sufficiently large, and thus, the charging current for C

_{ds5}did not charge C

_{D1}(Figure 12f).

- 4.

- 5.

_{ds5}was caused by turning on V

_{gs5}, when the current flowing to L21 started to switch from the D1 current to the S5 current. The current continued to flow into S5 and D1 until S5 was on and completely switched; therefore, both ends of V

_{txs}were connected to GND again, reducing V

_{txs}.

- 6.

_{ds5}was complete and S5 was completely on, the current started to flow to L21 via S5. At the same time, the charging of C

_{D1}started to turn off D1. The peak for I

_{txs}was the charging current. The current change at this point generated a surge voltage at V

_{diode1}. The periods t

_{6}to t

_{8}were the time from the start of discharging C

_{ds5}until the end of charging C

_{D1}. The current involved in the charging and discharging was dependent on P

_{out2}. Consequently, #16, with a greater P

_{out2}, had a longer t

_{6}to t

_{8}period than #01 and #05.

- 7.

- 8.

_{txp}and V

_{txs}decreased simultaneously. Accordingly, the current flowing from the transformer to L21 decreased. To compensate for this current loss, D1 was turned on. Discharging of C

_{D1}occurred as a preliminary step.

- 9.

#### 3.7. Load Disturbance Response Characteristics

_{out1}, I

_{out1}, V

_{out2}, and I

_{out2}when the operation point was switched during steady-state operation. Figure 15 shows the waveforms of V

_{txs}, V

_{out1}, and V

_{out2}at operation point #08. In Figure 13, operation points #02 and #03 were switched to switch P

_{out1}only. In Figure 14, #03 and #08 were switched to switch P

_{out2}only. PSIM version 12.04 (Powersim) was used for the simulation. The parameters in Table 3 were used in the simulation, and an ideal device was assumed for the switching devices. Furthermore, no parasitic resistance, inductance, or capacitance existed in the simulation circuit. Figure 13 and Figure 14 verify the following: (1) when switching P

_{out1}and switching P

_{out2}, it recovered to a steady state within 4 ms after the switching of the operation point, and (2) each waveform from the operation point switching to the recovered steady state was in good agreement with the simulated waveform. Based on these results, the load variation control was realized as designed. Compared to the simulation results, the actual measurement results exhibited greater superimposed noise in the voltage and current. These noises were in accordance with the surge timing of V

_{txs}, as illustrated in Figure 15. As indicated above, a V

_{txs}surge was generated at the switching timing of S5, S6, D1, and D2, thereby demonstrating that the switching noises in the secondary side circuit propagated to the output voltage. This indicates the noise propagation via paths that could not be absorbed by the output smoothing capacitors C1 and C2, revealing the layout design issue of the secondary side circuit.

## 4. Efficiency and Loss Evaluation

#### 4.1. Efficiency Characteristics

_{in}and output power P

_{out1}and P

_{out2}were measured using a power analyzer, namely WT1800 (YOKOGAWA). The efficiency η was measured at each operation point of the test circuit based on the following equation:

_{out1}increased, whereas it decreased as P

_{out2}increased. The maximum efficiency was 81.3% at #05, where P

_{out1}was the maximum and P

_{out2}was the minimum. The minimum efficiency was 65.1% at #16, where P

_{out2}was the maximum and P

_{out1}was the minimum. These results demonstrate the significant influence of the load loss of P

_{out2}on the reduced efficiency.

#### 4.2. Loss Characteristics

_{txp}and P

_{txs}of the transformer on the primary and secondary sides, respectively, were calculated based on the following equation:

_{txp}and P

_{txs}as well as the measured P

_{in}, P

_{out1}, and P

_{out2}were used to divide the total loss W

_{total}into three parts: the inverter loss W

_{inv}, transformer loss W

_{tx}, and secondary side loss W

_{sec}. The derivation formula for each loss is displayed in Table 6. Owing to the convenience of the measurement system, the time of the data acquisition by the power analyzer and the oscilloscope was not simultaneous but differed in each case.

_{out1}or P

_{out2}, respectively. The left axis indicates the power loss, and the right axis is the square of the total output current I

_{out1}+ I

_{out2}. The right axis is provided to indicate the conduction loss. As illustrated in Figure 17, the total loss and those at the different locations increased in the order of #01 < #05 < #16 < #20. This trend was consistent with the square of the total output current. Thus, it was demonstrated that the conduction loss was dominant compared to the iron loss or switching loss at the 400 kHz operation. Moreover, the secondary side loss accounted for more than half of the total loss at all operation points. Therefore, to improve the efficiency of the test circuit, it is effective to reduce the conduction loss in the secondary side circuit.

## 5. Conclusions

## Author Contributions

## Funding

## Conflicts of Interest

## Appendix A

_{fb1}and V

_{fb2}, the feedback voltages of the main circuit output voltage V

_{out1}and V

_{out2}, are input to FPGA. G1′~G6′ are generated by FPGA and input to the gate drive circuits. Gate signals G1~G6 adjusted by isolated gate drivers and gate resistances R

_{g}in the gate drive circuits input to each gate of S1~S6 in the main circuit, respectively. S1~S4 control V

_{out1}(V

_{fb1}) and S5, S6 control V

_{out2}(V

_{fb2}), respectively. This is a whole feedback loop image of the proposed circuit.

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**Figure 2.**Decomposed configuration of secondary circuit: (

**a**) current doubler; (

**b**) step-down chopper.

**Figure 4.**Equivalent circuit and current flow of each operation mode in secondary circuit: (

**a**) Mode 1; (

**b**) Mode 2; (

**c**) Mode 3; (

**d**) Mode 4; (

**e**) Mode 5; (

**f**) Mode 6.

**Figure 6.**Experimental circuit setup: (

**a**) main circuit with control circuit; (

**b**) main circuit without control circuit.

**Figure 12.**Current path of experimental circuit in each operation mode; (

**a**) Mode 1; (

**b**) Mode 2-1; (

**c**) Mode 2-2; (

**d**) Mode 3-1a; (

**e**) Mode 3-1b; (

**f**) Mode 3-2; (

**g**) Mode 4; (

**h**) Mode 5; (

**i**) Mode 6; (

**j**) Mode 7; (

**k**) Mode 8; (

**l**) Mode 9.

**Figure 13.**Results of P

_{out1}dynamic response test when P

_{out2}= 141 W: (

**a**) measurement results; (

**b**) simulation results.

**Figure 14.**Results of P

_{out2}dynamic response test when P

_{out1}= 825 W: (

**a**) measurement results; (

**b**) simulation results.

Operation Mode | 1 | 2 | 3 | 4 | 5 | 6 |
---|---|---|---|---|---|---|

V_{txs} | 1 | 1 | 0 | −1 | −1 | 0 |

S5 | off | on | - | - | - | - |

S6 | - | - | - | off | on | - |

Symbol | Value | Symbol | Value |
---|---|---|---|

V_{out1} | $\frac{{d}_{1}{N}_{2}{V}_{in}}{{N}_{1}}$ | V_{out2} | $\frac{{d}_{2}{N}_{2}{V}_{in}}{{N}_{1}}$ |

I_{out1} | $\frac{{d}_{1}{N}_{2}{V}_{in}}{{N}_{1}{R}_{1}}$ | I_{out2} | $\frac{{d}_{2}{N}_{2}{V}_{in}}{{N}_{1}{R}_{2}}$ |

$\overline{{I}_{L11}}$ $\overline{{I}_{L12}}$ | $\frac{{d}_{1}{N}_{2}{V}_{in}}{{2N}_{1}{R}_{1}}$ | $\overline{{I}_{L21}}$ $\overline{{I}_{L22}}$ | $\frac{{d}_{2}{N}_{2}{V}_{in}}{{2N}_{1}{R}_{2}}$ |

γ_{L11}γ _{L12} | $\frac{{2R}_{1}\left({1-d}_{1}\right)T}{{L}_{1}}$ | γ_{L21}γ _{L22} | $\frac{{2R}_{2}\left({1-d}_{2}\right)T}{{L}_{2}}$ |

Δi_{c1} | $\frac{{R}_{1}\left({1-d}_{1}\right){TI}_{out1}}{{L}_{1}}$ |
Δi_{c2} | $\frac{{R}_{2}\left({1-d}_{2}\right){TI}_{out2}}{{L}_{2}}$ |

Parameter | Value |
---|---|

V_{in} | 300 V |

C_{in} | 330 μF |

V_{out1} (current doubler side) | 48 V |

V_{out2} (step-down chopper side) | 12 V |

Switching frequency | 400 kHz (T = 2.5 μs) |

FPGA | XC7K70T-1FBG484C (Xilinx) |

Clock frequency of FPGA | 200 MHz |

S1, S2, S3, S4, S5, S6 | SCT3030AL (ROHM) |

D1, D2 | FFSH4065A (ON Semiconductor) |

Transformer turns ratio | N_{1}:N_{2} = 4:2 |

L11 and L12 | 15 μH |

L21 and L22 | 5 μH |

C1 | 44 μF |

C2 | 188 μF |

Instrument | Model Number |
---|---|

Oscilloscope | HDO6104A-MS (TELEDYNE) |

Voltage differential probe | 700924 (YOKOGAWA) |

Current probe (<30 A) | TCP312A (Tektronix) |

Current probe (>30 A) | TCP303 (Tektronix) |

Deskew calibration source | DCS025 (TELEDYNE) |

Operation Point | Operation Mode | |||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|

1 | 2-1 | 2-2 | 3-1a | 3-1b | 3-2 | 4 | 5 | 6 | 7 | 8 | 9 | |

t_{1}~t_{2} | t_{2}~t_{3} | t_{3}~t_{5} | t_{5}~t_{6} | t_{6}~t_{7} | t_{7}~t_{8} | t_{8}~t_{9} | t_{9}~t_{10} | t_{10}~t_{11} | ||||

#01 | ○ | ○ | ○ | ○ | ○ | ○ | ○ | ○ | ○ | |||

#05 | ○ | ○ | ○ | ○ | ○ | ○ | ○ | ○ | ○ | ○ | ||

#16 | ○ | ○ | ○ | ○ | ○ | ○ | ○ | ○ | ○ |

Part | Symbol | Equation |
---|---|---|

Total loss | W_{total} | P_{in} − (P_{out1} + P_{out2}) |

Inverter loss | W_{inv} | P_{in} − P_{txp} |

Transformer loss | W_{tx} | P_{txp} − P_{txs} |

Secondary side loss | W_{sec} | W_{total} − (W_{inv} + W_{tx}) |

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## Share and Cite

**MDPI and ACS Style**

Matsushita, Y.; Noguchi, T.; Taguchi, N.; Ishii, M.
2 kW Dual-Output Isolated DC/DC Converter Based on Current Doubler and Step-Down Chopper. *World Electr. Veh. J.* **2020**, *11*, 78.
https://doi.org/10.3390/wevj11040078

**AMA Style**

Matsushita Y, Noguchi T, Taguchi N, Ishii M.
2 kW Dual-Output Isolated DC/DC Converter Based on Current Doubler and Step-Down Chopper. *World Electric Vehicle Journal*. 2020; 11(4):78.
https://doi.org/10.3390/wevj11040078

**Chicago/Turabian Style**

Matsushita, Yoshinori, Toshihiko Noguchi, Noritaka Taguchi, and Makoto Ishii.
2020. "2 kW Dual-Output Isolated DC/DC Converter Based on Current Doubler and Step-Down Chopper" *World Electric Vehicle Journal* 11, no. 4: 78.
https://doi.org/10.3390/wevj11040078