In recent years, noise-induced transient faults and circuit aging effects are two main mechanisms of VLSI circuit failure during its lifetime. These effects will change the timing and voltage levels of logic gates and can induce timing errors, voltage level distortion, or bit-flips when the influence accumulates to a certain degree. Most of the current transient fault analysis methods model the noise induced fault as a transient glitch and analyze the propagation characteristics of the glitch in the logic circuit. They focus on the timing errors of the circuit and apply the state-of-art statistical static timing analysis method to evaluate the timing effect. However, with respect to the voltage level, efficient analysis methods have not yet been studied in detail.
Figure 1.
Pipeline stage structure of digital sequential circuits.
As shown in
Figure 1, a noise-induced voltage transient (at the input port of NAND gate A) can become a voltage or timing fault only if it propagates to the end of one pipeline stage (at the input port of DFF2) and is stored in the latch. Thus, although hundreds of logic gates may exist in one pipeline stage, only the gates connected to the latch inputs are required to estimate the transient fault rates at the gates, and the computational complexity can be dramatically reduced. According to the characteristics of a CMOS logic circuit, the probability that a logic state is stored in the latch depends on the voltage level at the data input of that latch during the sampling time window. Because the noise-induced voltage transient arrives at the input of the latch at any point in the clock cycle with an equal probability, a high occurrence probability for the voltage transient will result in a high probability that the wrong logic state is captured by the latch. Therefore, the statistical analysis method proposed in this paper is applied to estimate the probability density function (pdf) of the voltage level at the end of one pipeline stage in the presence of noise effects. In a digital system, considering the low-pass characteristics of the logic gates and the central limit theorem, the effects of noise can be generally modeled as variations following a normal distribution in terms of the supply voltage and input signal of the pipeline stages, and MC simulation is commonly used to analyze these effects on circuit performance. However, the computational cost of MC is extremely high due to the complexity of the circuit. Some improved MC methods have effectively decreased the computational costs for transient fault rate analysis [
19,
20] and have shortened the MC computation time. However, these methods do not consider the effects of some potential circuit characteristic changes in the analysis framework, such as aging effects, which undermine the accuracy of the analysis results during the lifetime of the circuit. Thus, in this paper, we propose a new NBTI-aware statistical analysis method to acquire accurate transient fault rates for different parts of the circuit to resolve the high computational cost problem of MC method. The design flow of the proposed method is shown in
Figure 2.
Figure 2.
NBTI-aware transient fault rate analysis framework based on the PVTC method.
2.1. PVTC-Based Analysis for Single Logic Gates
In VLSI design, a combinational circuit is composed of basic logic gate cells; thus, the transient fault analysis method begins with a single logic cell. In this paper, to describe the random characteristics of noise-induced effects, we apply a voltage level probability density function (pdf) to describe the input signal and supply and propose a PVTC method to establish the relationship between the input and output voltage pdf distributions of the logic gates. The basic scheme of the PVTC modeling method for logic gates is shown in
Figure 3.
Figure 3.
Diagram of the PVTC modeling method.
Figure 3.
Diagram of the PVTC modeling method.
As shown in
Figure 3, the function relationship between the voltage level of the input signal and output signal can be acquired by the PVTC model.
Figure 4 provides an illustration of the procedure for establishing the PVTC model for an inverter gate.
Figure 4a presents an SVTC curve for an inverter gate by SPICE DC analysis, and the pdf of the input signal can be modelled as a random variable following a normal distribution due to the environmental noise effects, as shown in
Figure 4c.
Figure 4a,c show that the probability of the input signal falling into the shaded area [
Vin1,
Vin2] is equal to the probability of the output signal falling into the shaded area [
Vout1,
Vout2], and this relationship can be expressed as
However,
Figure 4b illustrates that in the practical construction of an SVTC curve, instead of a continuous curve, only a series of discrete points can be acquired because of the actual characteristics of DC analysis. Therefore, the corresponding output signal point
Vo for any input signal point
Vi may not be found exactly in the discrete SVTC curve, which is necessary for the probability calculation in Equation (1). Thus, a discrete pdf approximation process must be used to implement the calculation. First, the input range of the signal is divided into a sequence of equal-length intervals by DC analysis, and the length of each interval is
dVin, which can be set in the analysis process. We assume that, for each point (
Vin,i,
Vout,i) in the SVTC curve (e.g., point
D in
Figure 4b), input signals falling into area [
Vin,i −
dVin/2,
Vin,i +
dVin/2] or the corresponding output signal of area [
VA,
VC] all have the same voltage
Vout,i. Furthermore, the approximation error can be tolerated because the division interval of
dVin is small. Then, the probability of the output voltage level being equal to
Vout,i can be calculated as
Figure 4.
Principle of the PVTC method for an inverter gate. (a) SVTC curve for an inverter gate; (b) Calculation of output signal’s pdf; (c) Voltage pdf for input signal Vin; (d) Division of Vin’s pdf.
Figure 4.
Principle of the PVTC method for an inverter gate. (a) SVTC curve for an inverter gate; (b) Calculation of output signal’s pdf; (c) Voltage pdf for input signal Vin; (d) Division of Vin’s pdf.
Subsequently, to calculate the probability of the output signal falling into area [
Vout2,
Vout1], we search for all points (
Vin,i,
Vout,i) having an output signal belonging to this area in the SVTC curve. All of the
P(
Vout,i) of these points are then accumulated, and the probability of the output signal falling into the given area can be acquired. In the pdf calculation process, the gap between
Vout1 and
Vout2 is set to a small interval
dVout; therefore, the pdf of area
p(
Vout) can be estimated as
where (
Vin,i,
Vout,i) is the
ith point on the SVTC curve with
Vout2 <
Vout,i ≤
Vout1.
PVTC analysis for gates with multiple input ports, such as NAND and NOR gates, can be modelled by a similar method. However, the SVTC curves for these gates are extended to three-dimensional curves (two or more input axes and one output axis), as shown in
Figure 5.
Figure 5.
Three-dimensional SVTC curves for multi-input gates. (a) SVTC of NAND gate; (b) SVTC of NOR gate.
Figure 5.
Three-dimensional SVTC curves for multi-input gates. (a) SVTC of NAND gate; (b) SVTC of NOR gate.
In
Figure 5, the
x- and
y-axes are the two input voltage levels, and the
z-axis is the output voltage level. The pdf calculation for the output signal
Vout is expressed as
where (
Vin1,i,
Vin2,i,
Vout,i) is the
ith point on the three-dimensional SVTC curve with
Vout2 <
Vout,i ≤
Vout1.
Accurate analysis of transient fault occurrence probabilities, or transient fault rates for different parts of circuits, is an important step for the effective implementation of transient fault mitigation techniques. Therefore, after acquiring the pdf of a circuit’s output ports, we can calculate the transient fault rate
Perror for these ports.
Figure 6 presents an illustration of the transient fault rate calculation for an inverter gate whose normal state is input “one” and output “zero”.
Figure 6.
Transient fault rate calculation for an inverter with input “one”.
Figure 6.
Transient fault rate calculation for an inverter with input “one”.
As shown in
Figure 6, the two shaded areas in the figure are the probability of logic “0” and logic “1”. Then,
Perror can be calculated according to Equation (5):
where
Vhigh,min is the voltage threshold for logic “one”,
Vnom is the expected correct voltage for the output signal, and
p(
Vout,i) is the estimated pdf of the points whose
Vout,i is greater than
Vhigh,min.
2.2. PVTC-Based Analysis for Multi-Gate Circuits
Transient fault analysis for single gates is clearly not sufficient. Digital logic circuits typically consist of hundreds of gates, and there is complex logic dependency between them, meaning that the pdf of the output of one gate is the pdf of the input of another gate. The pdf calculation result for the single gate obtained in
Section 2.1 is a series of discrete points, which is not suitable for estimating the pdf for gates in the next stage. Therefore, some approximation procedures are required, and the Riemann sum
p(
Vin)
dVin is applied to substitute for the integration ∫
p(
Vin)
dVin in Equations (3) and (4). We then obtain the modified pdf calculation equation for single- and multi-input gates in Equations (6) and (7), respectively.
where (
Vin,i,
Vout,i) or (
Vin1,i,
Vin2,i,
Vout,i) is the
ith point on the SVTC curve with
Vout2 <
Vout,i ≤
Vout1.
However, the functional complexity of actual circuits usually results in re-convergent fan-out characteristics, which causes different input ports of one gate to be interdependent. The full adder in
Figure 7 is an illustration of re-convergent fan-out characteristics.
Figure 7.
Illustration of the re-convergent fan-out characteristics in a multi-gate circuit.
Figure 7.
Illustration of the re-convergent fan-out characteristics in a multi-gate circuit.
As shown in
Figure 7, the output signal
C for the full adder circuit is determined by the inputs of gate
G5,
N1 and
N2. Port
N1 is the output of NAND gate
G3 and is determined by the root input signals
A,
B, and
D. Port
N2 is the output of NAND gate
G4 and is determined by
A and
B. Therefore, the two input ports of gate
G5 are not independent. Thus, in the pdf calculation of the output signal
C of
G5, the correlation between input ports
N1 and
N2 must be considered, as the calculation may otherwise lead to inaccurate results. To solve this problem, the pdf calculation formula Equation (7) is adapted by considering the dependence between
N1 and
N2 because these two signals are both related to root inputs
A and
B. The total probability formula Equation (8) is applied to estimate the pdf of the output signal
C, which considers conditional probability of input ports
N1 and
N2 of gate
G5 on the root input signals
VA and
VB.
In Equation (8), point (
VN1,i,
VN2,i,
VC,i) is the
ith point on the SVTC curve of gate
G5 with
VC2 <
VC,i ≤
VC1. (
VA,j,
VB,j) is each input voltage pair of the discrete three-dimensional SVTC curve acquired by SPICE DC analysis, as shown in
Figure 5. The conditional probability
p(
VN2,i|
VA =
VA,j,
VB =
VB,j) can be calculated directly because
VN2 is determined by
VA and
VB only, whereas
VN1 is determined by
D and
N0, and the pdf estimate of the conditional probability
p(
VN0,i|
VA =
VA,j,
VB =
VB,j) can be acquired by a similar method to that of
N2. The conditional probability
p(
VN1,i|
VA = VA,j,
VB = VB,j) can then be found by calculating the pdf estimate of gate
G3, and the final result of the pdf calculation for gate
G5’s output
C can be determined. The pdf estimation for other logic circuits can also be obtained by a similar method.
2.3. NBTI Effect and Its Impact on the PVTC Method
At present, the NBTI effect is the dominant aging mechanism for VLSI circuits; this effect occurs when pMOS transistors are negatively biased, which causes a shift in the threshold voltages (
Vth) and in turn causes changes in circuit characteristics during its lifetime. Grasser
et al. [
21] noted that in small-sized devices in CMOS logic circuits, the threshold voltage change induced by the NBTI effect is dominated by stochastic charging/discharging events of individual oxide defects; therefore, each device shows a different degradation curve. Clearly, this type of NBTI model will greatly complicate the analysis process. Because our aim was to estimate the transient fault rate that considers both environmental noise and the NBTI effect and provide a design basis for transient fault mitigation techniques, in this paper, pMOS transistors are assumed to suffer the same degree of degradation during the lifetime of the circuits, and the R-D model is applied to analyze the NBTI effect. According to the R-D model, the
Vth degradation of pMOS transistors caused by NBTI has two phases: the stress phase and the recovery phase. The magnitude of
Vth increases during the stress phase (
i.e.,
Vgs = −
Vdd), whereas the magnitude of
Vth partially decreases towards its initial value during the recovery phase (
i.e.,
Vgs = 0); however, recovery can only partially alleviate the effect of NBTI. The threshold voltage change during stress and recovery cycles is illustrated in
Figure 8.
Figure 8.
Threshold voltage change during stress and recovery cycles.
Figure 8.
Threshold voltage change during stress and recovery cycles.
Therefore, the magnitude of
Vth degradation is strongly dependent on the duty cycle (
α) of the input signal, which reflects the fraction of time that the pMOS transistor spent in the stress state in one clock period. In this paper, we apply the long-term prediction model proposed in [
14] to calculate the
Vth degradation effect as follows
where
, and
Tclk is the clock period. According to the formula Equation (9), we simulate the NBTI effect of a pMOS transistor using the PTM 45 nm model [
22] in HSPICE. The increase in
Vth after working 10
8 s (approximately 3 years) is presented in
Figure 9. The duty cycle (
α) of the NBTI effect is set from 0.05 to 0.95, with a step of 0.3.
Figure 9.
Change of Vth vs. work time under different duty cycles of an input signal.
Figure 9.
Change of Vth vs. work time under different duty cycles of an input signal.
The change in the SVTC curve for an inverter gate caused by the
Vth increase is shown in
Figure 10; this change, in turn, affects the occurrence probability of transient faults. Therefore, to acquire accurate transient fault rate estimations during the lifetime of circuits, changes in circuit characteristics caused by NBTI effect should be considered in the PVTC analysis framework.
Figure 10.
Changes in the SVTC of an inverter in the fresh and degraded states.
Figure 10.
Changes in the SVTC of an inverter in the fresh and degraded states.