# Decimal Multiplication in FPGA with a Novel Decimal Adder/Subtractor

^{1}

^{2}

^{*}

## Abstract

**:**

## 1. Introduction

## 2. Related Work

## 3. Decimal Adder/Subtractor

#### 3.1. BCD/Excess-6 Adder

#### 3.2. BCD/Excess-6 Subtractor

#### 3.3. BCD/Excess-6 Adder/Subtractor

## 4. Decimal Multiplier

#### 4.1. Partial Product Generator—Method 1

#### 4.2. Partial Product Generator—Method 2

#### 4.3. Generation of Multiples

#### 4.4. Partial Product Reduction

#### 4.5. BCD/Excess-6 to BCD Converter

#### 4.6. Architecture of the Two Versions of the Decimal Multiplier

## 5. Results

## 6. Conclusions and Future Work

## Author Contributions

## Funding

## Conflicts of Interest

## References

- Tsang, A.; Olschanowsky, M. A Study of Database 2 Customer Queries; Technical report; IBM Santa Teresa Laboratory: San Jose, CA, USA, 1991. [Google Scholar]
- IEEE Standards Committee. 754-2008 IEEE Standard for Floating-Point Arithmetic; IEEE: New York, NY, USA, 2008; pp. 1–58. [Google Scholar]
- Quinn, K. Ever had problems rounding offfigures? this stock exchange has. Wall Str. J.
**1983**, 202, 37. [Google Scholar] - IBM Corporation. The Telco Benchmark. 2017. Available online: http://speleotrove.com/decimal/telcoSpec.html (accessed on 20 May 2020).
- Cowlishaw, M.F. Decimal floating-point: Algorism for Computers. In Proceedings of the 16th IEEE International Symposium on Computer Arithmetic, Santiago de Compostela, Spain, 15–18 June 2003; pp. 104–111. [Google Scholar]
- IBM Corporation. Decimal Arithmetic FAQ. 2007. Available online: http://speleotrove.com/decimal/decifaq1.html#needed (accessed on 20 May 2020).
- Cornea, M.; Anderson, C.; Harrison, J.; Tang, P.; Schneider, E.; Tsen, S. A software implementation of the IEEE 754R decimal floating-point arithmetic using the binary encoding format. In Proceedings of the IEEE 18th Symposium on Computer Arithmetic, Montpellier, France, 25–27 June 2007; pp. 29–37. [Google Scholar]
- ANSI CdecNumber Library v3.68. Available online: http://speleotrove.com/decimal/decnumber.html (accessed on 27 June 2021).
- GNU CCompiler Library. Available online: https://www.gnu.org/software/libc/ (accessed on 27 June 2021).
- Cornea, M.; Crawford, J. IEEE 754R Decimal Floating-Point Arithmetic: Reliable and Efficient Implementation for Intel Architecture Platforms. Intel Technol. J.
**2007**, 11, 91–94. [Google Scholar] [CrossRef] - Busaba, F.; Krygowski, C.A.; Li, W.H.; Schwarz, E.M.; Carlough, S.R. The IBM z900 Decimal Arithmetic Unit. In Proceedings of the ASilomar Conference on Signals, Systems, Computers, Pacific Grove, CA, USA, 4–7 November 2001; pp. 1335–1339. [Google Scholar]
- Le, H.Q.; Starke, W.J.; Fields, J.S.; O’Connell, F.P.; Nguyen, D.Q.; Ronchetti, B.J.; Sauer, W.M.; Schwarz, E.M.; Vaden, M.T. IBM POWER6 microarchitecture. IBM J. Res. Dev.
**2007**, 51, 639–662. [Google Scholar] [CrossRef] - Webb, C.F. IBM z10: The Next- Generation Mainframe Microprocessor. IEEE Micro
**2008**, 28, 19–29. [Google Scholar] [CrossRef] - Zhao, Y.; Wang, D.; Wang, L. Convolution Accelerator Designs Using Fast Algorithms. Algorithms
**2019**, 12, 112. [Google Scholar] [CrossRef][Green Version] - Deabes, W. FPGA Implementation of ECT Digital System for Imaging Conductive Materials. Algorithms
**2019**, 12, 28. [Google Scholar] [CrossRef][Green Version] - Vestias, M.P.; Neto, H.C. Revisiting the Newton-Raphson Iterative Method for Decimal Division. In Proceedings of the 2011 21st International Conference on Field Programmable Logic and Applications, Chania, Greece, 5–7 September 2011; pp. 138–143. [Google Scholar] [CrossRef]
- Véstias, M.P.; Neto, H.C. Iterative decimal multiplication using binary arithmetic. In Proceedings of the 2011 VII Southern Conference on Programmable Logic (SPL), Cordoba, Argentina, 13–15 April 2011; pp. 257–262. [Google Scholar] [CrossRef]
- Larson, R.H. High-Speed Multiply Using Four Input Carry-Save Adder. IBM Tech. Discl. Bull.
**1973**, 16, 2053–2054. [Google Scholar] - Ueda, T. Decimal Multiplying Assembly and Multiply Module. U.S. Patent 5,379,245, 3 January 1995. [Google Scholar]
- Castillo, E.; Lloris, A.; Morales, D.P.; Parrilla, L.; García, A.; Botella, G. A new area-efficient BCD-digit multiplier. Digit. Signal Process.
**2017**, 62, 1–10. [Google Scholar] [CrossRef] - Erle, M.A.; Schwarz, E.M.; Schulte, M.J. Decimal Multiplication with Efficient Partial Product Generation. In Proceedings of the 17th IEEE Symposium on Computer Arithmetic, Cape Cod, MA, USA, 27–29 June 2005; pp. 21–28. [Google Scholar]
- Erle, M.A.; Schulte, M.J. Decimal multiplication via carry-save addition. In Proceedings of the 14th IEEE International Conference on Application Specific Systems, San Diego, CA, USA, 9–11 June 2003; pp. 348–358. [Google Scholar]
- Lang, T.; Nannarelli, A. A radix-10 combinational multiplier. In Proceedings of the IEEE 40th International Asilomar Conference on Signals, Systems, and Computers, Kos Island, Greece, 29 October–1 November 2006; pp. 313–317. [Google Scholar]
- Vázquez, A.; Antelo, E.; Montuschi, P. Improved Design of High-Performance Parallel Decimal Multipliers. IEEE Trans. Comput.
**2010**, 59, 679–693. [Google Scholar] [CrossRef] - Gorgin, S.; Jaberipur, G. Sign-Magnitude Encoding for Efficient VLSI Realization of Decimal Multiplication. IEEE Trans. Very Large Scale Integr. VLSI Syst.
**2017**, 25, 75–86. [Google Scholar] [CrossRef] - Cui, X.; Dong, W.; Liu, W.; Swartzlander, E.E.; Lombardi, F. High Performance Parallel Decimal Multipliers Using Hybrid BCD Codes. IEEE Trans. Comput.
**2017**, 66, 1994–2004. [Google Scholar] [CrossRef] - Zhu, M.; Jiang, Y.; Yang, M.; Chen, T. On High-Performance Parallel Decimal Fixed-Point Multiplier Designs. Comput. Electr. Eng.
**2014**, 40, 2126–2138. [Google Scholar] [CrossRef][Green Version] - Gorgin, S.; Jaberipur, G. A fully redundant decimal adder and its application in parallel decimal multipliers. Microelectron. J.
**2009**, 40, 1471–1481. [Google Scholar] [CrossRef] - Hoseininasab, S.S.; Nikmehr, H. Architectures for multiple constant decimal multiplication. Comput. Electr. Eng.
**2019**, 75, 31–45. [Google Scholar] [CrossRef] - Kenney, R.D.; Schulte, M.J. High Speed Multioperand Decimal Adders. IEEE Trans. Comput.
**2005**, 54, 953–963. [Google Scholar] [CrossRef][Green Version] - Dadda, L. Multioperand Parallel Decimal Adder: A Mixed Binary and BCD Approach. IEEE Trans. Comput.
**2007**, 56, 1320–1328. [Google Scholar] [CrossRef] - Vázquez, A.; Antelo, E.; Montushi, P. A New Family of High-Performance Parallel Decimal Multipliers. In Proceedings of the IEEE 18th Symposium on Computer Arithmetic, Montpellier, France, 25–27 June 2007; pp. 195–204. [Google Scholar]
- Neto, H.; Véstias, M. Decimal Multiplier on FPGA using Embedded Binary Multipliers. In Proceedings of the International Conference on Field Programmable Logic and Applications, Dublin, Ireland, 27–31 August 2008; pp. 197–202. [Google Scholar]
- Véstias, M.; Neto, H. Parallel Decimal Multipliers using Binary Multipliers. In Proceedings of the IEEE 6th Southern Programmable Logic Conference, Pernambuco, Brazil, 24–26 March 2010; pp. 73–78. [Google Scholar]
- Fazlali, M.; Valikhani, H.; Timarchi, S.; Malazi, H.T. Fast Architecture for Decimal Digit Multiplication. Microprocess. Microsyst.
**2015**, 39, 296–301. [Google Scholar] [CrossRef] - Mukkamala, S.; Rathore, P.; Peesapati, R. Decimal multiplication using compressor based-BCD to binary converter. Eng. Sci. Technol. Int. J.
**2018**, 21, 1–6. [Google Scholar] [CrossRef] - Al-Khaleel, O.; Al-Qudah, Z.; Al-Khaleel, M.; Papachristou, C. High performance FPGA-based decimal-to-binary conversion schemes for decimal arithmetic. Microprocess. Microsystems
**2013**, 37, 287–298. [Google Scholar] [CrossRef] - Emami, S.; Sedighi, M. An Optimized Reconfigurable Architecture for Hardware Implementation of Decimal Arithmetic. Comput. Electr. Eng.
**2017**, 63, 18–29. [Google Scholar] [CrossRef] - Sutter, G.; Todorovich, E.; Bioul, G.; Vázquez, M.; Deschamps, J.P. FPGA Implementations of BCD Multipliers. In Proceedings of the IEEE International Conference on Reconfigurable Computing and FPGAs, Cancun, Mexico, 9–11 December 2009; pp. 36–41. [Google Scholar]
- Jaberipur, G.; Kaivani, A. Binary-coded decimal digit multipliers. IET Comput. Digit. Tech.
**2007**, 1, 377–381. [Google Scholar] [CrossRef][Green Version] - Vázquez, A.; de Dinechin, F. Efficient implementation of parallel BCD multiplication in LUT-6 FPGAs. In Proceedings of the 2010 International Conference on Field-Programmable Technology (FPT), Beijing, China, 8–10 December 2010; pp. 126–133. [Google Scholar]
- Véstias, M.; Neto, H. Parallel Decimal Multipliers and Squarers Using Karatsuba-Ofman’s Algorithm. In Proceedings of the 15th Euromicro Conference on Digital System Design, Cesme, Izmir, Turkey, 5–8 September 2012; pp. 782–788. [Google Scholar]
- Gao, S.; Al-Khalili, D.; Langlois, J.; Chabini, N. Efficient Realization of BCD Multipliers Using FPGAs. Int. J. Reconfigurable Comput.
**2017**, 2017, 2410408. [Google Scholar] [CrossRef] - Véstias, M.P.; Neto, H.C. Improving the area of fast parallel decimal multipliers. Microprocess. Microsyst.
**2018**, 61, 96–107. [Google Scholar] [CrossRef] - Neto, H.C.; Véstias, M.P. Decimal addition on FPGA based on a mixed BCD/excess-6 representation. Microprocess. Microsyst.
**2017**, 55, 91–99. [Google Scholar] [CrossRef]

**Figure 1.**Partial product generator for a single multiplier digit using subsets ${S}_{1}$ = {0, 5A, 10A} and ${S}_{2}$ = {0, A, 2A}.

**Figure 5.**Partial product generator for a single multiplier digit using subsets ${S}_{1}$ = {4A, 5A} and ${S}_{2}$ = {0, 2A, 4A}.

**Figure 7.**Architecture fo the proposed decimal multipliers. (

**a**) Decimal multiplier with method 1 and (

**b**) decimal multiplier with method 2.

w | z | Action |
---|---|---|

BCD | BCD | none |

BCD | excess-6 | $z\to \overline{z}-6$ |

excess-6 | BCD | $z\to \overline{z}+6$ |

excess-6 | excess-6 | none |

Digit | BCD | Excess-3 |
---|---|---|

0 | 0000 | 0011 |

1 | 0001 | 0100 |

2 | 0010 | 0101 |

3 | 0011 | 0110 |

4 | 0100 | 0111 |

5 | 0101 | 1000 |

6 | 0110 | 1001 |

7 | 0111 | 1010 |

8 | 1000 | 1011 |

9 | 1001 | 1100 |

Multiple | $\in {\mathit{S}}_{1}$ | $\in {\mathit{S}}_{2}$ | Operation |
---|---|---|---|

0 | 0 | 0 | 0 + 0 |

A | 0 | A | 0 + A |

2A | 0 | 2A | 0 + 2A |

3A | 5A | 2A | 5A − 2A |

4A | 5A | A | 5A − A |

5A | 5A | 0 | 5A + 0 |

6A | 5A | A | 5A + A |

7A | 5A | 2A | 5A + 2A |

8A | 10A | 2A | 10A − 2A |

9A | 10A | A | 10A − A |

${\mathit{b}}_{\mathit{i}}\left[3\right]{\mathit{b}}_{\mathit{i}}\left[2\right]{\mathit{b}}_{\mathit{i}}\left[1\right]{\mathit{b}}_{\mathit{i}}\left[0\right]$ | Multiple | Operation | ${\mathit{S}}_{\mathit{a}}$ | ${\mathit{S}}_{\mathit{b}}$ | op |
---|---|---|---|---|---|

“0000” | 0 | 0 + 0 | “00” | “00” | 0 |

“0001” | A | 0 + A | “00” | “01” | 0 |

“0010” | 2A | 0 + 2A | “00” | “10” | 0 |

“0011” | 3A | 5A − 2A | “01” | “10” | 1 |

“0100” | 4A | 5A − A | “01” | “01” | 1 |

“0101” | 5A | 5A + 0 | “01” | “00” | 0 |

“0110” | 6A | 5A + A | “01” | “01” | 0 |

“0111” | 7A | 5A + 2A | “01” | “10” | 0 |

“1000” | 8A | 10A − 2A | “10” | “10” | 1 |

“1001” | 9A | 10A − A | “10” | “01” | 1 |

Multiple | $\in {\mathit{S}}_{1}$ | $\in {\mathit{S}}_{2}$ | Operation |
---|---|---|---|

0 | 4A | 4A | 4A − 4A |

A | 5A | 4A | 5A − 4A |

2A | 4A | 2A | 4A − 2A |

3A | 5A | 2A | 5A − 2A |

4A | 4A | 0 | 4A + 0 |

5A | 5A | 0 | 5A + 0 |

6A | 4A | 2A | 4A + 2A |

7A | 5A | 2A | 5A + 2A |

8A | 4A | 4A | 4A + 4A |

9A | 5A | 4A | 5A + 4A |

${\mathit{b}}_{\mathit{i}}\left[3\right]{\mathit{b}}_{\mathit{i}}\left[2\right]{\mathit{b}}_{\mathit{i}}\left[1\right]{\mathit{b}}_{\mathit{i}}\left[0\right]$ | Multiple | Operation | ${\mathit{S}}_{\mathit{a}}$ | ${\mathit{S}}_{\mathit{b}}$ | op |
---|---|---|---|---|---|

“0000” | 0 | 4A − 4A | “0” | “10” | 1 |

“0001” | A | 5A − 4A | “1” | “10” | 1 |

“0010” | 2A | 4A − 2A | “0” | “01” | 1 |

“0011” | 3A | 5A − 2A | “1” | “01” | 1 |

“0100” | 4A | 4A + 0 | “0” | “00” | 0 |

“0101” | 5A | 5A + 0 | “1” | “00” | 0 |

“0110” | 6A | 4A + 2A | “0” | “01” | 0 |

“0111” | 7A | 5A + 2A | “1” | “01” | 0 |

“1000” | 8A | 4A + 4A | “0” | “10” | 0 |

“1001” | 9A | 5A + 4A | “1” | “10” | 0 |

a | ${\mathit{a}}_{\mathit{i}}[3-0]$ | $\mathit{ae}{3}_{\mathit{i}}[3-0]$ | ${\mathit{y}}_{\mathit{i}}[3-0]$ |
---|---|---|---|

0 | 0000 | 0011 | 0011 |

1 | 0001 | 0100 | 0100 |

2 | 0010 | 0101 | 0101 |

3 | 0011 | 0110 | 0110 |

4 | 0100 | 0111 | 0111 |

5 | 0101 | 1000 | 1000 |

6 | 0110 | 1001 | 1001 |

7 | 0111 | 1010 | 1010 |

8 | 1000 | 1011 | 1011 |

9 | 1001 | 1100 | 1100 |

a | $2{\mathit{a}}_{\mathit{i}}[4-0]$ | $2\mathit{ae}{3}_{\mathit{i}}[4-0]$ | ${\mathit{y}}_{\mathit{i}}[3-0]$ | |
---|---|---|---|---|

${\mathit{a}}_{\mathit{i}-\mathbf{1}}\left[\mathbf{4}\right]=\mathbf{1}$ | ${\mathit{a}}_{\mathit{i}-\mathbf{1}}\left[\mathbf{4}\right]=\mathbf{0}$ | |||

0 | 0 0000 | 0 0011 | 0100 | 0011 |

1 | 0 0010 | 0 0101 | 0110 | 0101 |

2 | 0 0100 | 0 0111 | 1000 | 0111 |

3 | 0 0110 | 0 1001 | 1010 | 1001 |

4 | 0 1000 | 0 1011 | 1100 | 1011 |

5 | 1 0000 | 1 0011 | 0100 | 0011 |

6 | 1 0010 | 1 0101 | 0110 | 0101 |

7 | 1 0100 | 1 0111 | 1000 | 0111 |

8 | 1 0110 | 1 1001 | 1010 | 1001 |

9 | 1 1000 | 1 1011 | 1100 | 1011 |

a | $5{\mathit{a}}_{\mathit{i}-1}[6-0]$ | ${\mathit{y}}_{\mathit{i}}[3-0]$ | |
---|---|---|---|

${\mathit{a}}_{\mathit{i}}\left[\mathbf{0}\right]=\mathbf{1}$ | ${\mathit{a}}_{\mathit{i}}\left[\mathbf{0}\right]=\mathbf{0}$ | ||

0 | 000 0000 | 0110 | 0011 |

1 | 000 0101 | 0110 | 0011 |

2 | 001 0000 | 0111 | 0100 |

3 | 001 0101 | 0111 | 0100 |

4 | 010 0000 | 1000 | 0101 |

5 | 010 0101 | 1000 | 0101 |

6 | 011 0000 | 1001 | 0110 |

7 | 011 0101 | 1001 | 0110 |

8 | 100 0000 | 1100 | 0111 |

9 | 100 0101 | 1100 | 0111 |

Block | Multiplier 1 (#LUT6) | Multiplier 2 (#LUT6) |
---|---|---|

MultGen(BCD) | 7N | 10N + 7 |

MultGen(BCD/e6) | 8N + 1 | 10N + 7 |

PPG | $8{N}^{2}+11N$ | $6{N}^{2}+8N$ |

PPR | $4\times (\frac{N}{2}\times \u2308lo{g}_{2}N\u2309+{N}^{2}-N)$ | |

Converter (BCD) | 4N | |

BCD Multiplier(BCD) | $12{N}^{2}+18N+2N\u2308lo{g}_{2}N\u2309$ | $10{N}^{2}+18N+7+2N\u2308lo{g}_{2}N\u2309$ |

BCD Multiplier(BCD/e6) | $12{N}^{2}+15N+1+2N\u2308lo{g}_{2}N\u2309$ | $10{N}^{2}+14N+7+2N\u2308lo{g}_{2}N\u2309$ |

**Table 11.**Logic area (LUTs) and delay (ns) of both multipliers with BCD inputs and output for different number of digits in a Virtex-7 FPGA, speed grade -3.

Multiplier 1 | Multipler 2 | |||||
---|---|---|---|---|---|---|

Size | Model | Area | Delay | Model | Area | Delay |

$2\times 2$ | 88 | 88 | 3.56 | 87 | 87 | 4.62 |

$4\times 4$ | 280 | 280 | 4.97 | 255 | 255 | 5.92 |

$8\times 8$ | 960 | 960 | 6.58 | 839 | 839 | 7.96 |

$16\times 16$ | 3488 | 3504 | 8.93 | 2983 | 3001 | 10.22 |

$32\times 32$ | 13,184 | 13,248 | 12.26 | 11,143 | 11,194 | 13.12 |

$34\times 34$ | 14,892 | 14,976 | 13.04 | 12,587 | 12,643 | 13.91 |

**Table 12.**Logic area (LUTs) and delay (ns) of both multipliers with BCD/excess-6 inputs and output for different number of digits in a Virtex-7 FPGA, speed grade -3.

Multiplier 1 | Multipler 2 | |||||
---|---|---|---|---|---|---|

Size | Model | Area | Delay | Model | Area | Delay |

$2\times 2$ | 83 | 83 | 3.02 | 79 | 79 | 3.84 |

$4\times 4$ | 271 | 271 | 4.32 | 239 | 239 | 5.31 |

$8\times 8$ | 943 | 943 | 6.06 | 807 | 814 | 7.23 |

$16\times 16$ | 3455 | 3471 | 8.37 | 2919 | 2937 | 9.31 |

$32\times 32$ | 13,119 | 13,183 | 11.99 | 11,015 | 11,076 | 12.94 |

$34\times 34$ | 14,823 | 14,907 | 12.84 | 12,451 | 12,535 | 13.78 |

**Table 13.**Comparison of the proposed decimal multipliers with state of the art works for different number of digits.

[41] * | [43] * | [42] * | [44] | Multiplier 1 | Multiplier 2 | |||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|

Size | LUTs | Delay | LUTs | Delay | LUTs | Delay | LUTs | Delay | LUTs | Delay | LUTs | Delay |

$2\times 2$ | 82 | 4.2 | — | — | — | — | 91 | 4.2 | 88 | 3.56 | 87 | 4.62 |

$4\times 4$ | 300 | 5.3 | 450 | 5.6 | 365 | 5.6 | 301 | 5.4 | 280 | 4.97 | 255 | 5.92 |

$8\times 8$ | 1128 | 6.9 | 1850 | 8.1 | 1197 | 7.5 | 1065 | 7.0 | 960 | 6.58 | 839 | 7.96 |

$16\times 16$ | 4336 | 9.5 | 6843 | 11.9 | 4088 | 11.5 | 3954 | 8.9 | 3504 | 8.53 | 3001 | 10.22 |

$32\times 32$ | 16,928 | 13.4 | — | — | 13,257 | 18.1 | 15,146 | 14.0 | 13,248 | 12.26 | 11,194 | 13.12 |

$34\times 34$ | 19,197 | 14.2 | — | — | — | — | 17,135 | 14.9 | 14,976 | 13.04 | 12,643 | 13.91 |

**Table 14.**Comparison of the proposed decimal multipliers with state of the art works for different number of digits.

Multiplier 2 | Binary | Comparison | |||||
---|---|---|---|---|---|---|---|

Size (Digits) | LUTs | Delay (ns) | Size (bits) | LUTs | Delau (ns) | Area Ratio | Delay Ratio |

$2\times 2$ | 87 | 4.62 | 7 | 46 | 2.59 | 1.89 | 1.78 |

$4\times 4$ | 255 | 5.92 | 14 | 190 | 3.62 | 1.34 | 1.63 |

$8\times 8$ | 839 | 7.96 | 27 | 720 | 5.11 | 1.16 | 1.56 |

$16\times 16$ | 3001 | 10.22 | 54 | 2899 | 6.88 | 1.04 | 1.49 |

$32\times 32$ | 11,194 | 13.12 | 13.1 | 11,866 | 9.84 | 0.94 | 1.33 |

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**MDPI and ACS Style**

Véstias, M.P.; Neto, H.C. Decimal Multiplication in FPGA with a Novel Decimal Adder/Subtractor. *Algorithms* **2021**, *14*, 198.
https://doi.org/10.3390/a14070198

**AMA Style**

Véstias MP, Neto HC. Decimal Multiplication in FPGA with a Novel Decimal Adder/Subtractor. *Algorithms*. 2021; 14(7):198.
https://doi.org/10.3390/a14070198

**Chicago/Turabian Style**

Véstias, Mário P., and Horácio C. Neto. 2021. "Decimal Multiplication in FPGA with a Novel Decimal Adder/Subtractor" *Algorithms* 14, no. 7: 198.
https://doi.org/10.3390/a14070198