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Convolution Accelerator Designs Using Fast Algorithms

1,2,3,*, 1,2 and 1,2
1
Institute of Acoustics, Chinese Academy of Sciences, Beijing 100190, China
2
Key Laboratory of Information Technology for Autonomous Underwater Vehicles, Institute of Acoustics, Chinese Academy of Sciences, Beijing 100190, China
3
University of Chinese Academy of Sciences, Beijing 100049, China
*
Author to whom correspondence should be addressed.
Algorithms 2019, 12(5), 112; https://doi.org/10.3390/a12050112
Received: 11 March 2019 / Revised: 18 May 2019 / Accepted: 21 May 2019 / Published: 27 May 2019
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Abstract

Convolutional neural networks (CNNs) have achieved great success in image processing. However, the heavy computational burden it imposes makes it difficult for use in embedded applications that have limited power consumption and performance. Although there are many fast convolution algorithms that can reduce the computational complexity, they increase the difficulty of practical implementation. To overcome these difficulties, this paper proposes several convolution accelerator designs using fast algorithms. The designs are based on the field programmable gate array (FPGA) and display a better balance between the digital signal processor (DSP) and the logic resource, while also requiring lower power consumption. The implementation results show that the power consumption of the accelerator design based on the Strassen–Winograd algorithm is 21.3% less than that of conventional accelerators. View Full-Text
Keywords: convolutional neural network; fast convolution; FPGA; Strassen; Winograd convolutional neural network; fast convolution; FPGA; Strassen; Winograd
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Zhao, Y.; Wang, D.; Wang, L. Convolution Accelerator Designs Using Fast Algorithms. Algorithms 2019, 12, 112.

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