# A High Performance Real-Time Simulator for Controllers Hardware-in-the-Loop Testing

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## Abstract

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## 1. Introduction

## 2. CHIL Interfacing Issues

- The original incorrect values calculated without accounting for the switching event [23]: This is the case when the corrective algorithm is initiated at the next timestep since the real-time operation does not permit going back in time to correct the system variables.
- The interpolated values at the switching instant [22]: This is the case when the corrective algorithm is initiated before issuing the outputs.

## 3. FPGA-Based Real-Time Simulator Architecture

- speed, i.e., a computation time in the range of tens to few hundreds of nanoseconds, and
- scalability, i.e., can be expanded to accommodate larger systems without impacting the simulation timestep.

- exploit all possible levels of parallelism inherent to the solution algorithm of the system model, and
- design a customized hardware architecture that closely maps both the solution algorithm and dataflow.

- the first building block is responsible for calculating the node voltages, and
- the second and third building blocks are responsible for updating the history current sources associated with switching and non-switching elements, respectively.

## 4. Interfacing with External Control Platforms

## 5. Case Study: HIL Testing of a Robust Controller for Autonomous Operation of a Distributed Generation Unit

#### 5.1. System Model for Controller Design

V_{dc} | R_{TL} | L_{TL} | R | C | L | R_{L} |
---|---|---|---|---|---|---|

46 kV | 0.8 Ω | 158 mH | 76 Ω | 62 μF | 111.9 mH | 0.1 Ω |

#### 5.2. Robust Servomechanism Controller

**Controller Design Procedure:**Consider the following “cheap control” performance index [44]:

^{th}order strictly proper controller is obtained.

#### 5.3. Hardware-in-the-Loop Setup

**Figure 7.**Photo of the experimental setup: (

**A**) the FPGA-based real-time simulator; (

**B**) the CRIO controller platform; and (

**C**) the oscilloscope.

## 6. Results and Discussions

**Scenario I:**While the system is in the islanded mode with both ${V}_{dref}$ and ${V}_{qref}$ set to zero, ${V}_{dref}$ is stepped up to 6 kV and ${V}_{qref}$ is stepped up to 4 kV. Figure 8 shows an oscilloscope screen capture of the FPGA-based simulation results corresponding to the d and q components of the load voltage, and the phase a and b voltages of the load. Figure 9 and Figure 10 show the d and q components of the load voltage, and the phase a and b voltages of the load obtained from the Matlab/simpowersystems.

**Figure 8.**Oscilloscope screen capture of the d and q components of the load voltage, and the phase a and b voltages of the load.

**Scenario II:**While the system is operating in the islanded mode, in steady state, with ${V}_{dref}=6$ kV and ${V}_{qref}=4$ kV, ${V}_{dref}$ is stepped down to 4 kV and ${V}_{qref}$ is stepped down to 2.667 kV. Figure 11 shows an oscilloscope screen capture of the FPGA-based simulation results corresponding to the d and q components of the load voltage, and the phase a and b voltages of the load. Figure 12 and Figure 13 show the d and q components of the load voltage, and the phase a and b voltages of the load obtained from the Matlab/simpowersystems.

**Figure 11.**Oscilloscope screen capture of the d and q components of the load voltage, and the phase a and b voltages of the load.

**Scenario III:**This scenario demonstrates the controller responses to load switchings, both ON and OFF. While the system is operating in the islanded mode, in steady state, with ${V}_{dref}=6$ kV and ${V}_{qref}=4$ kV, a resistive load of 76 Ω is switched ON. After the system settles to steady state the resistive load is switched back OFF. Figure 14 shows an oscilloscope screen capture of the FPGA-based simulation results corresponding to the d and q components of the load voltage, and the phase a and b voltages of the load. Figure 15 and Figure 16 show the d and q components of the load voltage, and the phase a and b voltages of the load obtained from the Matlab/simpowersystems.

**Figure 14.**Oscilloscope screen capture of the d and q components of the load voltage, and the phase a and b voltages of the load.

#### Discussions

- the delays in the controller outputs imposed by the computation time required by the controller platform to perform the arithmetic calculation of the control algorithm and of the PWM scheme. This delay time is not accounted for in the Matlab/simpowersystems simulation,
- the discretization errors since the Matlab/simpowersystems adopts floating point representation whereas the FPGA-based real-time simulator is based on the fixed point number representation, and
- the errors introduced due to the D/A and A/D converters.

## 7. Conclusions

## Acknowledgements

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**MDPI and ACS Style**

Matar, M.; Karimi, H.; Etemadi, A.; Iravani, R.
A High Performance Real-Time Simulator for Controllers Hardware-in-the-Loop Testing. *Energies* **2012**, *5*, 1713-1733.
https://doi.org/10.3390/en5061713

**AMA Style**

Matar M, Karimi H, Etemadi A, Iravani R.
A High Performance Real-Time Simulator for Controllers Hardware-in-the-Loop Testing. *Energies*. 2012; 5(6):1713-1733.
https://doi.org/10.3390/en5061713

**Chicago/Turabian Style**

Matar, Mahmoud, Houshang Karimi, Amir Etemadi, and Reza Iravani.
2012. "A High Performance Real-Time Simulator for Controllers Hardware-in-the-Loop Testing" *Energies* 5, no. 6: 1713-1733.
https://doi.org/10.3390/en5061713