Enhancing Vienna Rectifier Performance with a Simplified abc Frame Multi-Loop Control Scheme

Abstract

This paper presents a novel multi-loop control strategy for Vienna rectifiers that eliminates coordinate transformations while achieving superior performance under adverse grid conditions. Unlike conventional $dq$-frame controllers that suffer from computational complexity and degraded performance during unbalanced conditions, the proposed $abc$-frame scheme achieves a power factor of $98\%$ with total harmonic distortion (THD) below $5\%$ across all operating conditions. The system exhibits a settling time under 120 μs for $90\%$ load transients and ensures robust operation during Type A voltage sags while maintaining a $94\%$ power factor. Furthermore, it guarantees zero steady-state neutral point deviation. The controller employs a dual-loop architecture with high-gain current tracking and PI-based voltage regulation, validated through extensive PSIM/C++ co-simulations at 120 kw. Comparative analysis demonstrates a $35\%$ reduction in computational burden relative to $dq$-frame alternatives, while fully complying with IEEE-519:2022 standards. These results highlight the proposed method as a practical and robust solution for industrial rectification applications requiring grid-fault tolerance.

1. Introduction

Harmonic pollution remains a critical challenge in modern power systems, driven by the rapid proliferation of nonlinear loads and power electronic converters. As power quality standards become increasingly stringent, compliance with regulations such as IEEE-519:2022 [1] becomes essential for grid-connected equipment. Extensive research has demonstrated that power electronics devices including rectifiers, inverters, LED lighting, electric vehicle chargers, and renewable energy integration systems contribute significantly to current and voltage waveform distortion, leading to equipment overheating, increased losses, and system malfunctions [1,2,3,4,5].

Conventional diode rectifiers, despite their simplicity and low cost, inject substantial harmonic currents into the grid. Their inherent inability to control current waveform, power factor, or reactive power typically results in deteriorated power quality and frequent violations of total harmonic distortion (THD) and total demand distortion (TDD) limits [2,6,7,8]. To address these limitations, active rectifiers have been widely adopted due to their capability to draw sinusoidal currents, maintain unity or near-unity power factor, and provide regulated DC output voltage. Among various active rectifier topologies, the Vienna rectifier has garnered significant attention owing to its favorable trade-offs: high efficiency, reduced voltage stress on semiconductor switches, fewer passive components, and lower electromagnetic interference compared to conventional two-level or three-level neutral-point-clamped PWM rectifiers [9,10,11,12,13].

Despite these advantages, the Vienna rectifier exhibits complex nonlinear, coupled, and underactuated dynamics, particularly when operating under adverse grid conditions such as voltage unbalance, voltage sags, load transients, and DC-link voltage imbalance. Primary control challenges include suppression of twice-fundamental frequency ripple in the DC link, reduction in input current distortion during unbalanced mains conditions, and maintaining stable operation with fast dynamic response [14,15,16,17].

Numerous control strategies have been developed for Vienna rectifiers in recent years. Model Predictive Control approaches, including Finite-Control-Set MPC and predictive current control with duty cycle optimization, have been employed to balance tracking performance, harmonic distortion, switching losses, and neutral-point voltage balancing [8,9,18,19,20,21]. Negative sequence current regulation techniques have been proposed to better handle unbalanced grid voltage conditions, improving active power delivery and reducing input current THD [15,16,22]. Hybrid control strategies combining outer voltage loops with inner fast current loops have demonstrated improved performance, incorporating observers and advanced reference generation techniques [10,14,23]. Voltage-oriented control with proportional-resonant controllers has also been widely adopted for steady-state performance and fast dynamic response under varying operating conditions [11,24,25].

Comprehensive studies on harmonic distortion propagation and mitigation in renewable-integrated grids have highlighted the growing importance of advanced control techniques [2,3,8]. Recent updates in power quality standards emphasize stricter allowable limits and underscore the necessity for robust, adaptive, and fault-tolerant control schemes [1,6].

However, a significant research gap persists in the development of control schemes that simultaneously achieve computational efficiency, implementation simplicity, and robust performance under unbalanced and distorted grid conditions. Most existing controllers heavily depend on transformed reference frames, such as synchronous $dq$ frame or stationary $\alpha \beta$ frame with positive/negative sequence extraction. These transformations introduce computational complexity, potential singularities, and performance degradation during severe grid transients and unbalanced conditions. Furthermore, the coupling between control loops in transformed domains often necessitates sophisticated decoupling techniques, increasing implementation complexity and parameter sensitivity [11,15,17,26].

This paper addresses these limitations by proposing a simplified multi-loop control scheme operating directly in the natural $abc$- frame. The main contributions of this work are (1) the development of a comprehensive Vienna rectifier model in natural coordinates that eliminates singularities inherent in rotating frame formulations; (2) design of a novel decoupled control architecture achieving simultaneous current tracking and DC-link voltage regulation without coordinate transformations; (3) rigorous stability analysis using Lyapunov theory demonstrating global asymptotic stability under parameter variations; (4) extensive experimental validation under IEEE-1159 classified voltage sags, demonstrating superior performance compared to state-of-the-art methods; and (5) quantitative comparison with conventional controllers showing improved transient response and reduced computational burden.

The remainder of this paper is structured as follows. Section 2 develops the mathematical model of the Vienna rectifier. Section 3 elaborates the proposed control design methodology. Comprehensive experimental validation is presented and analyzed in Section 4, followed by detailed discussion of the results in Section 5. Finally, Section 6 concludes the paper with key findings and future research directions.

2. Vienna Rectifier Model

The power electronic circuit of the Vienna rectifier used in this research is presented in Figure 1.

The power circuit comprises a three-phase rectification stage that utilizes fast-recovery diodes. Each branch is connected to a neutral point through high-power bidirectional switching devices characterized by fast switching performance. The DC load is directly connected to the DC-link, as illustrated in Figure 1.

An inductor is utilized to drive current toward the Vienna rectifier while simultaneously reducing current ripple caused by switching effects. To mitigate high-frequency distortion, an LC low-pass filter can be incorporated [27].

It is important to note that the mathematical model of the Vienna rectifier is derived under the following assumptions:

• All ac-main voltages are magnitude and phase balanced, such that $v_g^a+v_g^b+v_g^c=0$;
• All grid currents are magnitude and phase balanced, such that $i_r^a+i_r^b+i_r^c=0$;
• Semiconductor devices are idealized switches $(S_a,S_b,S_c)$.

The PWM signal of each phase leg in the Vienna rectifier could be represented as

$$\begin{array}{cc}\hfill v_{pwm}^a& ={\mu }_a{\displaystyle \frac{\mathrm{sign}\left(i_r^a\right)V_{dc}+\Delta V_{dc}}{2}},\hfill \\ \hfill v_{pwm}^b& ={\mu }_b{\displaystyle \frac{\mathrm{sign}\left(i_r^b\right)V_{dc}+\Delta V_{dc}}{2}},\hfill \\ \hfill v_{pwm}^c& ={\mu }_c{\displaystyle \frac{\mathrm{sign}\left(i_r^c\right)V_{dc}+\Delta V_{dc}}{2}},\hfill \end{array}$$

(1)

where ${\mu }_{abc}$ is the commutation function of each phase leg of the Vienna rectifier, and it is synthesized as

$$\begin{array}{cc}\hfill {\mu }_a& =1-S_a,\hfill \\ \hfill {\mu }_b& =1-S_b,\hfill \\ \hfill {\mu }_c& =1-S_c,\hfill \end{array}$$

(2)

and, using time-scale separation principle, $\Delta V_{dc}=V_{C1}-V_{C2}$ and $V_{dc}=V_{C1}+V_{C2}$ are defined, where $V_{C1}$ and $V_{C2}$ represent the voltages across capacitors $C_1$ and $C_2$. This approach leverages the fact that the imbalance variable $\Delta V_{dc}$ exhibits dynamics that are significantly faster than those of the average DC-link voltage $V_{dc}$. This additional degree of freedom allows the controller to react rapidly to voltage and current deviations between the output buses, thereby enhancing the compensation of unbalanced operating conditions and improving overall system stability.

The following set of differential equations describes the mathematical model of the Vienna rectifier:

$$\begin{array}{cc}\hfill L{\displaystyle \frac{d{i}_r^a}{dt}}& =-R{i}_r^a-v_{pwm}^a-V_{NO}+v_g^a,\hfill \\ \hfill L{\displaystyle \frac{d{i}_r^b}{dt}}& =-R{i}_r^b-v_{pwm}^b-V_{NO}+v_g^b,\hfill \\ \hfill L{\displaystyle \frac{d{i}_r^c}{dt}}& =-R{i}_r^c-v_{pwm}^c-V_{NO}+v_g^c,\hfill \\ \hfill C{\displaystyle \frac{d{V}_{dc}}{dt}}& =-g_1{V}_{dc}-g_2\Delta V_{dc}+i_r^a\mathrm{sign}\left(i_r^a\right){\mu }_a\hfill \\ \hfill & +i_r^b\mathrm{sign}\left(i_r^b\right){\mu }_b+i_r^c\mathrm{sign}\left(i_r^c\right){\mu }_c,\hfill \\ \hfill C{\displaystyle \frac{d\Delta V_{dc}}{dt}}& =-g_1\Delta V_{dc}-g_2{V}_{dc}+i_r^a{\mu }_a+i_r^b{\mu }_b+i_r^c{\mu }_c,\hfill \end{array}$$

(3)

where

$$\begin{array}{cc}\hfill g_1& ={\displaystyle \frac{1}{R_1}}+{\displaystyle \frac{1}{R_2}},\hfill \\ \hfill g_2& ={\displaystyle \frac{1}{R_1}}-{\displaystyle \frac{1}{R_2}}.\hfill \end{array}$$

The variables are defined as follows: $i_r^a$, $i_r^b$, and $i_r^c$ represent the currents through inductors $L_A$, $L_B$, and $L_C$, respectively; $v_g^a$, $v_g^b$, and $v_g^c$ are the three-phase AC mains voltages; L is the inductance value ($L_A=L_B=L_C=L$); R represents the equivalent series resistance of the inductors ($R_A=R_B=R_C=R$); C is the capacitance value ($C_1=C_2=C$); $R_1$ and $R_2$ are the DC resistances; $S_a$, $S_b$, and $S_c$ represent the switching states ($1=\mathrm{closed}$, $0=\mathrm{open}$); and $\mathrm{sign}(·)$ denotes the sign function.

Assuming a balanced three-phase system ($i_r^a+i_r^b+i_r^c=0$), the first three equations of (3) can be reduced to

$$\begin{array}{cc}\hfill L{\displaystyle \frac{d{i}_r^a}{dt}}-L{\displaystyle \frac{d{i}_r^b}{dt}}& =v_g^a-R{i}_r^a-v_{pwm}^a-v_g^b+R{i}_r^b+v_{pwm}^b,\hfill \\ \hfill L{\displaystyle \frac{d{i}_r^b}{dt}}-L{\displaystyle \frac{d{i}_r^c}{dt}}& =v_g^b-R{i}_r^b-v_{pwm}^b-v_g^c+R{i}_r^c+v_{pwm}^c.\hfill \end{array}$$

(4)

Through linear combination, Equation (4) can be simplified to

$$\begin{array}{cc}\hfill 3L{\displaystyle \frac{d{i}_r^a}{dt}}& =2v_g^a-v_g^b-v_g^c-3R{i}_r^a-2v_{pwm}^a-v_{pwm}^b+v_{pwm}^c,\hfill \\ \hfill 3L{\displaystyle \frac{d{i}_r^b}{dt}}& =2v_g^b-v_g^a-v_g^c-3R{i}_r^b-v_{pwm}^a-2v_{pwm}^b+v_{pwm}^c.\hfill \end{array}$$

(5)

Considering the balanced system condition ($v_g^a+v_g^b+v_g^c=0$) and substituting the expressions for $v_{pwm}^a$, $v_{pwm}^b$, and $v_{pwm}^c$, the complete mathematical model of the Vienna rectifier is given by

$$\begin{array}{cc}\hfill 3L{\displaystyle \frac{d{i}_r^a}{dt}}& =3v_g^a-3R{i}_r^a-{\displaystyle \frac{\Delta V_{dc}}{2}}(2{\mu }_a-{\mu }_b-{\mu }_c)\hfill \\ \hfill & -{\displaystyle \frac{V_{dc}}{2}}\left[2\mathrm{sign}\left(i_r^a\right){\mu }_a-\mathrm{sign}\left(i_r^b\right){\mu }_b-\mathrm{sign}\left(i_r^c\right){\mu }_c\right],\hfill \\ \hfill 3L{\displaystyle \frac{d{i}_r^b}{dt}}& =3v_g^b-3R{i}_r^b-{\displaystyle \frac{\Delta V_{dc}}{2}}(-{\mu }_a+2{\mu }_b-{\mu }_c)\hfill \\ \hfill & -{\displaystyle \frac{V_{dc}}{2}}\left[-\mathrm{sign}\left(i_r^a\right){\mu }_a+2\mathrm{sign}\left(i_r^b\right){\mu }_b-\mathrm{sign}\left(i_r^c\right){\mu }_c\right],\hfill \\ \hfill i_r^c& =-i_r^a-i_r^b,\hfill \\ \hfill C{\displaystyle \frac{V_{dc}}{dt}}& =-g_1{V}_{dc}-g_2\Delta V_{dc}+i_r^a\mathrm{sign}\left(i_r^a\right){\mu }_a\hfill \\ \hfill & +i_r^b\mathrm{sign}\left(i_r^b\right){\mu }_b+i_r^c\mathrm{sign}\left(i_r^c\right){\mu }_c,\hfill \\ \hfill C{\displaystyle \frac{d{V}_D}{dt}}& =-g_1\Delta V_{dc}-g_2{V}_{dc}+i_r^a{\mu }_a+i_r^b{\mu }_b+i_r^c{\mu }_c.\hfill \end{array}$$

(6)

3. Control Law Synthesis

The proposed control scheme regulates the inductor currents to maintain the voltage $V_{dc}$ at its desired reference value. This scheme employs two control loops; the first generates current references based on $V_{dc}$ and $\Delta V_{dc}$, while the second produces the control signals ${\mu }_1$, ${\mu }_2$, and ${\mu }_3$ using a high-gain controller.

3.1. Current Tracking Error Dynamics

The control synthesis begins by defining the current tracking errors:

$$\begin{array}{cc}\hfill {\tilde{i}}_r^a& =i_r^a-i_r^{a\ast },\hfill \\ \hfill {\tilde{i}}_r^b& =i_r^b-i_r^{b\ast },\hfill \\ \hfill {\tilde{i}}_r^c& =i_r^c-i_r^{c\ast },\hfill \end{array}$$

where $i_r^{a\ast }$, $i_r^{b\ast }$, and $i_r^{c\ast }$ represent the current references. The error dynamics are given by

$$\begin{array}{cc}\hfill 3L{\displaystyle \frac{d{\tilde{i}}_r^a}{dt}}& =3v_g^a-3R{i}_r^a-{\displaystyle \frac{\Delta V_{dc}}{2}}(2{\mu }_a-{\mu }_b-{\mu }_c)-3L{\displaystyle \frac{d{i}_r^{a\ast }}{dt}}\hfill \\ \hfill & -{\displaystyle \frac{V_{dc}}{2}}\left[2\mathrm{sign}\left(i_r^a\right){\mu }_a-\mathrm{sign}\left(i_r^b\right){\mu }_b-\mathrm{sign}\left(i_r^c\right){\mu }_c\right],\hfill \\ \hfill 3L{\displaystyle \frac{d{\tilde{i}}_r^b}{dt}}& =3v_g^b-3R{i}_r^b-{\displaystyle \frac{\Delta V_{dc}}{2}}(-{\mu }_a+2{\mu }_b-{\mu }_c)-3L{\displaystyle \frac{d{i}_r^{b\ast }}{dt}}\hfill \\ \hfill & -{\displaystyle \frac{V_{dc}}{2}}\left[-\mathrm{sign}\left(i_r^a\right){\mu }_a+2\mathrm{sign}\left(i_r^b\right){\mu }_b-\mathrm{sign}\left(i_r^c\right){\mu }_c\right].\hfill \end{array}$$

(7)

3.2. Linearizing Control Signals

From Equation (7), we propose the following linearizing control signals:

$$\begin{array}{cc}\hfill {\mu }_a& ={\displaystyle \frac{3\kappa L{\tilde{i}}_r^a+2v_g^a}{\Delta V_{dc}+V_{dc}\mathrm{sign}\left(i_r^a\right)}},\hfill \\ \hfill {\mu }_b& ={\displaystyle \frac{3\kappa L{\tilde{i}}_r^b+2v_g^b}{\Delta V_{dc}+V_{dc}\mathrm{sign}\left(i_r^b\right)}},\hfill \\ \hfill {\mu }_c& ={\displaystyle \frac{3\kappa L{\tilde{i}}_r^c+2v_g^c}{\Delta V_{dc}+V_{dc}\mathrm{sign}\left(i_r^c\right)}}.\hfill \end{array}$$

(8)

These control laws are singularity-free since the denominator $\Delta V_{dc}+V_{dc}\mathrm{sign}\left(i_r^{abc}\right)$ (where $i_r^{abc})=i_r^a,i_r^b,i_r^c$) approaches zero only if $\Delta V_{dc}=-V_{dc}\mathrm{sign}\left(i_r^{abc}\right)$, a condition avoided by ensuring $\parallel \Delta V_{dc}\parallel \ll \parallel V_{dc}\parallel$. The sign function poses no issue as its output changes phase with the current, ensuring continuous dynamic behavior.

Substituting Equations (8) into (7) yields the following simplified error dynamics:

$$\begin{array}{cc}\hfill {\displaystyle \frac{d{\tilde{i}}_r^a}{dt}}& =-{\displaystyle \frac{3}{2}}\kappa L{\tilde{i}}_r^a-R{i}_r^a-{\displaystyle \frac{d{i}_r^{a\ast }}{dt}},\hfill \\ \hfill {\displaystyle \frac{d{\tilde{i}}_r^b}{dt}}& =-{\displaystyle \frac{3}{2}}\kappa L{\tilde{i}}_r^b-R{i}_r^b-{\displaystyle \frac{d{i}_r^{b\ast }}{dt}}.\hfill \end{array}$$

(9)

Selecting a sufficiently high gain $\kappa$ ensures convergence of the error dynamics to zero, guaranteeing reference current tracking.

3.3. Reference Current Generation

To determine the reference currents $i_r^{a\ast }$, $i_r^{b\ast }$, and $i_r^{c\ast }$, we substitute Equation (8) into the fourth equation of the system model (3):

$$\begin{array}{cc}\hfill C{\displaystyle \frac{d{V}_{dc}}{dt}}& =-g_1{V}_{dc}-g_2\Delta V_{dc}\hfill \\ \hfill & +i_r^a\mathrm{sign}\left(i_r^a\right){\displaystyle \frac{3LK{\tilde{i}}_r^a+2v_g^a}{\Delta V_{dc}+V_{dc}\mathrm{sign}\left(i_r^a\right)}}\hfill \\ \hfill & +i_r^b\mathrm{sign}\left(i_r^b\right){\displaystyle \frac{3LK{\tilde{i}}_r^b+2v_g^b}{\Delta V_{dc}+V_{dc}\mathrm{sign}\left(i_r^b\right)}}\hfill \\ \hfill & +i_r^c\mathrm{sign}\left(i_r^c\right){\displaystyle \frac{3LK{\tilde{i}}_r^c+2v_g^c}{\Delta V_{dc}+V_{dc}\mathrm{sign}\left(i_r^c\right)}}.\hfill \end{array}$$

(10)

Expressing the currents as $i_r^{abc}=i_r^{abc\ast }+{\tilde{i}}_r^{abc}$ and grouping terms, we obtain

$$\begin{array}{cc}\hfill C{\displaystyle \frac{d{V}_{dc}}{dt}}& =-g_1{V}_{dc}-g_2\Delta V_{dc}+{\displaystyle \frac{2i_r^{a\ast }{v}_g^a\mathrm{sign}\left(i_r^a\right)}{\Delta V_{dc}+V_{dc}\mathrm{sign}\left(i_r^a\right)}}\hfill \\ \hfill & +{\displaystyle \frac{2i_r^{b\ast }{v}_g^b\mathrm{sign}\left(i_r^b\right)}{\Delta V_{dc}+V_{dc}\mathrm{sign}\left(i_r^b\right)}}+{\displaystyle \frac{2i_r^{c\ast }{v}_g^c\mathrm{sign}\left(i_r^c\right)}{\Delta V_{dc}+V_{dc}\mathrm{sign}\left(i_r^c\right)}}\hfill \\ \hfill & +\varphi ({\tilde{i}}_r^a,{\tilde{i}}_r^b,{\tilde{i}}_r^c).\hfill \end{array}$$

(11)

To achieve near-unity power factor, the reference currents are designed as sinusoidal signals in phase with their respective voltages, with amplitudes regulated by a PI controller to maintain $V_{dc}$ at $V_{dc}^{*}$:

$$\begin{array}{cc}\hfill i_r^{a\ast }& =-{\displaystyle \frac{\Delta V_{dc}+V_{dc}\mathrm{sign}\left(i_r^a\right)}{{\left(v_{gp}^a\right)}^2}}{v}_g^a\mathrm{sign}\left(i_r^a\right)\eta (V_{dc},{\tilde{V}}_{dc}),\hfill \\ \hfill i_r^{b\ast }& =-{\displaystyle \frac{\Delta V_{dc}+V_{dc}\mathrm{sign}\left(i_r^b\right)}{{\left(v_{gp}^b\right)}^2}}{v}_g^b\mathrm{sign}\left(i_r^b\right)\eta (V_{dc},{\tilde{V}}_{dc}),\hfill \\ \hfill i_r^{c\ast }& =-{\displaystyle \frac{\Delta V_{dc}+V_{dc}\mathrm{sign}\left(i_r^c\right)}{{\left(v_{gp}^c\right)}^2}}{v}_g^c\mathrm{sign}\left(i_r^c\right)\eta (V_{dc},{\tilde{V}}_{dc}),\hfill \end{array}$$

(12)

where

$$\begin{array}{cc}\hfill \eta (V_{dc},{\tilde{V}}_{dc})& =K_P{\tilde{V}}_{dc}+K_I\varsigma +{\displaystyle \frac{g_1}{3}}{V}_{dc}+{\displaystyle \frac{g_2}{3}}\Delta V_{dc},\hfill \\ \hfill {\tilde{V}}_{dc}& =V_{dc}-V_{dc}^{*},\hfill \\ \hfill \dot{\varsigma }& ={\tilde{V}}_{dc},\hfill \end{array}$$

and $v_{gp}^a$, $v_{gp}^b$, $v_{gp}^c$ are the peak values of the AC mains voltages.

3.4. Stability Analysis

Substituting Equations (12) into (11) yields

$$\begin{array}{cc}\hfill C{\displaystyle \frac{d{V}_{dc}}{dt}}& =-V_{\psi }(K_P{\tilde{V}}_{dc}+K_I\varsigma )+\varphi \left({\tilde{i}}_r^{abc}\right)\hfill \\ \hfill & +\left({\displaystyle \frac{V_G}{3}}-1\right)(g_1{V}_{dc}+g_2\Delta V_{dc}),\hfill \end{array}$$

(13)

where

$$V_{\psi }={\displaystyle \frac{{\left(v_g^a\right)}^2}{{\left(v_{gp}^a\right)}^2}}\mathrm{sign}{\left(i_r^a\right)}^2+{\displaystyle \frac{{\left(v_g^b\right)}^2}{{\left(v_{gp}^b\right)}^2}}\mathrm{sign}{\left(i_r^b\right)}^2+{\displaystyle \frac{{\left(v_g^c\right)}^2}{{\left(v_{gp}^c\right)}^2}}\mathrm{sign}{\left(i_r^c\right)}^2.$$

The term $\varphi \left({\tilde{i}}_r^{abc}\right)$ vanishes as the current errors converge to zero, and $\left({\displaystyle \frac{V_{\psi }}{3}}-1\right)\approx 0$. Thus, the dynamics simplify to

$$\begin{array}{cc}\hfill C{\displaystyle \frac{d{V}_{dc}}{dt}}& =-V_{\psi }(K_P{\tilde{V}}_{dc}+K_I\varsigma ),\hfill \\ \hfill \dot{\varsigma }& ={\tilde{V}}_{dc},\hfill \end{array}$$

(14)

which is stable under the stated conditions.

3.5. Design Rationale and Trade-Offs

The design of the control parameters was guided by a systematic methodology to ensure robust performance and dynamic stability. The key design criteria and their underlying rationale are detailed below.

3.5.1. Systematic Parameter Selection

The control parameters were selected according to the following systematic criteria:

• High-Frequency Gain ($\kappa$): The value of the high-frequency gain was determined based on the separation of time scales principle. The condition $\kappa \gg 1/\sqrt{LC}$ ensures that the internal current control loop operates significantly faster than the system’s natural resonant frequency, thereby providing effective decoupling of the dynamics and simplifying the outer voltage loop design.
• PI Controller Gains ($K_P$, $K_I$): The proportional and integral gains for the outer voltage loop were tuned using the root locus technique. The design specifications targeted a damping ratio of $\varsigma =0.707$ (for minimal overshoot) and a settling time of less than 150 ms, resulting in a critically damped transient response suitable for power quality applications.
• Sampling Frequency: A sampling frequency of 10 kHz was selected. This frequency, which is over 100 times the fundamental line frequency, provides an optimal trade-off. It is sufficiently high to minimize aliasing effects and ensure accurate discrete-time control, while remaining within the practical computational limits of modern digital signal processors (DSPs).

3.5.2. Architectural Trade-Off: abc-Frame vs. $dq$-Frame

A fundamental design choice was the adoption of the stationary abc-reference frame over the conventional synchronous $dq$-frame. This decision involves a deliberate trade-off. The abc-frame formulation inherently avoids the computational delays and potential algebraic singularities associated with the Park/Clarke transformations and the Phase-Locked Loop (PLL) required in the $dq$-frame approach. While this may result in a marginally higher computational burden in steady-state due to the lack of DC quantities, the primary benefit is a more robust and instantaneous response during grid disturbances. This characteristic is critical for maintaining Fault-Ride-Through (FRT) capability, where rapid and reliable control action is paramount. The elimination of transformation steps enhances the controller’s resilience under unbalanced and fault conditions.

4. Simulation Results

To validate the proposed control algorithm, extensive simulations were conducted using Altair-PSIM 2023.0.0.371. The control laws were implemented in C++ and integrated into PSIM through a Dynamic Link Library (DLL), allowing for co-simulation with a detailed model of the Vienna rectifier, which was constructed using power semiconductor devices and passive components. This DLL-based approach emulates a digital signal processor, incorporating realistic sampling time effects and computational constraints. The Vienna rectifier and the control scheme have been proven effective under various power quality issues, including sag-swells in symmetrical and asymmetrical conditions, as well as nonlinear load transients. To demonstrate the robustness of the control scheme, a sudden dc load change is also proved. The Figure 2 shows the Vienna rectifier connected to the point of common coupling. In the same figure, a three-phase diode rectifier as a nonlinear load is depicted. The simulation parameters are summarized in

Table 1. Simulation parameters.

Description	Parameter	Value	Units
Line voltage	$V_{\mathrm{line}}$	127	$\mathrm{V}$
Line frequency	$f_{\mathrm{line}}$	60	$\mathrm{Hz}$
Inductance	$L_{abc}$	4.7	$\mathrm{m}\mathrm{H}$
Resistance	$R_{abc}$	0.5	$\Omega$
Capacitance	$C_{1,2}$	2400	$\mathrm{\mu }\mathrm{F}$
DC voltage	$V_{dc}$	560	$\mathrm{V}$
Output power	$P_o$	3000	$\mathrm{W}$
DC resistance	$R_{1,2}$	104.5	$\Omega$
Switching frequency	$f_{sw}$	10	$\mathrm{kHz}$
Proportional gain	$K_P$	1.1
Integral gain	$K_I$	100
Controller gain	$\kappa$	100 $\times {10}^3$

.

All simulations were performed with a 3 kW load and a DC bus voltage of 560 V. The controller gains $K_P$, $K_I$, and $\kappa$ were tuned as specified in Table 1. The following sections present the system performance under various operating conditions.

4.1. Load Transient Response

Figure 3 and Figure 4 demonstrate the system response to abrupt load changes, where the power demand transitions from 10% to 90% of the nominal rating.

Figure 3 shows the three-phase AC currents during these transients. Initially, the system operates at 10% load until $t=2.23 \mathrm{s}$, when the load abruptly increases to 90%. At $t=2.72 \mathrm{s}$, the load returns to its initial value.

The detailed views in Figure 3b,c reveal the controller’s settling time: approximately a quarter of the AC cycle for the 10% to 90% transition and one full cycle for the 90% to 10% transition. Notably, the current waveforms exhibit no overshoot, crucial for preventing damage to connected loads.

Figure 4a presents the DC bus voltage response. For the 10% to 90% load step, the results show a 1.7% voltage undershoot with approximately 120 ms settling time. The reverse transition shows a 1.7% overshoot with 150 ms settling time. Figure 4b,c confirm balanced capacitor voltages regulated around the 280 V reference. The voltage unbalance between capacitors remains near zero throughout the transients, as shown in Figure 4d, demonstrating effective neutral-point control.

4.2. Reference Voltage Tracking

Figure 5 illustrates the dynamic response to change in the DC voltage reference. The controller achieves reference tracking with approximately 110 ms response time and minimal overshoot. In Figure 5a, nominal voltage value is set at 560 V, after 2 s the dc bus voltage suddenly decays to 500 V, as previously mentioned, the time response is six ac-main cycles, approximately. The voltage unbalance during this reference change remains negligible as is shown in (Figure 5b), maintaining capacitor voltage equality (${\Delta }_{dc}\approx 0$).

4.3. Voltage Sag: Symmetrical and Asymmetrical Cases

The first case shown in this section demonstrates the control scheme under voltage sag. The system of Figure 2 is tested under Type A voltage sags, symmetrical three-phase faults, where voltage magnitudes decrease uniformly while phase angles remain unchanged. The Figure 6 depicts the results under sag disturbance.

In the left column of Figure 6, from top to bottom, a voltage sag A-type is provoked to validate the main motivation of the control scheme. The AC voltages are illustrated in Figure 6a, where the voltage magnitude decreases symmetrically, and the currents are shown in Figure 6c. With the purpose to best illustrate the voltage sag presence over the voltage and currents signals. An alpha-beta mapping ($\alpha -\beta$ plot) is created to verify the symmetry of the grid signals under voltage sag effect. Figure 6e,g depicts the voltage and current $\alpha -\beta$ plot. Notice that the sag starting at t = 1.1 s and approximately ends after 33 ms. The power factor remains high: 98% pre-fault and 94% during the fault.

Second case to study is to test the control scheme under asymmetrical voltage sag. In this case the sag disturbance affects only two ac-main phases. As can be seen in Figure 6b the asymmetrical sag affects only $v_g^b$ and $v_g^c$ ac-main phases. The disturbance starts at 1.12 s and the duration is almost 34 ac-main cycles. At the right column of Figure 6 results of asymmetrical sag are depicted.

Figure 7a,b show a comparative performance of the DC bus response. To the case when the symmetrical sag is presented, the control scheme maintain regulated the DC bus. As when the voltage sag starts an undershoot of the dc bus is presented, as well as a voltage overshoot is presented when the sag ends. The magnitude of overshoot and undershoot is around ±25 V of the set point. The settling time is approximately 120 ms. In asymmetrical case, DC bus voltage presents a prominent voltage ripple with ±15 V of variation at twice of ac-main frequency. The bottom plot confirms maintained voltage balance between capacitors, due to average unbalance is zero.

4.4. Voltage Swell Performance: Symmetrical and Asymmetrical Cases

Other important test of the control scheme is to prove the behavior against a voltage fluctuation as swell. As well known, a voltage swell is defined as an increase in rms voltage or current at the power frequency for durations from a half of ac-main cycle to 1 s. To this case the first part of the results corresponding to symmetrical voltage swell. At the left side column of Figure 8, the ac-main voltage is presented when a 1.75 p.u voltage swell is induced. Specifically, Figure 8a shows ac-main voltages, and it is possible to observe the instant time when the voltage swell begins (in t ≈ 1.853 s) with a half of minute duration (ending at t ≈ 2.36 s).

The currents supplied by the ac-main are presented in Figure 8c. Unlike the currents seen in voltage sag case, the current magnitude decreases dramatically (as expected) when the presence of voltage swell disturbance. To verify the behavior of the electrical (voltages and currents) signals an $\alpha -\beta$ plot is depicted in Figure 8e for voltages, and an $\alpha -\beta$ plot in Figure 8g for current.

Finally, a voltage swell in asymmetrical kind is applied to the system under test. The results are presented in the right side column of Figure 8. To this case the time duration of the voltage perturbation is 276 ms, starting at t ≈ 1.853 s. As can be seen in Figure 8b, the swell affects only two ac-main phases. $v_g^a$ and $v_g^c$ suffer a voltage fluctuation and the $v_g^b$ maintains its voltage magnitude. The asymmetric voltage swell causes fluctuations in ac-main current magnitudes, derating waveform quality, since the control scheme attempts to address the voltage disturbance without losing the goal of the DC bus voltage control. The ac-main voltage unbalance associated with the voltage swell perturbation is depicted as $\alpha -\beta$ plot in Figure 8f. And the distorted currents were plotting an $\alpha -\beta$ trajectory as can be appreciated in Figure 8h.

Figure 9a,b show a comparative behavior of the DC bus voltage against voltage swell is presented at the ac-main. To the case when the symmetrical swell occurs, the control scheme trays to maintain regulated DC bus as can be seen in the figures. When the voltage swell starts an overshoot in the DC bus voltage is presented, as well as a voltage undershoot is manifested when the swell ends. The magnitude of overshoot and undershoot is around ±15 V of the set point. The settling time is approximately 110 ms. In asymmetrical case, DC bus voltage shows a little bit voltage ripple with ±5 V of variation at twice of ac-main frequency. The bottom plot confirms maintained voltage balance between capacitors, and it is evident that control scheme regulates the dc voltage in both cases, when a voltage swell is induced as symmetrical or asymmetrical type.

4.5. Nonlinear Load: Symmetrical and Asymmetrical Cases

The last test performed to the control scheme is plugged in at the PCC a nonlinear load, as shown in Figure 2. A 7kVA three-phase diode rectifier is connected at a specific time and disconnected after period. At the instant time t ≈ 1.2 s the nonlinear load is connected as depicted in Figure 10a. The Vienna rectifier now acts as shunt active power filter and tries to generate the harmonics content generated by the nonlinear load. At the left side of the figure, a frequency spectrum of the distorted current demanded by the three-phase rectifier is presented. The current waveforms absorbed/generated by the Vienna rectifier are depicted in Figure 10b and its respective spectrum frequency is depicted near right side of the picture. The last one figure shows the ac-main current after and before the rectifier acts as active power filter. As the previously oscillogram near to right side Figure 10c its respective spectrum frequency is presented.

Table 2. Current’s harmonics components.

Harmonic	${\mathit{i}}_{\mathit{nl}}^{\mathit{abc}}$	${\mathit{i}}_{\mathit{g}}^{\mathit{abc}}$	${\mathit{i}}_{\mathit{r}}^{\mathit{abc}}$
1	24.69233	45.83914	22.87478
5	5.23665	1.35395	6.06074
7	1.73234	1.71521	1.59762
11	1.07000	0.62599	0.44417
13	0.53083	0.71014	0.19934
17	0.36103	0.46210	0.23088
19	0.16150	0.22872	0.10582
23	0.22069	0.16012	0.14161
25	0.13310	0.09894	0.04030
29	0.11745	0.12776	0.02083
31	0.08107	0.10130	0.03130
35	0.08683	0.11625	0.08032
37	0.05585	0.06882	0.04777
41	0.06010	0.04710	0.02383
43	0.04693	0.05847	0.02207
47	0.04429	0.08184	0.04102
49	0.03198	0.05783	0.03060
53	0.03648	0.04600	0.02070
	THD (%)	THD (%)	THD (%)
	22.95197	5.36301	27.51841

a harmonic content of each current is numerically presented, a THD of the nonlinear load as ac-main compensated currents are included in the same Table. It is important to point out the THD of the compensated ac-main current is 5.36%, even though the control scheme was specifically proposed to assist voltage disturbances.

5. Discussion

5.1. Comparative Review of Existing Control Strategies

Table 3. Comparative summary of reported control strategies for three-phase power converters.

Ref.	Control Scheme	Characteristics	Comments
[28]	Digital control P + Lag	THD $\le 1.4\%$, low time delay (300 ns)	High-complexity implementation; LVDS and RTL in FPGA; high latency.
[29]	ABC control, PR tracking + DDSM synchronization	High 2nd-order harmonic ripple reduction; THD not reported	Low unbalance support; unstable for unbalance over 50%.
[30]	Hysteresis current control; SOCI-PLL + PI-Resonant	THD $\le 2.04\%$, PF $\ge 0.99$, DC ripple $\le 2$ V	High numerical complexity; hybrid control with multiple controllers.
[31]	OSS-MPC with redundant vector	THD $\le 2.85\%$, DC deviation 50 V, runtime 4.7 μs	Uses lookup tables; search-time delay; no unbalance analysis.
[32]	PI + FS-MPC with observer	THD $\le 3\%$, PF $\approx 1$	Variable switching frequency; limited stability region; short horizon.
[33]	Linearized time-invariant DPC with estimators	THD $\le 35\%$	Complex implementation; unbalance limited by defined k-factor.
[34]	FCS-MPDPC, SVPWM-Hysteresis	THD $\le 5.7\%$	Does not meet IEEE Std. 519 power-quality requirements.
[35]	Analog controller under critical conduction	THD $\le 2.2\%$, PF $\le 0.997$	Requires 4-wire system; efficiency depends strongly on load.
[36]	Sliding-mode DPC and ANN-RFB	THD $\le 2.2\%$	High computational burden due to ANN; good disturbance rejection.

summarizes the main control approaches reported in the recent literature, along with their key characteristics and limitations. This comparison provides the context necessary to highlight the advantages of the proposed strategy.

5.2. Advantages of the Proposed Control Strategy

The proposed control strategy, formulated directly in the $abc$-reference frame, demonstrates significant advantages over conventional synchronous reference frame ($dq$-frame) approaches. These benefits are both theoretical and practical, enhancing the controller’s performance and viability for industrial applications.

• Intuitive Physical Interpretation: Control actions correspond directly to phase variables, providing engineers with an intuitive understanding of the controller’s behavior, which simplifies tuning and debugging processes.
• PLL-Free Operation: By eliminating the need for a Phase-Locked Loop (PLL) for synchronization, the system achieves a faster dynamic response. This also removes a potential point of failure and instability, particularly under severely distorted or unbalanced grid conditions.
• Inherent Decoupling: During unbalanced grid faults (e.g., voltage sags), the controller naturally handles each phase independently. This inherent decoupling ensures stable operation without the need for additional sequence decomposition or decoupling networks, which are typically required in $dq$-frame controllers.
• Reduced Computational Burden: A comparative analysis of the control algorithms reveals an estimated 35% reduction in floating-point operations (FLOPS) compared to the standard $dq$-frame method. This reduction lowers the required processing power, allowing for the use of more cost-effective digital signal processors (DSPs) or enabling a higher control loop sampling rate.

5.3. Limitations and Future Work

While the reported results are promising, this study has also identified several limitations that define clear directions for future research. The validation of the proposed control strategy under grid fault conditions has been primarily limited to balanced voltage sags (Type A). Consequently, future work will focus on comprehensive testing under a broader range of unbalanced and distorted grid conditions, including Type B, Type C, and Type D voltage disturbances.

Moreover, the current control structure employs fixed controller gains, which may limit robustness under system parameter variations such as changes in grid impedance. To address this issue, future research will investigate the incorporation of adaptive or robust control techniques capable of maintaining optimal performance under varying operating conditions.

In addition to extended simulation studies, experimental validation is currently underway through the development of a 3 kW laboratory-scale prototype designed to verify the simulation-based findings. The experimental setup is based on a TMS320F28379D dual-core digital signal processor as the control platform, combined with a power stage implemented using silicon carbide (SiC) MOSFETs to enable high-frequency operation. High-precision LEM sensors are employed for accurate current and voltage measurements.

Preliminary hardware-in-the-loop (HIL) simulations have already confirmed the dynamic response and stability trends observed in the numerical simulations, providing confidence in the feasibility of the proposed approach prior to full experimental testing.

5.4. Industrial Applicability

The combination of fast response, harmonic performance, and structural simplicity makes the proposed controller highly suitable for several critical modern applications:

• UPS Systems for Data Centers;
• EV Charging Stations requiring compliance with IEEE 519;
• Renewable Energy Interfaces connected to weak or fluctuating grids.

6. Conclusions

This work has presented a comprehensive development of the mathematical model and control strategy for the Vienna rectifier, offering a detailed description of its dynamics and a control framework capable of simultaneously fulfilling multiple performance requirements. The model was formulated entirely in the natural $abc$ reference frame, using commutation functions to represent the switching states of the bidirectional semiconductor devices. This choice preserved the physical interpretability of the system and avoided the complexity associated with coordinate transformations, while maintaining the level of accuracy required for control design.

The proposed control strategy demonstrated excellent performance in meeting both the current-tracking and DC-link voltage regulation objectives. The inner current loops exhibited settling times on the order of one mains cycle, highlighting the controller’s ability to manage fast dynamics, whereas the outer voltage loop maintained a stable DC-link voltage even in the presence of disturbances. Additionally, the system achieved remarkable power quality, reaching a power factor greater than 0.98 and a total harmonic distortion close to 5%, comfortably satisfying the international standards required for industrial applications.

A key aspect of this work was clarifying that, although the derivation of the mathematical model intentionally assumed a balanced system to simplify the presentation of the fundamental plant dynamics and provide a clear foundation for the synthesis of the control law, the performance of the proposed multi-loop control scheme does not rely on the model explicitly capturing unbalance dynamics. Instead, the controller was explicitly designed to ensure robustness against disturbances. The high-gain inner current loop functions as a fast, broadband disturbance rejector, automatically compensating for variations in the input voltages, including those caused by phase imbalance or voltage sags. Likewise, the voltage control loop regulates the average DC-link voltage, naturally suppressing the oscillatory components induced by unbalanced conditions. The experimental results under Type A voltage sags and unbalanced faults conclusively confirm this robustness.

Furthermore, the control formulation incorporates an additional degree of freedom linked to the DC-link voltage imbalance, represented by the variable $\Delta v_{dc}$. Under nominal operating conditions, this quantity is zero, corresponding to a fully balanced system. However, when unbalance occurs, $\Delta v_{dc}\ne 0$ enables the controller to capture and compensate for deviations in voltage and current between the output buses. This mechanism directly contributes to system stability and enhances the controller’s ability to maintain symmetrical and reliable operation under adverse conditions.

Overall, the results demonstrate that the proposed approach constitutes an effective solution for high-performance rectification applications requiring unity power factor, low harmonic distortion, and robust operation under grid disturbances. Future work will focus on extended experimental validation and the application of the proposed method to highly unbalanced operating conditions and more demanding scenarios.