Topology and Control of Current-Fed Quadruple Active Bridge DC–DC Converters for Smart Transformers with Integrated Battery Energy Storage Systems

Abstract

Smart transformers (STs), which are power electronic-based transformers with control and communication capabilities, facilitate managing future distribution grids with distributed generators (DGs) and battery energy storage systems (BESSs). This paper presents a current-fed quadruple active-bridge (CF-QAB) DC–DC converters-based cascaded H-bridge (CHB) ST architecture in which it is easy to coordinate the system-level power transmission and distribution. Compared with the QAB/DAB + Boost baseline, this topology achieves a reduction of approximately 20% in device count. For the core component of the proposed ST architecture, the operation principles are illustrated and the small-signal model is derived. Based on that, the control system obtained by using the individual channel design method is proposed to decouple the highly coupled LV and BESS DC ports, which significantly simplify the control system structure and design process. The experimental results are shown to validate the effectiveness of the proposed DC–DC converter and associated control system.

1. Introduction

World-wide renewable energy resources (RESs) are growing significantly in recent years, which helps in overcoming environmental concerns and energy crises. As the main forms of RES, lots of wind and photovoltaic (PV) distributed generators (DGs) have been installed. However, the intermittent nature of wind and PV DGs poses serious challenges to the stability and reliability of the electric grid [1,2]. In this regard, battery energy storage systems (BESSs) are commonly used to compensate sudden power variations from the DGs, to store the surplus DG power, and to meet the extra load demands during peak hours [3,4]. A low-cost and high-reliability solution for high-power quality photovoltaic power stations (such as distributed rooftop photovoltaics and microgrids) by incorporating battery/supercapacitor storage and a novel ten-switch inverter is provided in [5]. Figure 1a shows the conventional distribution electric grid with DGs and BESSs, where the low-frequency transformers are used as the energy exchange interfaces between the DGs, BESSs, and the grid.

However, the conventional distribution electric grid lacks the power flow control capability and the convenient DC interfaces and therefore cannot meet the operational requirements of future power systems [6]. The smart transformers (STs), which are electronic power-based transformers equipped with effective control and communication features, show high potential to improve the power control and energy management performance of multi-source systems [7,8]. Therefore, combining STs with BESSs can meet the operational and functional requirements of the future distribution electric grids.

Regarding to the ST architectures, numerous works have been reported, which are mainly classified into three categories according to the number of power stages: single-, two- and three-stage STs [9]. Compared with the single- or two-stage architecture, the three-stage ST architecture can not only guarantee power decoupling between the medium voltage (MV) side and low voltage (LV) side but can also offer AC and DC interfaces for various kinds of power sources and loads. Therefore, the three-stage ST architecture is considered as the most suitable candidate for ST implementation and application in the distribution electric grid. References [10,11,12] show several typical three-stage ST architectures, which consist of MV AC–DC rectifiers, isolated DC–DC converters and LV DC–AC inverters. The available converters in the AC–DC stage include NPCs, Cascaded H-bridge (CHB) converters, Modular Multilevel Converters (MMCs), etc. In the isolation stage, there are more options, e.g., dual-active bridge (DAB), single-active bridge (SAB), series resonant converter (SRC), CLLC resonant converter, CF-DAB converter, etc., [13,14,15,16].

Based on the three-stage ST architectures, the BESSs in the distribution electric grid can be connected to the available MV or LV DC-link. Figure 1b shows a typical example, where the BESSs are connected to the LV DC-link of the ST through DC–DC converters. References [17,18] discussed power flow control and energy management in the three-stage ST architectures with the integration of BESSs through the DC-link. However, the above architectures need additional hardware circuits to integrate the BESSs, which increases the system volume and cost. Moreover, the power coordination and cooperation between the STs and BESS converters are necessary, which increases the communication and control system complexity.

In this paper, the architecture of STs integrated with BESSs in the distribution electric grid is presented and shown in Figure 1c, where the typical ST configuration and DC–DC converters are shown in Figure 2 and Figure 3, respectively. Compared with the conventional one in Figure 1b, the architecture in Figure 1c can provide additional DC ports to integrate BESSs in the isolated DC–DC stage, which completely eliminates the need for a specific DC–DC converter for the BESSs. Therefore, the proposed architecture decreases system volume and cost. Additionally, the system-level power flow control and energy management capacity are improved due to centralized control capability. However, for the control system of the DC–DC converter with consideration of the highly coupled relationship between the LV port and the BESS port, the control parameter design in the control system is complicated. Although the system can be divided into several single-input/single-output (SISO) subsystems by using a decoupling matrix, the process of solving the decoupling matrix is complex [19]. Thus, a control system for the DC–DC stage based on an individual channel design method is proposed, which significantly simplifies the structure of the control system. Therefore, the stability and controller parameter tuning can be accurately analyzed by using the Bode and Nyquist diagram techniques of the classical control theory.

This paper is organized as follows. In Section 2, the ST architectures are presented, the detailed operation principles are analyzed, and the losses and efficiency are analyzed and compared with other traditional structures. In Section 3, the small-signal models of the DC–DC converters are derived and the control system is designed. The experimental results are presented to verify the effectiveness of the proposed architecture and control system in Section 4. Finally, the conclusions are discussed.

2. Proposed Smart Transformer Architectures

2.1. Topology of the CF-QAB Converters

Figure 2 shows the typical ST architecture. In the AC-DC stage, the cascaded H–bridge (CHB) multilevel converter with n H-bridge cells is adopted. The output voltages of n H-bridge cells in series can synthesize a 2n + 1 level inverter output voltage, which enables the CHB converter available to be directly connected to the medium voltage (MV) grid e_j (j ∈ {A, B, C}) through the smoothing inductor L_g. i_A, i_B, and i_C are the three-phase grid currents.

The typical DC–DC stage, which is composed of current-fed quadruple active-bridge (CF-QAB) DC–DC converters, is depicted in Figure 3. Each CF-QAB converter has four AC ports formed by four active bridges, where v_MVA, v_MVB, v_MVC, and v_LVac are the AC output voltages of the MV active bridges AB_A, AB_B, AB_C, and the LV active bridge AB_LV; L_MVA, L_MVB, L_MVC, and L_LV are the inductors connected to corresponding AC ports; i_MVA, i_MVB, i_MVC, and i_LV are the windings of the high-frequency transformer N_A, N_B, N_C, and N_LV. Additionally, each CF-QAB converter has five DC ports: three MV DC ports connected to the DC-links of H-bridge cells (HB_A, HB_B, HB_C) that respectively belong to phase A, B, and C, one LV DC port connected to the LV DC bus and one battery port connected to the midpoints of the leading leg and lagging leg of the active bridge AB_LV through the inductors L_b1 and L_b2. i_b1 and i_b2 are the currents flowing through the inductors L_dc1 and L_dc2. C_bat and v_bat are the battery port capacitor and capacitor voltage. v_MV and v_LV are the MV and LV DC port voltages, while V_MV and V_LV are the corresponding port reference voltages.

According to the location relationship between the AC output voltages of the arbitrary MV active bridge AB_j and the LV active bridge AB_LV, the operation states can be divided into four modes. The corresponding AC output voltage and current waveforms in each mode are depicted in Figure 4, where duty cycle D varies from [0, 1] and D^T is equal to min {D, 1 − D}. v’_MVj is the output voltage of the active bridge AB_j referred to the LV side, which is a three-level AC square wave with duty cycle D^T, magnitude V’_MVj = V_MVN_LV/N_j, and phase-shift angle Φ_j. v_LVac is the output voltage of active bridge AB_LV with duty cycle D^T, magnitude V_LV, and phase-shift angle Φ_LV. The phase-shift angle Φ_jLV is equal to Φ_j−Φ_jLV. i_jLV is the current flowing through L_LV, which is produced by the active bridge AB_j and the LV active bridge AB_LV. Practically, the value of D is usually limited within 0.25–0.75 in order to achieve high efficiency, while Φ_jLV is usually smaller than π/3 for low circulating loss. Therefore, the CF-QAB converters will mainly operate in mode I and II.

The power transmission mechanism can be illustrated by the Y-model circuit of CF-QAB converters in Figure 5a, where L_m and L’_MVj are the equivalent magnetizing inductor and the equivalent MV inductor referred to the LV side, respectively. v^l_LV and v^r_LV are the voltages of the left and right legs in the LV active bridge AB_LV. Here, if the MV active bridge AB_j is selected as the sending power port and the LV active bridge AB_LV is selected as the receiving power port, then according to Thevenin’s Theorem, the equivalent circuit between AB_MVj and AB_LV can be obtained as shown in Figure 5b, where L_jLV is the corresponding Thevenin-equivalent inductance and v’_MVj(th) is the corresponding Thevenin-equivalent voltage with magnitude V’_MVj(th). Since the inductor current is periodic and symmetrical over a switching cycle, the initial value of the current flowing through L_jLV i_jLV(0) can be derived and then the instantaneous inductor current i_jLV(θ) over a half switching cycle can be obtained. Finally, the transferred power P_jLV from AB_j to AB_LV can be calculated through the following.

$$P_{j\mathrm{LV}}={\displaystyle \frac{1}{2\pi }}{\displaystyle \underset{0}{\overset{2\pi }{\int }}{v}_{\mathrm{LV}}(\theta )}\cdot i_{j\mathrm{LV}}(\theta )d\theta$$

(1)

Based on the superposition theorem, the resulting total current flowing through L_LV and the total transferred power P_tot into AB_LV can be obtained based on the above analysis for single MV active bridge and the LV active bridge. For simplicity, assuming that N_A = N_B = N_C = N_LV, L_MVA = L_MVB = L_MVC = L_LV = L ≪ L_m, and Φ_ALV = Φ_BLV = Φ_CLV = Φ, the total transferred power from MV active bridges to LV active bridges P_tot can be simplified as P_{tot_s}. The key variables and calculation results in the above analysis are given and summarized in

Table 1. The initial current and transferred power in four modes.

Mode	Initial Current ijLV(0)	Total Transferred Power Ptot	Simplified Transferred Power Ptot_s
I	$-{\displaystyle \frac{\left(V_{\mathrm{MV}j(\mathrm{th})}^{’}-V_{\mathrm{LV}}\right)}{\omega L_{j\mathrm{LV}}}}{D}^{\mathrm{T}}\pi$	${\displaystyle \sum _{j=\mathrm{A},\mathrm{B},\mathrm{C}}\frac{V_{\mathrm{MV}j}^{’}{V}_{\mathrm{LV}}}{\omega L_{j\mathrm{LV}}}{\varphi }_{j\mathrm{LV}}}\left(2D^{\mathrm{T}}-{\displaystyle \frac{{\varphi }_{j\mathrm{LV}}}{2\pi }}\right)$	${\displaystyle \frac{3V_{\mathrm{MV}}{V}_{\mathrm{LV}}}{4\omega L}}\varphi \left(2D^{\mathrm{T}}-{\displaystyle \frac{\varphi }{2\pi }}\right)$
II	$-{\displaystyle \frac{V_{\mathrm{LV}}\left(\varphi -\pi \right)+\left(V_{\mathrm{MV}j(\mathrm{th})}^{’}+V_{\mathrm{LV}}\right)D^{\mathrm{T}}\pi }{\omega L_{j\mathrm{LV}}}}$	${\displaystyle \sum _{j=\mathrm{A},\mathrm{B},\mathrm{C}}\frac{V_{\mathrm{MV}j}^{’}{V}_{\mathrm{LV}}}{\omega L_{j\mathrm{LV}}}\left[{\varphi }_{j\mathrm{LV}}\left(1-\frac{{\varphi }_{j\mathrm{LV}}}{\pi }\right)-\frac{\pi }{2}{\left(1-2D^{\mathrm{T}}\right)}^2\right]}$	${\displaystyle \frac{3V_{\mathrm{MV}}{V}_{\mathrm{LV}}}{4\omega L}}\left[\varphi \left(1-{\displaystyle \frac{\varphi }{\pi }}\right)-{\displaystyle \frac{\pi }{2}}{\left(1-2D^{\mathrm{T}}\right)}^2\right]$
III	$-{\displaystyle \frac{V_{\mathrm{LV}}\left(\varphi -\pi \right)+\left(V_{\mathrm{MV}j(\mathrm{th})}^{’}+V_{\mathrm{LV}}\right)D^{\mathrm{T}}\pi }{\omega L_{j\mathrm{LV}}}}$	${\displaystyle \sum _{j=\mathrm{A},\mathrm{B},\mathrm{C}}\frac{V_{\mathrm{MV}j}^{’}{V}_{\mathrm{LV}}}{\omega L_{j\mathrm{LV}}}\left(\pi -{\varphi }_{j\mathrm{LV}}\right)\left[\frac{{\varphi }_{j\mathrm{LV}}}{2\pi }-\left(\frac{1}{2}-2D^{\mathrm{T}}\right)\right]}$	${\displaystyle \frac{3V_{\mathrm{MV}}{V}_{\mathrm{LV}}}{4\omega L}}\left(\pi -\varphi \right)\left[{\displaystyle \frac{\varphi }{2\pi }}-\left({\displaystyle \frac{1}{2}}-2D^{\mathrm{T}}\right)\right]$
IV	$-{\displaystyle \frac{\left(V_{\mathrm{MV}j(\mathrm{th})}^{’}-V_{\mathrm{LV}}\right)}{\omega L_{j\mathrm{LV}}}}{D}^{\mathrm{T}}\pi$	${\displaystyle \sum _{j=\mathrm{A},\mathrm{B},\mathrm{C}}\frac{2V_{\mathrm{MV}j}^{’}{V}_{\mathrm{LV}}}{\omega L_{j\mathrm{LV}}}\pi {\left(D^{\mathrm{T}}\right)}^2}$	${\displaystyle \frac{3V_{\mathrm{MV}}{V}_{\mathrm{LV}}}{2\omega L}}\pi {\left(D^{\mathrm{T}}\right)}^2$
$\begin{array}{c}{L}_{\mathrm{MV}j}^{’}={\left({\displaystyle \frac{N_{\mathrm{LV}}}{N_j}}\right)}^2{L}_{\mathrm{MV}j}, V_{\mathrm{MV}j}^{’}={\displaystyle \frac{N_{\mathrm{LV}}}{N_j}}{V}_{\mathrm{MV}j}\\ L_{j\mathrm{LV}}=\left[{\left({\displaystyle \frac{1}{L_{\mathrm{m}}}}+{\displaystyle \sum _{k=\mathrm{A},\mathrm{B},\mathrm{C}}\frac{1}{L_{\mathrm{MV}k}^{’}}}\right)}^{-1}+L_{\mathrm{LV}}\right]\left[L_{\mathrm{MV}j}^{’}\left({\displaystyle \frac{1}{L_{\mathrm{m}}}}+{\displaystyle \sum _{\begin{array}{c}k\ne j\\ k=\mathrm{A},\mathrm{B},\mathrm{C}\end{array}}\frac{1}{L_{\mathrm{MV}k}^{’}}}\right)+1\right], V_{\mathrm{MV}j(\mathrm{th})}^{’}=\left[L_{\mathrm{MV}j}^{’}\left({\displaystyle \frac{1}{L_{\mathrm{m}}}}+{\displaystyle \sum _{\begin{array}{c}k\ne j\\ k=\mathrm{A},\mathrm{B},\mathrm{C}\end{array}}\frac{1}{L_{\mathrm{MV}k}^{’}}}\right)+1\right]V_{\mathrm{MV}j}^{’}\end{array}$

.

2.2. Comparison and Analysis of Losses and Efficiencies with Other Converters

From the perspective of converter topology, the typical converter topologies (DABs + Boost Converter and QAB + Boost Converter) and the proposed topology (CF-QAB) are shown in Figure 6a–c. Assuming the medium-voltage side voltage is 10 kV, the low-voltage side voltage is 800 V, and the total transmission power is 450 kW, the three different converter topologies mentioned above are adopted as sub-modules. The input voltage of each sub-module port is 800 V. Each sub-module is designed to have a transmission power of 90 kW. The input ports of the module are connected in series and linked to the medium-voltage side voltage through a cascade H-bridge (CHB) structure, and the device selection is as shown in

Table 2. The main devices of different converters (“*” indicates the quantity of devices).

	Converter	DAB + Boost Converter	QAB + Boost Converter	CF-QAB Converter (The Proposed Converter)
Device
Power Semi-conductor Device	MV side MOSFET	C2M0040120D*12	C2M0040120D*12	C2M0040120D*12
	LV side MOSFET	C2M0040120D*12	C3M0016120K1*4	C3M0016120K1*4
	interleaved Boost converter	C2M0040120D*4	C3M0016120K1*4
High-frequency Transformer	Core Type	EE185/80/27	EE240/118/40	EE240/118/40
	Core Material	LP3A	LP3A	LP3A
	Wire Type	8076/20AWG	8076/20AWG	8076/20AWG
	Number of Winding Turns	49:49	32:32	32:32
	Number of Coil Strands	31:31	25:76	25:76
Inductor Components	Core Type	EE55/28/21	EE85/45/31	EE85/45/31
	Core Material	LP3A	LP3A	LP3A
	Winding Wire Type	20AWG	20AWG	20AWG
	Number of Winding Turns	48	62	62
	Number of Coil Strands	31	76	76
Inductor Components in interleaved Boost converter	Core Type	EE65/32/27	EE65/32/27	EE55/28/21
	Core Material	LP3A	LP3A	PC44
	Winding Wire Type	24AWG	24AWG	18AWG
	Number of Winding Turns	40	40	110
	Number of Coil Strands	34	34	7
Capacitor	Voltage-Stabilizing Capacitor	SNAJ50471M450BK
Cooling System	Heat Sink(511-9U/228*132)

.

From the topological structure and the above table, it can be seen that the converter proposed in this paper reduces the number of switching tubes compared with the other two converters. Compared with the DAB + Boost converter, it reduces the number of transformers and decreases the size, cost, and volume of the converter. Next, the losses of the three types of converters will be calculated, respectively. The losses of the converters mainly consist of the losses of the switching devices and the losses of the transformers and the inductive components. The losses of the switching devices include on-state losses, turn-on losses, and turn-off losses. The calculation formulas are, respectively, shown as (2) and (3). The losses of transformers and inductive components include winding copper loss and core loss. The calculation formulas are as shown in (4). Since all three converters can achieve MOSFET ZVS (Zero Voltage Switching) turn-on, there is no turn-on loss. The values of other actual parameters needed for reproduction, such as Id_off, tf, and Steinmetz coefficients, can be found in Appendix B Table A1.

$$\{\begin{array}{c}{P}_{\mathrm{sw}\_\mathrm{on}}={\displaystyle \frac{C_{\mathrm{D}}{V_{\mathrm{D}}}^2}{2}}\cdot f_{\mathrm{sw}}+{\displaystyle \frac{1}{2}}{V}_{\mathrm{D}}{I}_{\mathrm{on}}\left(t_{\mathrm{d}\_\mathrm{on}}+t_{\mathrm{r}}\right)\cdot f_{\mathrm{sw}}\\ P_{\mathrm{sw}\_\mathrm{off}}={\displaystyle \frac{1}{2}}{V}_{\mathrm{D}}{I}_{\mathrm{off}}\left(t_{\mathrm{d}\_\mathrm{off}}+t_{\mathrm{f}}\right)\cdot f_{\mathrm{sw}}\end{array}$$

(2)

C_D represents the output capacitance of the switch, I_on represents the current at the switch turn-on time, I_off represents the current at the switch turn-off time, I_{d_on} represents the turn-on delay time, I_{d_off} represents the turn-off delay time, t_r represents the rise time, t_f represents the fall time, and V_D represents the voltage value after the switch is turned off.

$$P_{\mathrm{cond}}={I_{\mathrm{rms}}}^2\cdot R_{\mathrm{on}}$$

(3)

I_rms represents the RMS value of the current flowing through the switch. R_on represents on-resistance.

$$\{\begin{array}{c}{P}_{\mathrm{copper}}=I_{\mathrm{m}\_\mathrm{rms}}\cdot R_{\mathrm{m}}\\ P_{\mathrm{core}}=k\cdot {f_{\mathrm{sw}}}^{\alpha }\cdot {B_{\mathrm{T}}}^{\beta }\cdot V_{\mathrm{e}}\end{array}$$

(4)

I_{m_rms} represents the RMS current flowing through the magnetic element, R_m corresponds to the AC impedance in the magnetic element. k, α, and β are Steinmentz coefficients, B_T represents the maximum change in magnetic induction, and V_e represents the volume of the magnetic component.

The losses of the three converters are shown in Figure 7. The efficiencies of the DAB + BOOST converter, the QAB + BOOST converter, and the CF-QAB converter are 97.56%, 98.09%, and 98.12%, respectively. It can be seen that the converter loss proposed in this paper is lower than that of the DAB + BOOST converter and the QAB + BOOST converter and the efficiency has been improved. Compared with the DAB + BOOST converter, the converter proposed in this paper mainly benefits from the reduction in the number of switching devices and transformers, resulting in significant improvements in losses and efficiency. Compared with the QAB + BOOST converter, the converter proposed in this paper mainly benefits from the reuse of the bridge arms, reducing the number of switching devices, and, by using PWM and phase-shifting techniques, reducing losses and improving efficiency.

To further illustrate the advantages of the proposed CF-QAB converter, a

Table 3. Comparison of topological features for CF-QAB converter and related converters.

	DAB + Boost Converter	QAB + Boost Converter	CF-QAB Converter (The Proposed Converter)
Cost	High	High	Low
Loss	High loss	Moderate Loss	Low Loss
Switch voltage stress	Low	High	High
Switch current stress	Low	High	High
Structural configuration	Complex	Moderately Complex	Simple
BESS integration capability	Poor	Poor	Excellent
control complexity	Low Complexity	Low Complexity	High Complexity
hardware requirements	Lowest	High	Moderate

is provided below, comparing its topological features with those of related converters in terms of structural configuration, BESS integration capability, control complexity, hardware requirements, and system-level advantages.

3. Modeling and Control System Design

3.1. Small-Signal Model of the CF-QAB Converters

The corresponding average equivalent circuit model of the CF-QAB converter is depicted as Figure 8, where I_QAB is the equivalent average current from the MV side to the LV side. I_Ldc is the sum of Boost inductor average currents I_Ldc1, I_Ldc2. L_dc = 0.5 L_dc1 = 0.5 L_dc2 is the equivalent inductance of parallel Boost inductors L_dc1 and L_dc2. R_dc = 0.5 R_dc1 = 0.5 R_dc2 is the equivalent resistance of parallel inductors L_dc1 and L_dc2. R_LV is the equivalent LV side port load. Considering the forward power flow, the battery port can be equivalent to a resistor R_bat. Based on the developed average equivalent circuit model in Figure 6, the average and the small-signal models can be derived. The small-signal state-space equations in main operation modes are derived in Appendix A Equations (A1)–(A4). Accordingly, the transfer functions G₁₁(s), G₁₂(s), G₂₁(s), and G₂₂(s), which represent the relationship between v_bat-d, v_bat-Φ, v_LV-d, and v_LV-Φ, are summarized in Equations (5)–(7).

Different from the design case in Section 2.2, the specific parameters in the lab/HIL case are shown in

Table 4. The main parameters of the CF-QAB converter.

Parameters	Description	Values
VMV	MV side reference voltage	400 V
VLV	LV side reference voltage	400 V
CLV	LV side capacitor	0.1 mF
Cbat	BESS port capacitor	0.1 mF
L	Equivalent AC inductor	50 μH
Ldc1	Boost inductor	1500 μH
RLdc1	Resistor of Boost inductors	0.5 Ω
k	Transformer turns ratio	1:1:1:1
f	Switching frequency	10 kHz

. The Bode plots of the transfer functions G11(s), G12(s), G21(s), and G22(s) can be obtained and compared with circuit simulation results, as shown in Figure 9. It can be seen that the analytical small-signal model is in agreement with the circuit simulation results, which indicates the good accuracy of the established model.

Mode I:

$$\{\begin{array}{l}{G}_{11}=\left\{2V_{\mathrm{LV}}\left(C_{\mathrm{LV}}s+1/R_{\mathrm{LV}}\right)+D\left[\mathrm{sgn}\left(0.5-D\right)\cdot 3\varphi V_{\mathrm{MV}}/\omega L-4I_{\mathrm{Ldc}1}\right]\right\}/\mathrm{den}\\ G_{12}=\left[3D\left(2D^{\mathrm{T}}-\varphi /\pi \right)V_{\mathrm{MV}}/2\omega L\right]/\mathrm{den}\\ G_{21}=\left\{\left[\mathrm{sgn}(0.5-D)\cdot 3\varphi V_{\mathrm{MV}}/\left(2\omega L\right)-2I_{\mathrm{Ldc}1}\right]\left[\left(L_{\mathrm{dc}1}s+R_{\mathrm{Ldc}1}\right)\left(C_{\mathrm{bat}}s+1/R_{\mathrm{bat}}\right)+2\right]-2D{V}_{\mathrm{LV}}\left(C_{\mathrm{bat}}s+1/R_{\mathrm{bat}}\right)\right\}/\mathrm{den}\\ G_{22}=\left\{\left(3V_{\mathrm{MV}}/4\omega L\right)\left(2D^{\mathrm{T}}-\varphi /\mathsf{\pi }\right)\left[\left(C_{\mathrm{bat}}s+1/R_{\mathrm{bat}}\right)\left(L_{\mathrm{dc}1}s+R_{\mathrm{Ldc}1}\right)+2\right]\right\}/\mathrm{den}\end{array}$$

(5)

Mode II:

$$\{\begin{array}{l}{G}_{11}=\left\{2V_{\mathrm{LV}}\left(C_{\mathrm{LV}}s+1/R_{\mathrm{LV}}\right)+D\left[\mathrm{sgn}\left(0.5-D\right)\cdot 3V_{\mathrm{MV}}\mathsf{\pi }\left(1-{2\mathrm{D}}^{\mathrm{T}}\right)/\omega L-4I_{\mathrm{Ldc}1}\right]\right\}/\mathrm{den}\\ G_{12}=\left[3D\left(1-2\varphi /\pi \right)V_{\mathrm{MV}}/2\omega L\right]/\mathrm{den}\\ G_{21}=\left\{\left[\mathrm{sgn}(0.5-D)\cdot 3\mathsf{\pi }\left(1-2D^{\mathrm{T}}\right)V_{\mathrm{MV}}/\left(2\omega L\right)-2I_{\mathrm{Ldc}1}\right]\left[\left(L_{\mathrm{dc}1}s+R_{\mathrm{Ldc}1}\right)\left(C_{\mathrm{bat}}s+1/R_{\mathrm{bat}}\right)+2\right]-2D{V}_{\mathrm{LV}}\left(C_{\mathrm{bat}}s+1/R_{\mathrm{bat}}\right)\right\}/\mathrm{den}\\ G_{22}=\left\{\left(3V_{\mathrm{MV}}/4\omega L\right)\left(1-2\varphi /\mathsf{\pi }\right)\left[\left(C_{\mathrm{bat}}s+1/R_{\mathrm{bat}}\right)\left(L_{\mathrm{dc}1}s+R_{\mathrm{Ldc}1}\right)+2\right]\right\}/\mathrm{den}\end{array}$$

(6)

$$\begin{array}{l}\mathrm{den}=\left(C_{\mathrm{bat}}{C}_{\mathrm{LV}}s+C_{\mathrm{LV}}/R_{\mathrm{bat}}+C_{\mathrm{bat}}/R_{\mathrm{LV}}\right)\left(L_{\mathrm{dc}1}{s}^2+R_{\mathrm{Ldc}1}s+2D^2/C_{\mathrm{LV}}+2/C_{\mathrm{bat}}\right)+\left(L_{\mathrm{dc}1}s+R_{\mathrm{Ldc}1}\right)/\left(R_{\mathrm{bat}}{R}_{\mathrm{LV}}\right)\\ -2C_{\mathrm{LV}}/\left(R_{\mathrm{bat}}{C}_{\mathrm{bat}}\right)-2D^2{C}_{\mathrm{bat}}/\left(C_{\mathrm{LV}}{R}_{\mathrm{LV}}\right)\end{array}$$

(7)

3.2. Control System Design of the CF-QAB Converter

According to the small-signal model of the CF-QAB converter, it can be seen that the converter is a multiple-input and multiple-output (MIMO) system. The corresponding control block diagram is shown in Figure 10, where the PI controllers G_c1 and G_c2 are used for voltage control of the LV side voltage v_LV and BESS port voltage v_bat of the CF-QAB converter, respectively. G_d(s) represents the delay caused by the sensors, digital controller, and driving circuits, with a delay time of approximately (1–1.5) T_s. In the process of model analysis, the delay function $G_{\mathrm{d}}(s)={\mathrm{e}}^{-1.5T_{s}s}$ can be approximated as a third order transfer function.

For the convenience of designing the proposed system controllers and analyzing its stability, the control system based on individual channel design method is proposed in this paper. Based on the small-signal model and the control structure in Figure 10, the MIMO system can be equivalent to two single-input single-output (SISO) systems, as shown in Figure 11. It is worth noting that in the derivation of a single channel, no variable information is lost. Therefore, the stability of the MIMO system in Figure 10 depends on the stability of the two individual SISO systems in Figure 11.

The open-loop gains of single channels are represented as follows:

$$T_1(s)=G_{\mathrm{c}1}(s)G_{\mathrm{d}}{\left(\mathrm{s}\right)\mathrm{G}}_{11}\left(\mathrm{s}\right)\left(1-\gamma \left(\mathrm{s}\right)H_2(s)\right)$$

(8)

$$T_2(s)=G_{\mathrm{c}2}(s)G_{\mathrm{d}}{\left(\mathrm{s}\right)\mathrm{G}}_{22}\left(\mathrm{s}\right)\left(1-\gamma \left(\mathrm{s}\right)H_1(s)\right)$$

(9)

where γ(s), H₁(s), and H₂(s) are given in (7)–(9). γ(s) is the Multivariable Information Structure Function (MSF) [20] and its magnitude reflects the coupling degree of the system. The larger the magnitude, the stronger the coupling. Figure 12 shows the Bode plot of γ(s), when the frequency is less than 70 Hz and the amplitude of γ(s) is smaller than 10 dB, indicating that the degree of coupling in the system is small.

$$\gamma (s)={\displaystyle \frac{G_{12}(s)G_{21}(s)}{G_{11}(s)G_{22}(s)}}$$

(10)

$$H_1(s)={\displaystyle \frac{G_{\mathrm{c}1}(s)G_{\mathrm{d}}(s)G_{11}(s)}{1+G_{\mathrm{c}1}(s)G_{\mathrm{d}}(s)G_{11}(s)}}$$

(11)

$$H_2(s)={\displaystyle \frac{G_{\mathrm{c}2}(s)G_{\mathrm{d}}(s)G_{22}(s)}{1+G_{\mathrm{c}2}(s)G_{\mathrm{d}}(s)G_{22}(s)}}$$

(12)

Based on the equivalent SISO control system and the control system design by using the classical Bode diagram, the Bode plots of T₁(s) and T₂(s) with blue and red can be obtained as shown in Figure 13. It can be seen that the bandwidths of T₁(s) and T₂(s) are 3.37 Hz and 30 Hz, respectively, where both of them are less than 70 Hz. The phase margins are 99.5° and 109°, and the corresponding crossover frequencies ω_c are 726 Hz and 3770 Hz, respectively, with corresponding gain margins of 21.5 dB and 37.7 dB. Additionally, the closed-loop pole-zero diagrams of T₁(s) and T₂(s) have been created to further complement the analysis, as shown in Figure 14. Based on the stability criteri-on, it can be concluded that the system is stable.

4. Experimental Results

To validate the proposed topology and control system, the CF-QAB converter was modeled in Typhoon HIL 402 with the parameters of the power stage provided in Table 2. The rated battery voltage is 200 V, while the three MV-side port voltages are 400 V and the rated LV-side port voltage is 400 V. The turns ratio of the high-frequency transformer is equal to k = 1. Meanwhile, the ADC samplings, the PWM generation, and digital controls are implemented in the DSP 2808 controller. The ADC sampling rate is consistent with the switching frequency, both being 10 kHz. The total measured control-loop delay is one sampling period. The overall experimental setup in the laboratory is shown in Figure 15.

The experimental results of the CF-QAB converter are presented in Figure 16, Figure 17 and Figure 18. Figure 16a,b show the BESS and LV-side port voltages, and the BESS voltage and current, respectively, before and after t = t_step. The low-voltage (LV) side port voltage (v_lv) exhibits remarkable stability. Operating at the rated reference voltage of 400 V, v_lv maintains a constant value without significant fluctuations even when the battery energy storage system (BESS) port undergoes dynamic transitions—specifically, when the BESS port voltage steps from 140 V to 160 V and the BESS current steps from 4 A to 6 A. The power absorbed by the LV-side port (P_LV) remains constant at 4000 W due to the proposed “individual channel design method,” which decouples the CF-QAB’s MIMO system into two independent SISO subsystems. Combined with PI controllers and precise small-signal parameter design (bandwidth 3.37 Hz, phase margin 99.5°), this strategy ensures stable LV-side voltage regulation. As shown in Figure 16c, Pbat increases from 560 W to 960 W, while P_LV stays at 4000 W. Consequently, the total transfer power P_tot = P_LV + P_bat rises from 4560 W to 4960 W after t = t_step.

Figure 17 shows the AC output voltages and the inductor currents of the MV and LV active bridges, and the BESS port currents before the step time t_step. In Figure 17a, the AC output voltages of the active bridges are three-level and there is a phase-shift angle φ₁ between the MV and LV sides for the power transmission, which is consistent with the analysis of Section 2. In Figure 17b, due to V_MV = V_LV, the inductor currents are also three-level according to the theoretical analysis. Moreover, the AC inductor current of active bridge AB_LV is the sum of the MV side currents i_MVA, i_MVB, and i_MVB.

Figure 17c shows the current flowing into the BESS i_bat and the current flowing through BESS port inductors i_b1 and i_b2. It can be seen that the average value of i_bat is 4 A while those of i_b1 and i_b2 are 2 A. Since the leading leg and lagging leg are phase-shifted with π in the LV active bridge, the ripple of i_bat is smaller than that of i_b1 and i_b2.

Figure 18 shows the AC output voltages and the inductor currents of the MV and LV active bridges, and the BESS port currents after the step time t_step. Similarly, the AC output voltages of the active bridges are three-level and there is a phase-shift angle φ₂ between the MV and LV sides as shown in Figure 18a. Due to the increase in duty cycle D for the regulation of BESS voltage, the inductor currents i_MVA, i_MVB, i_MVC, and i_LV are nearly two-level, which are the obvious differences with Figure 18b. Figure 17c shows the current flowing into the BESS i_bat and the current flowing through BESS port inductors i_b1 and i_b2. It can be seen that the average value of i_bat is 6 A, while those of i_b1 and i_b2 are 3 A. Therefore, the duty cycle is close to 0.5 and the ripple of i_bat is smaller than that in Figure 17c.

5. Conclusions

This paper proposed a current-fed quadruple active-bridge DC–DC converter and the corresponding control system design method for smart transformers with integration of BESSs. The principles of operation, modeling, and control system design based on an individual channel design method were analyzed and the experimental results were shown to validate the analysis. Due to requiring no additional hardware circuits for the BESSs and it being easy to achieve power distribution control, the proposed architecture can not only reduce the system volume and cost but can also improve the system management capability. However, how to achieve an optimized power distribution among the grid, the BESSs, and the load, although it is challenging, has not yet been discussed in detail, so it should be an emphasis of future research.