Comprehensive Performance Assessment of Conventional and Sequential Predictive Control for Grid-Tied NPC Inverters: A Hardware-in-the-Loop Study

Abstract

Model Predictive Control (MPC) has become very attractive for the efficient control of power converters. This paper compares Classical MPC (C-MPC) and Sequential MPC (S-MPC) for a three-level NPC converter. Although C-MPC is simple to implement, it faces challenges such as switching frequency variations and complex weighting factor tuning. S-MPC addresses these issues by prioritizing control objectives sequentially, eliminating weighting factors, and simplifying controller design. Simulation results show that S-MPC improves the tracking of output currents, reduces harmonic distortion, and enhances the balancing of dc–link voltages under steady-state and transient conditions. These findings establish S-MPC as a robust alternative to C-MPC, improving power quality and system performance in multilevel converter applications.

1. Introduction

Over the years, the rapid development of the global economy has led to a continuous increase in energy consumption, bringing climate and environmental issues to the forefront. Carbon dioxide emissions from human activities significantly exacerbate the greenhouse effect, drawing increasing attention from society, the scientific community, and industrial and agricultural sectors. In response, these sectors have increasingly focused on developing and adopting new technologies based on renewable energy sources (RES), particularly solar and wind energy [1,2]. Consequently, modern power grids have become increasingly dependent on power electronics to efficiently integrate these energy sources and promote energy sustainability by reducing carbon dioxide emissions in electricity generation [3].

As the integration of distributed energy resources (DER) into power grids incessantly grows, it becomes crucial to understand the potential benefits of this paradigm for both electricity suppliers and end-users. The beneficial trend behind DERs is primarily driven by the versatile application of power electronic converters, which act as interfacing equipment capable of flexibly regulating power generation and consumption. Grid-connected inverters, in particular, enable DERs to seamlessly interact with the electric grid, facilitating active power dispatch to feed loads and achieve financial objectives while ensuring compliance with standards and grid codes [3,4,5,6,7].

Multilevel power converters can generate high-quality AC voltages and currents, making them suitable for high-voltage and high-power applications [8]. However, their increased number of power switches introduces control complexity [9]. Among these topologies, the neutral-point-clamped (NPC) converter, often referred to as the three-level diode-clamped converter, is extensively utilized in medium-voltage, high-power industrial applications as well as in photovoltaic (PV) generation systems [10,11]. These converters employ clamping diodes and cascaded dc–link capacitors to produce multiple voltage levels, effectively reducing common-mode voltages, total harmonic distortion (THD), and electromagnetic interference (EMI) [8,12]. Despite their advantages, the control of NPC converters remains challenging, necessitating advanced modulation and control strategies to ensure reliable operation in demanding environments.

In the past decades, Model Based Predictive Control (MPC) techniques began to be spread in academia and industry environments due to the advancements in semiconductors and computer systems. Among MPC methods, the Finite Control Set (FCS-MPC) approach stands out due to its simplicity of implementation, considering modern microprocessors [13]. The classic FCS-MPC control method (C-MPC) solves the inverter model for all the possible switching states. In the case of an NPC three-level inverter, twenty-seven states are evaluated in each sample time [13,14]. Several control objectives can be included in the MPC cost function [15]. For example, the cost function of MPC control can comprise different objectives, such as voltage, current, switching frequency, and so on [16,17].

Conventional MPC uses a single cost function with weighting factors to handle additional control objectives, i.e., the controlled variables. However, the selection of weighting factors regarding a specific control objective significantly affects the remaining controlled variables [18], since in many cases, the target objectives could require conflicting actions [19]. In other words, if a high weighting factor is applied to achieve a given objective, the other control variables may deviate from the target reference. The above discussion enforces that weighting factor values directly influence the system’s performance. Nevertheless, it is not simple to define suitable weighting factor values to achieve a desired system behavior. Usually, the procedure consists of a heuristic approach based on defining figures of merit depending on the application, followed by a large number of exhaustive simulations or experiments [17], which often relies on the experience of engineers and is a time-consuming process [16]. In [20,21], an approach and a set of guidelines are presented to reduce the uncertainty and the time consumed in the process of defining the weighting factors, relying on the classification of different types of cost functions and weighting factors. Despite this attempt to systematize the weighting factor designs, a high number of simulations is still required.

Sequential Model Predictive Control (S-MPC) was first proposed in [22] to avoid the design complexity associated with the weighting factors design required by C-MPC. This strategy uses a sequential structure with a single cost function for each control objective evaluated. In the case of a three-phase NPC, the primary cost function is evaluated considering all the possible switching vectors (twenty-seven). Then, a given number (N) of switching vectors that yield the best value for the main control cost function are ranked and used to evaluate the secondary cost function. In the end, a switching vector that complies with the restriction of both cost functions is selected and applied to the inverter. As highlighted in [19], the primary cost function has a higher priority over the secondary one. Despite its design simplicity, the aforementioned method requires a tuning process to define the optimum number of switching vectors selected to be evaluated in the secondary cost functions. However, this process is expected to be simpler than that required to tune the weighting factors of the C-MPC method.

On the other hand, due to the limited granularity resulting from the restricted number of evaluated voltage vectors, the S-MPC strategy does not achieve the same performance levels observed with the C-MPC approach. Moreover, S-MPC incurs a higher computational burden, as it requires sorting the voltage vectors based on the evaluation of the primary cost function.

Although previous studies have extensively explored C-MPC for multilevel converters, limited work has focused on systematically analyzing the performance trade-offs between C-MPC and S-MPC, particularly in the context of three-phase neutral-point-clamped (NPC) converters used for renewable energy integration into the grid. The most comprehensive comparison so far [23] investigates the performance of C-MPC versus S-MPC, although the evaluation focuses solely on disturbances on the ac side of the system, without considering variations in DC power, disturbances within the dc–link control system, or voltage fluctuations of individual capacitors in the dc–link. The behavior of the NPC converter is analyzed under variations in dc power in [24], yet no consideration is given to ac grid disturbances. The study only presents simulation results. Ref. [25] addresses an NPC converter supplying a nonlinear load. The system is implemented on a Hardware-In-the-Loop (HIL) platform, but only results for ac voltage step variations are reported, with no discussion on other types of disturbances or transient behavior. Ref. [26] presents simulation results, but the analysis is limited to step variations in ac output current and the dc–link capacitor voltage balance. No ac or dc side disturbances are introduced to examine the steady-state or transient response.

Therefore, this paper provides a comprehensive comparison of C-MPC and S-MPC strategies applied to a three-level NPC converter connected to the grid. By evaluating key performance metrics considering dc- and ac-side performance under steady-state and transient conditions, this study provides critical insight into the practical advantages and limitations of each approach. Furthermore, to ensure the reproducibility of the tests and provide a fair comparison between the two MPC techniques, the performance assessment is carried out using a real-time Hardware In the Loop (HIL) device.

The remainder of this paper is organized as follows. Section 2 outlines the system modelling and control of the three-phase grid-tied NPC using conventional and sequential FCS-MPC strategies. The impact of weighting factor selection and the quantity of voltage vectors used on both MPC strategies are discussed in Section 3. Section 4 details the deployment of the real-time simulations using the Opal-RT HIL system. The real-time HIL results are provided in Section 5, and a detailed comparison of the two approaches is presented. Finally, Section 6 concludes the paper with key findings.

2. System Modelling

The three-phase NPC converter topology is shown in Figure 1. Each phase consists of four switching devices and two clamp diodes. The switching states and the corresponding voltage magnitudes are organized in

Table 1. Three-level NPC switch state.

Switching State $\mathbf{\left(}{\mathit{S}}_{\mathit{x}}\mathbf{\right)}$	Switch Signals $\mathbf{(}{\mathit{S}}_{\mathbf{1}\mathit{x}}\mathbf{,}{\mathit{S}}_{\mathbf{2}\mathit{x}}\mathbf{)}$	Output Voltage $\mathbf{\left(}{\mathit{v}}_{\mathit{xN}}\mathbf{\right)}$
−1	(0, 0)	$-{\displaystyle \frac{v_{dc}}{2}}$
0	(0, 1)	0
1	(1, 1)	${\displaystyle \frac{v_{dc}}{2}}$

, where $x\in \{a,b,c\}$ represents each one of the three phases of the converter. The switching states of the power transistors are indicated by $S_x\in \{-1,0,1\}$, respectively. Three voltage levels are generated between each of the inverter legs and the point n depending on the switching state, i.e., $v_{xn}\in \{{\displaystyle \frac{v_{dc}}{2}},0,-{\displaystyle \frac{v_{dc}}{2}}\}$. If converted, to $\alpha \beta$ frame, the output voltage can be represented as 27 voltage vectors generated by the 27 possible switching states. A full list of the switching states and resulting phase voltages is presented in

Table 2. Three-level NPC switch state.

State	${\mathit{S}}_{1\mathit{a}}$	${\mathit{S}}_{2\mathit{a}}$	${\mathit{S}}_{1\mathit{b}}$	${\mathit{S}}_{2\mathit{b}}$	${\mathit{S}}_{1\mathit{c}}$	${\mathit{S}}_{2\mathit{c}}$	${\mathit{v}}_{\mathit{an}}$	${\mathit{v}}_{\mathit{bn}}$	${\mathit{v}}_{\mathit{cn}}$	${\mathit{v}}_{\mathit{\alpha }}$	${\mathit{v}}_{\mathit{\beta }}$
1	1	1	1	1	1	1	$+{\displaystyle \frac{v_{dc}}{2}}$	$+{\displaystyle \frac{v_{dc}}{2}}$	$+{\displaystyle \frac{v_{dc}}{2}}$	0	0
2	1	1	1	1	0	1	$+{\displaystyle \frac{v_{dc}}{2}}$	$+{\displaystyle \frac{v_{dc}}{2}}$	0	$+{\displaystyle \frac{v_{dc}}{3}}$	$+{\displaystyle \frac{v_{dc}}{\sqrt{3}}}$
3	1	1	1	1	0	0	$+{\displaystyle \frac{v_{dc}}{2}}$	$+{\displaystyle \frac{v_{dc}}{2}}$	$-{\displaystyle \frac{v_{dc}}{2}}$	$+{\displaystyle \frac{2v_{dc}}{3}}$	0
4	1	1	0	1	1	1	$+{\displaystyle \frac{v_{dc}}{2}}$	0	$+{\displaystyle \frac{v_{dc}}{2}}$	0	$+{\displaystyle \frac{v_{dc}}{\sqrt{3}}}$
5	1	1	0	1	0	1	$+{\displaystyle \frac{v_{dc}}{2}}$	0	0	$+{\displaystyle \frac{v_{dc}}{3}}$	$+{\displaystyle \frac{v_{dc}}{3\sqrt{3}}}$
6	1	1	0	1	0	0	$+{\displaystyle \frac{v_{dc}}{2}}$	0	$-{\displaystyle \frac{v_{dc}}{2}}$	$+{\displaystyle \frac{2v_{dc}}{3}}$	$-{\displaystyle \frac{v_{dc}}{\sqrt{3}}}$
7	1	1	0	0	1	1	$+{\displaystyle \frac{v_{dc}}{2}}$	$-{\displaystyle \frac{v_{dc}}{2}}$	$+{\displaystyle \frac{v_{dc}}{2}}$	0	0
8	1	1	0	0	0	1	$+{\displaystyle \frac{v_{dc}}{2}}$	$-{\displaystyle \frac{v_{dc}}{2}}$	0	$+{\displaystyle \frac{v_{dc}}{3}}$	$-{\displaystyle \frac{v_{dc}}{\sqrt{3}}}$
9	1	1	0	0	0	0	$+{\displaystyle \frac{v_{dc}}{2}}$	$-{\displaystyle \frac{v_{dc}}{2}}$	$-{\displaystyle \frac{v_{dc}}{2}}$	$+{\displaystyle \frac{2v_{dc}}{3}}$	$-{\displaystyle \frac{2v_{dc}}{\sqrt{3}}}$
10	0	1	1	1	1	1	0	$+{\displaystyle \frac{v_{dc}}{2}}$	$+{\displaystyle \frac{v_{dc}}{2}}$	$-{\displaystyle \frac{v_{dc}}{3}}$	$+{\displaystyle \frac{v_{dc}}{\sqrt{3}}}$
11	0	1	1	1	0	1	0	$+{\displaystyle \frac{v_{dc}}{2}}$	0	0	$+{\displaystyle \frac{v_{dc}}{\sqrt{3}}}$
12	0	1	1	1	0	0	0	$+{\displaystyle \frac{v_{dc}}{2}}$	$-{\displaystyle \frac{v_{dc}}{2}}$	$+{\displaystyle \frac{v_{dc}}{3}}$	0
13	0	1	0	1	1	1	0	0	$+{\displaystyle \frac{v_{dc}}{2}}$	$-{\displaystyle \frac{v_{dc}}{3}}$	$+{\displaystyle \frac{v_{dc}}{3\sqrt{3}}}$
14	0	1	0	1	0	1	0	0	0	0	0
15	0	1	0	1	0	0	0	0	$-{\displaystyle \frac{v_{dc}}{2}}$	$+{\displaystyle \frac{v_{dc}}{3}}$	$-{\displaystyle \frac{v_{dc}}{3\sqrt{3}}}$
16	0	1	0	0	1	1	0	$-{\displaystyle \frac{v_{dc}}{2}}$	$+{\displaystyle \frac{v_{dc}}{2}}$	$-{\displaystyle \frac{v_{dc}}{3}}$	$-{\displaystyle \frac{v_{dc}}{\sqrt{3}}}$
17	0	1	0	0	0	1	0	$-{\displaystyle \frac{v_{dc}}{2}}$	0	0	$-{\displaystyle \frac{v_{dc}}{\sqrt{3}}}$
18	0	1	0	0	0	0	0	$-{\displaystyle \frac{v_{dc}}{2}}$	$-{\displaystyle \frac{v_{dc}}{2}}$	$+{\displaystyle \frac{v_{dc}}{3}}$	$-{\displaystyle \frac{2v_{dc}}{\sqrt{3}}}$
19	0	0	1	1	1	1	$-{\displaystyle \frac{v_{dc}}{2}}$	$+{\displaystyle \frac{v_{dc}}{2}}$	$+{\displaystyle \frac{v_{dc}}{2}}$	$-{\displaystyle \frac{2v_{dc}}{3}}$	0
20	0	0	1	1	0	1	$-{\displaystyle \frac{v_{dc}}{2}}$	$+{\displaystyle \frac{v_{dc}}{2}}$	0	$-{\displaystyle \frac{v_{dc}}{3}}$	$+{\displaystyle \frac{v_{dc}}{\sqrt{3}}}$
21	0	0	1	1	0	0	$-{\displaystyle \frac{v_{dc}}{2}}$	$+{\displaystyle \frac{v_{dc}}{2}}$	$-{\displaystyle \frac{v_{dc}}{2}}$	0	0
22	0	0	0	1	1	1	$-{\displaystyle \frac{v_{dc}}{2}}$	0	$+{\displaystyle \frac{v_{dc}}{2}}$	$-{\displaystyle \frac{2v_{dc}}{3}}$	$+{\displaystyle \frac{v_{dc}}{\sqrt{3}}}$
23	0	0	0	1	0	1	$-{\displaystyle \frac{v_{dc}}{2}}$	0	0	$-{\displaystyle \frac{v_{dc}}{3}}$	0
24	0	0	0	1	0	0	$-{\displaystyle \frac{v_{dc}}{2}}$	0	$-{\displaystyle \frac{v_{dc}}{2}}$	0	$-{\displaystyle \frac{v_{dc}}{\sqrt{3}}}$
25	0	0	0	0	1	1	$-{\displaystyle \frac{v_{dc}}{2}}$	$-{\displaystyle \frac{v_{dc}}{2}}$	$+{\displaystyle \frac{v_{dc}}{2}}$	$-{\displaystyle \frac{2v_{dc}}{3}}$	$-{\displaystyle \frac{v_{dc}}{\sqrt{3}}}$
26	0	0	0	0	0	1	$-{\displaystyle \frac{v_{dc}}{2}}$	$-{\displaystyle \frac{v_{dc}}{2}}$	0	$-{\displaystyle \frac{v_{dc}}{3}}$	$-{\displaystyle \frac{v_{dc}}{\sqrt{3}}}$
27	0	0	0	0	0	0	$-{\displaystyle \frac{v_{dc}}{2}}$	$-{\displaystyle \frac{v_{dc}}{2}}$	$-{\displaystyle \frac{v_{dc}}{2}}$	0	0

.

Based on their length, vectors can be categorized into four groups: zero, small, medium, and large vectors. In terms of capacitor voltage balancing, only the small- and medium-sized vectors have an impact [27]. Therefore, the application of such vectors must be determined by some strategy focusing on maintaining the balance between the voltages of both capacitors.

At this point, it is important to note that voltage imbalance in the capacitors of NPC inverters can be caused by several factors. Asymmetric load currents can result in an unequal current distribution between the three inverter points, leading to a voltage imbalance [28]. Imperfections in switching devices, such as transistors or IGBTs, can affect the load distribution and, consequently, disturb the voltage balance [29]. Errors in system modellng or incorrect inverter parameters can also affect the precision of voltage control and the balance [30]. Improper pulse width modulation (PWM) may lead to imbalances in energy distribution, causing voltage discrepancies between capacitors [31]. Furthermore, variations in the load conditions or operating conditions of the inverter can facilitate voltage imbalance [32]. Failures in inverter components, such as diodes or transistors, can contribute to voltage imbalances due to the improper or defective behavior of one of the branches [33]. Lastly, overloading or an imbalance in the energy supplied between voltage levels increases the risk of a capacitor voltage imbalance [34]. These factors require careful control and monitoring to ensure the safe and efficient operation of the NPC inverter.

In a three-level NPC converter, the voltage ($v_{xn}$) between each phase output and the n-point can be represented by the relationship between the switching state and the voltage of the dc–link split capacitors:

$$v_{xN}=v_{c1}{S}_{1x}+v_{c2}{S}_{2x},x\in \{a,b,c\}$$

(1)

The dynamic relationship between the current ($i_{Cn}$) throughout the dc–link capacitors and the respective dc–link capacitor voltage ($v_{Cn}$) is expressed according to

$${\displaystyle \frac{d{v}_{cn}}{dt}}={\displaystyle \frac{i_{Cn}}{C_n}},n\in \{1,2\}$$

(2)

Moreover, the current ($i_{Cn}$) flowing through the dc–link capacitors can be derived using Kirchhoff’s current law (KCL) for the intersection of the dc–link capacitor and the upper bridge arm. Therefore, the dc currents can be expressed as the relationship among the grid currents, switching states, and the overall dc–link current $i_{dc}$, as depicted below:

$$i_{C1}=i_{dc}-S_{1a}{i}_a-S_{1b}{i}_b-S_{1c}{i}_c$$

(3)

$$i_{C2}=i_{dc}+S_{2a}^{\prime }{i}_a+S_{2b}^{\prime }{i}_b+S_{2c}^{\prime }{i}_c$$

(4)

where $S_{2ax}^{\prime }$ represent the complementary gating signals $S_{2ax}$.

Equations (3) and (4) can be used to calculate the current through the dc–link capacitors, avoiding the need for external current measurements.

The ac output of the NPC inverter can be modeled by applying Kirchhoff’s Voltage Law (KVL), considering the voltage output of the inverter ($v_{ix}$), the grid voltage ($v_{gx}$), and the grid current ($i_x$). where x stands for each of the three phases, that is, $x\in \{a,b,c\}$, resulting in

$${\displaystyle \frac{d{i}_{gx}}{dt}}={\displaystyle \frac{(v_{ix}-v_{gx})}{L}}-{\displaystyle \frac{R}{L}}{i}_{gx}$$

(5)

Parameters L and R represent the inductance and parasitic resistance of the inverter’s output filter summed to the intrinsic grid inductance and resistance.

For simplicity and ease of implementation, Equation (5) is transformed to the stationary reference frame using the Clarke transformation shown in (6), resulting in (7), where both the coordinates $\alpha$ and $\beta$ are presented in separate equations.

$$\left[\begin{array}{c}{f}_{\alpha }\\ f_{\beta }\end{array}\right]={\displaystyle \frac{2}{3}}\left[\begin{array}{ccc}1& -{\displaystyle \frac{1}{2}}& -{\displaystyle \frac{1}{2}}\\ 0& {\displaystyle \frac{\sqrt{3}}{2}}& -{\displaystyle \frac{\sqrt{3}}{2}}\end{array}\right]\left[\begin{array}{c}{f}_a\\ f_b\\ f_c\end{array}\right]$$

(6)

$$\begin{array}{cc}\hfill {\displaystyle \frac{d{i}_{g\alpha }}{dt}}& ={\displaystyle \frac{1}{L}}(v_{i\alpha }-v_{g\alpha })-{\displaystyle \frac{R}{L}}{i}_{g\alpha }\hfill \\ \hfill {\displaystyle \frac{d{i}_{g\beta }}{dt}}& ={\displaystyle \frac{1}{L}}(v_{i\beta }-v_{g\beta })-{\displaystyle \frac{R}{L}}{i}_{g\beta }\hfill \end{array}$$

(7)

In order to achieve the application of conventional and sequential MPC controllers and due to the inherently discrete nature of such control methods, Equation (1), describing the current and voltage dynamic in the dc–link capacitors, and Equation (2), governing the three-phase grid-tied NPC inverter output current, are converted to discrete time using the forward Euler approximation. Assuming that the control variable remains constant during the sampling time $T_s$ [35], the discrete-time model, which can be used for voltage and current predictions required by MPC methods, is given by:

$$i_{g\alpha }(k+1)=(1-{\displaystyle \frac{R{T}_s}{L}})i_{g\alpha }(k)+{\displaystyle \frac{T_s}{L}}(v_{i\alpha }(k)-v_{g\alpha }(k)),$$

(8)

$$i_{g\alpha }(k+1)=(1-{\displaystyle \frac{R{T}_s}{L}})i_{g\alpha }(k)+{\displaystyle \frac{T_s}{L}}(v_{i\alpha }(k)-v_{g\alpha }(k)),$$

(9)

$$v_{c1}(k+1)=v_{c1}(k)+{\displaystyle \frac{T_s}{C_1}}{i}_{c1}(k+1),$$

(10)

and

$$v_{c2}(k+1)=v_{c2}(k)+{\displaystyle \frac{T_s}{C_2}}{i}_{c2}(k+1).$$

(11)

2.1. Conventional Model Predictive Control (C-MPC)

In the three-level NPC converter, the switching states $(S_x)$ that compose each of the three phases of the power converter can assume three distinctive states: −1, 0, and 1, as presented in Table 1, producing 27 voltage vectors, which are detailed in Table 2, considering the frame $\alpha \beta$. The vector space can be divided into six sectors, subdivided into four groups based on the difference in vector lengths: zero, small, medium, and large vectors. In terms of maintaining the voltage balance of the capacitor, only the medium and small vectors have an effect, while the large and zero vectors are not directly related to this objective [27,35].

Output current and grid voltage measurements are used to predict the output current and dc–link voltage one step ahead and calculate the value of the cost function for each of the 27 switching states. The switching state that yields the minimum-cost function value is then applied to the NPC converter. In this work, the control objectives consist of tracking the inverter’s output current reference and maintaining the voltages balanced in the dc–link capacitors. Consequently, the cost function in (12) is defined to incorporate the quadratic current error (13) and the voltage difference between the dc–link capacitors (14) [36].

$$g=g_i+\lambda g_v$$

(12)

$$g_i={[i_{\alpha }^{*}-i_{\alpha }(k+1)]}^2+{[i_{\beta }^{*}-i_{\beta }(k+1)]}^2$$

(13)

$$g_v={[v_{c1}(k+1)-v_{c2}(k+1)]}^2$$

(14)

where $\lambda$ is a weighting factor that can be used to enhance or attenuate the effect of the dc–link capacitor voltage balancing control and weighting the relationship between the control objectives [35]; $i_x^{*}$ denotes the grid current reference; $i_x(k+1)$ denotes the predicted grid currents, and $v_{cx}(k+1)$ denotes the predicted voltage across the dc–link capacitors.

The flowchart of the C-MPC controller is shown in Figure 2. The input of the C-MPC controller is the three-phase grid current frame ($i_{gabc}$), the grid voltage ($v_{gabc}$), and the dc–link voltages ($v_{c1}$) and ($v_{c2}$). Then, all the switching states of Table 2 are swept, and for each of the switching states, the currents of the dc–link capacitors ($i_{c1}$) and ($i_{c2}$) are calculated according to (3) and (4) to predict the voltages of the dc–link capacitors one sample ahead using (10) and (11). The prediction of the grid current is performed using (8) and (9) for each of the voltage vectors $v_{g\alpha }$ and $v_{g\beta }$ of Table 2, which are related to the switching states. With the predicted values of the grid current and the voltages of the dc–link capacitors, the cost function (12) is calculated for each of the 27 switching states. Note that the index j is used to interactively evaluate the cost function (g) for all available switching vectors. Finally, the switching state associated with the minimal cost function value is selected and applied to the NPC converter.

2.2. Sequential Model Predictive Control (S-MPC)

The discrete equations that model the NPC in the C-MPC are the same as used to implement the S-MPC. However, the S-MPC divides the control objectives into two separate cost functions in order to avoid designing the weighting factor $\lambda$.

In S-MPC, the primary control objective is achieved by evaluating the cost function $g_i$ given by (13) for the 27 VSI voltage vectors in Table 2, according to the flow chart shown in Figure 3. Hence, the 27 values of $g_i$ are sorted in ascending order, and an array with the indices of the switching states of Table 2 is created. Then, in the second stage of the S-MPC algorithm, the switching states corresponding to the first N positions of the sorted array are used to evaluate the currents of the dc–link capacitor, $i_{c1}$ and $i_{c2}$, according to (3) and (4). Subsequently, the voltages of the dc–link capacitors are predicted in a sampling period using (10) and (11). Taking into account the predicted voltages of the dc–link capacitor, the cost function $g_v$, defined in (14), is evaluated for each of the preselected N switching states. Finally, the switching state corresponding to the minimum-cost function value is selected and applied to the NPC converter.

It is important to highlight that the S-MPC approach evaluates only the grid current equations for all 27 switching states, while capacitor current estimation and dc–link capacitor voltage prediction are performed exclusively for the N preselected states.

2.3. Current Reference Generation (PLL Design)

To ensure unity power factor operation, the injected current must be synchronized with the positive-sequence component of the grid voltage. This synchronization is achieved using a Phase-Locked Loop (PLL) based on the synchronous reference frame (SRF-PLL) shown in Figure 4, which extracts the fundamental phase angle ($\theta$) of the grid voltage. The SRF-PLL output is used to generate a unit-amplitude sinusoidal waveform, which is then scaled by the desired current magnitude to form the complete current reference, as further discussed in Section 4.

The phase detection is performed through the Park transformation, and the resulting error is regulated by a PI controller to drive the phase error to zero. The closed-loop transfer function of the system is derived in (15), enabling the design of the proportional ($k_p$) and integral ($k_i$) gains by comparing it with the standard second-order system model. The equations to set the proportional and integral gains are given by (16) and (17), respectively. In this work, the PLL parameters are selected to yield a damping ratio of $\zeta =0.707$, and the bandwidth is set one decade below the grid fundamental frequency (${\omega }_n$ = 31.42 rad/s) to ensure adequate filtering and dynamic response.

$$H_{\mathrm{PLL}}(s)={\displaystyle \frac{k_{p}s+k_i}{s^2+k_{p}s+k_i}}$$

(15)

$$k_p=2\zeta {\omega }_n$$

(16)

$$k_i={\omega }_n^2$$

(17)

The PLL plays a critical role in maintaining a stable and accurate current reference under adverse grid conditions, including voltage unbalance, harmonic distortion, and voltage sags or swells.

3. Determination of MPC Parameters

In this section, the effect of the weighting factor ($\lambda$) on the performance of the C-MPC, as well as the impact of the number of voltage vectors evaluated in the secondary objective (N) of the S-MPC, are investigated. These parameters are defined through extensive simulations to determine their influence on current quality and voltage balancing performance, thereby supporting the optimal tuning of the proposed predictive control strategies.

3.1. Optimal $\lambda$ for C-MPC Strategy

The optimal value of the weighting factor used in the cost function g leads to the lowest total harmonic distortion (THD) of the phase currents and the fastest convergence of the dc–link capacitor voltage balance. The optimum weighting factor was determined through exhaustive simulations using the C-MPC strategy, varying its value from 0 to 0.5 in increments of 0.01. The simulations start with an unbalanced dc–link voltage condition, where $v_{c1}$ = 500 V and $v_{c2}$ = 300 V. The convergence time of the voltage balance and the steady-state current THD were recorded, yielding Figure 5. The weighting factor was selected based on the proximity to the origin in the Cartesian plot shown in Figure 6, which represents the trade-off between THD and convergence time. This approach yields the optimal weighting factor value $\lambda$ = 0.4, resulting in a THD of 3.32% and a voltage balance convergence time of 29 ms. However, as observed in Figure 5, the THD and convergence time remain similar across all evaluated weighting factors since the difference between the highest convergence time and the lowest is only 7 ms, and the deviation in the THD values is only 0.4%. Similarly, Figure 5 shows that the variation in distance to origin is small, indicating that, for practical purposes, any weighting factor greater than zero is sufficient.

3.2. Optimum Number of Candidates Voltage Vectors for S-MPC Strategy

The optimal value for the number of sorted voltage vectors (N) that minimizes the control objectives was determined through exhaustive simulations using the S-MPC strategy, where all 27 voltage vectors were evaluated. The results are presented in Figure 7. The simulations indicate that when more than 10 vectors are used to evaluate the secondary objective of maintaining the dc–link capacitor voltage balance, the current THD increases significantly. Therefore, only the results for $N\le 10$ are shown in Figure 7.

As in the C-MPC case, the proximity to the origin in the Cartesian plot was adopted as the selection criterion (see Figure 8). This approach yields the optimal value N = 2, resulting in a current THD of 3.6% and a voltage balance convergence time of 48 ms.

As the number of evaluated vectors in the secondary objective increases, the convergence time of the dc–link voltage is reduced. However, unlike the C-MPC strategy, the THD of the current increases and may exceed the limits established by grid codes. Therefore, higher values of N are not practically acceptable due to the resulting deterioration in current quality.

4. Hardware in the Loop (HIL) Implementation

The effectiveness of the FCS-MPC approaches applied to the control of the NPC grid-tied converter presented in the previous sections is validated through real-time simulation, considering the system shown in Figure 1. The system parameters are listed in

Table 3. System parameters.

Description and Symbol	Value
Grid voltage ($v_g$/${\omega }_f$)	380 V/50 Hz
Dc–link voltage ($v_{dc}$)	800 V
Filter inductance per phase (L)	5 mH
Resistance of filter inductor (R)	0.8 $\Omega$
Dc–link capacitance ($C_1$ and $C_2$)	3.3 mF
C-MPC controller—Weighting Factor ($\lambda$)	0.4
S-MPC controller—secondary evaluation (N)	2
Sampling Time ($T_s$)	50 μs
SRF-PLL proportional gain ($k_p$)	45
SRF-PLL integral gain ($k_i$)	970
Voltage scaling factor ($g_v$)	100
Current scaling factor ($g_i$)	10

. The weighting factor ($\lambda$) in C-MPC and the number of switching vectors (N) evaluated in the secondary objective cost function of S-MPC were optimized through extensive simulations to achieve the best trade-off between the THD of the grid current and dc–link voltage balance. Real-time simulations were performed using the Opal-RT OP5600 Hardware-in-the-Loop (HIL) platform, following a predefined sequence of programmed events designed to highlight the key characteristics of C-MPC and S-MPC and provide a comprehensive performance assessment between both control approaches.

4.1. Design of NPC Inverter Parameters

The parameters of the proposed system, shown in Table 3, were designed according to the methodology presented in [37]. A dc–link voltage of $V_{dc}=800$ V was adopted, incorporating a 50% design margin to ensure safe operation according to (18). As a result, each semiconductor device is subjected to only half of the dc–link voltage, i.e., 400 V. The dc–link capacitance was selected to limit the voltage ripple to $\mathsf{\Delta }u=1\%$ (0.01 in per unit), based on an average switching frequency of $F_{sw}=4$ kHz and a rated power of 15 kW, calculated according to (19).

$$V_{\mathrm{dc}}=\sqrt{2}{V}_{LL}$$

(18)

$$C_1=C_2={\displaystyle \frac{P}{F_{sw}{V}_{dc}^2\mathsf{\Delta }u}}$$

(19)

The methodology proposed in [38] was applied to calculate the value of the AC output filter inductor using (20), considering an average switching frequency of $F_{\mathrm{sw}}=4$ kHz and a maximum allowable current ripple of 10%.

$$L={\displaystyle \frac{V_{dc}}{12F_{sw}\mathsf{\Delta }{i}_{max}}}$$

(20)

4.2. Real-Time HIL Overview

An overview of the real-time implementation is illustrated in Figure 9. The parameters of the proposed system are shown in Table 3.

The real-time simulation approach employed in this study is based on the Software-in-the-Loop (SIL) concept, enabling rapid prototyping of the controllers. Both FCS-MPC control algorithms were implemented in the C programming language using MATLAB/Simulink s-function blocks.

The power stage, consisting of the NPC power converter, the inductive output filter, the dc source, and the main grid, was modeled within the power block, as shown in Figure 9. To accurately replicate the behavior of a DSP-based control implementation, all measurements transferred from the power block to the control block are delayed by one sampling step. Similarly, a one-step delay is introduced in the control signals transmitted from the control block to the power block. Although this delay mimics the real-world conditions of experimental implementations, it is also a fundamental requirement to ensure proper data exchange between the power and control blocks. This is necessary since each block is executed on a separate microprocessor within the Opal-RT OP5600 HIL, effectively decoupling the power and control sections, similar to conventional experimental setups.

The voltage measurements, namely, the dc–link capacitor voltages $v_{c1}$ and $v_{c2}$ and the three-phase grid voltages $v_{gabc}$, are scaled down by the voltage gain $g_v$, while the three-phase grid currents ($i_{gabc}$) are scaled down by the current gain $g_i$, as illustrated in the control block diagram of Figure 9. To reconstruct the original signals within the control system and ensure unitary feedback, these signals are subsequently scaled up using the same gain factors $g_v$ and $g_i$, respectively. In this way, the behavior of the HIL implementation replicates the signal processing that would occur in a real-world system, thereby ensuring that the control algorithm operates under conditions representative of practical applications.

4.3. Working Flow

In the present work, all models, i.e., control and power converter, are deployed directly into two distinct x64 Intel Xeon processors without using the high-resolution FPGA capability. This approach allows for full exploitation of hardware resources on the target real-time simulator available, minimising the costs with additional hardware and lisences required to execute models with refined time granularity.

Before deployment, both the control and power models were tested offline by simulations using MATLAB/Simulink version 2024a. Subsequently, they were compiled using the RT-Lab software provided by Opal-RT, generating two distinct real-time execution codes, one for the control block and another for the power block. These codes were then uploaded to separate microprocessors within the OP5600 hardware to ensure independent execution. Finally, the output waveforms generated by the HIL platform were acquired using an oscilloscope. The results obtained for each test scenario are presented and analyzed in detail in the following subsections, providing a comprehensive evaluation and comparison of the performance of the proposed control strategy.

5. Results Analysis

The real-time simulation results are structured to highlight the key characteristics of the proposed control approach under steady-state and transient conditions. The analysis focuses on critical performance indicators, considering ac-side parameters such as total harmonic distortion of current (THD_i), settling time ($t_s$), and current ripple ($\mathsf{\Delta }i$). Furthermore, dc-side parameters are evaluated, including dc–link voltage ripple, settling time, and voltage balance between the two input ports ($v_{c1}$ and $v_{c2}$).

5.1. Steady-State Response

Considering steady-state operation, both controllers achieved good grid current tracking, as shown in Figure 10, with THD yielding 4.7% and 5.0% for C-MPC and S-MPC, respectively. C-MPC produces a slightly improved current waveform compared with S-MPC, with a maximum peak-to-peak ripple of approximately 2.0 A, while S-MPC inhibits a ripple of 2.5 A.

The grid current spectrum for phase a is shown in Figure 11, which exhibits a similar harmonic profile in the low-frequency range for both approaches. The small amplitude of the low-frequency harmonics is remarkable for both control approaches as well as the usual spread spectrum expected from MPC controllers.

Figure 12 exhibits the phase-a inverter voltage waveform superimposed on the grid current. The characteristic multilevel voltage waveform can be noticed, along with a slight phase shift between the inverter voltage and the grid current. Given that the grid current is maintained in phase with the grid voltage, which is consistent with the unity power factor control strategy employed, the observed phase shift between the inverter voltage and grid current is due to the coupling inductor filter, setting the power flow from the inverter to the grid side.

5.2. Current Tracking Transient Response

The transient behavior for an increase in current reference step increase of 10 A is shown in Figure 13a,b. Figure 13c,d show a detailed view of the current in phase a during the reference step, highlighting the fast transient response of the MPC controllers. Both MPC control approaches performed similarly without overshoot, with settling times of about 0.25 ms and 0.2 ms for C-MPC and S-MPC, respectively.

5.3. Influence of $\lambda$ and N on Predictive Control Performance

To investigate the ability of both control approaches to balance the voltage of the dc–link capacitors, it was considered that the initial condition of the dc–link capacitor was $v_{c1}$ = 500 V and $v_{c2}$ = 300 V. Figure 14a shows the waveforms for the voltage across $v_{c1}$ and $v_{c2}$ and the grid currents in phases a and b for both C-MPC and, in Figure 14b, for S-MPC. C-MPC took approximately 27 ms to balance the dc–link voltage, while S-MPC took 48 ms. The higher settling time required to balance the dc–link capacitor’s voltage exposed to the S-MPC is due to the selection of only two switching states to evaluate the secondary cost function ($g_2$).

It is important to note that evaluating more switching vectors in the secondary cost function would reduce the settling time, potentially matching that of the C-MPC approach. This behavior is observed, for example, by evaluating seven (N = 7) switching states, as shown in Figure 14d. However, such a configuration leads to a significant increase in current distortion in steady-state conditions, with $TH{D}_i$ rising to approximately 8%. Therefore, to ensure comparable $TH{D}_i$ performance between both control strategies, only two switching vectors are considered in the secondary cost function. This condition is considered when the minimum distance to the origin criteria is used to design the parameters of the MPC strategies, as shown in Section 3.

However, the fast transient response of C-MPC comes at the cost of a higher distorted and rippled current, as seen in the first cycles of Figure 14a, resulting in a current DHT in the first transient cycles of approximately 10.2% and 5.2% for C-MPC and S-MPC, respectively. In addition, both control techniques achieve the secondary objective of balancing the dc link capacitors in a steady state with negligible voltage difference, as shown in the right corner of Figure 14a,b. C-MPC yields a slightly higher low-frequency oscillation at 100 Hz (double the grid frequency) of approximately 0.4 V peak-to-peak. However, the S-MPC approach is free from low-frequency oscillations.

Figure 14a,c show the dc–link voltage convergence time for the C-MPC strategy considering different values of weighting factors, $\lambda =0.4$ and $\lambda =0.02$, respectively. One can note that the difference in the convergence time of dc–link voltages is smaller (27 ms for $\lambda =0.4$ and 32 ms for $\lambda =0.02$) than the difference caused by variations in the number of voltage vectors for the S-MPC. This behavior is supported by Figure 5, where the THD and convergence time remain similar across all evaluated weighting factors since the difference among the convergence time is negligible for all factors evaluated throughout extensive simulations.

5.4. Voltage Harmonics

Grid-tied inverters are widely used in environments with non-linear loads, such as residential and commercial buildings, where harmonic currents interact with the impedance of the grid, causing voltage distortion. In addition, high-power inverters are often exposed to non-sinusoidal voltages in renewable energy parks based on solar or wind sources. Therefore, it is important to ensure that the NPC grid-tied converter with the FCS-MPC controller is capable of handling distorted voltage.

A representative test case is implemented considering 10% of the fifth harmonic component superimposed on the voltage of the grid, as shown in Figure 8. The inverter output current exhibits low sensitivity to the voltage of the grid, as a positive sequence PLL is used to extract the fundamental component of the grid voltage, which is used to generate the current reference.

As expected, since the NPC converter is fed on the dc side with a pure dc voltage source, the practical effect of grid voltage harmonics on the grid current waveform is negligible, as shown in Figure 15 and in the spectra shown in Figure 16. The amplitude of the fundamental current component is 30 A, while the amplitude of the fifth harmonic is less than 0.1, representing 0.4% distortion for this specific harmonic. The overall THDi is 3.7% for the C-MPC and 4.0% for the S-MPC.

5.5. Voltage Sag and Swell

The voltage sags and swells are characterized by sudden variations in grid voltage, resulting in voltages lower than the nominal value for sag events and overvoltage for swell events. The voltage sags and swells could be caused by grid faults, sudden changes in load, or generated power flowing through the main grid. The first scenario analyzed consists of a voltage sag of 40%, i.e., the phase-to-neutral grid voltage experiences a sudden drop from 220 V rms to 132 V rms. The grid currents and voltages during voltage sag and swell are shown in Figure 17 for phases a and b.

During the voltage swell (right side of the subfigures), the current waveforms promptly return to a steady state following the voltage disturbance. In the center of the figures, a particularly challenging scenario is depicted, corresponding to a 40% voltage swell. In this case, the grid voltage was deliberately increased to an abnormally high level—twice the standard tolerance for swells—to evaluate the performance of the FCS-MPC current controller. According to IEEE Std. 1547-2018 [5], grid-tied inverters must withstand overvoltages of up to 20% of the nominal grid voltage. For larger deviations, the inverter is required to disconnect from the grid. Despite this extreme condition, the proposed controller maintains high-quality current waveforms while the current amplitude is kept constant because of the chosen power injection strategy. It is worth emphasizing that the focus of this work is on the controller’s performance evaluation. In practice, such elevated grid voltages could hypothetically cause permanent damage to the inverter hardware. Furthermore, the current waveform and the $TH{D}_i$ indicator do not exhibit significant deviations compared with normal voltage conditions.

5.6. Sensitivity to Parameter Variations

This work evaluates the parameter sensitivity attributes of C-MPC and S-MPC by analyzing variations in the output filter inductance, which may occur due to aging, heating, or imprecise manufacturing processes. Additionally, since the inductance of the grid is typically unknown, it effectively adds to the total inductance of the filter. Figure 18a,b exhibit the grid current waveforms when the filter inductance is reduced to half of its nominal value, decreasing from 5 mH to 2.5 mH. As expected, this reduction increases the current ripple and degrades $TH{D}_i$, which increases from 3.4% to 9.2% when the C-MPC strategy is used to control the NPC converter and from 3.4% to 10.8% for S-MPC. On the other hand, when the nominal output filter inductance is increased twice, from 5 mH to 10 mH, see Figure 18c,d, the current waveform improves, reflecting a reduced ripple and lower $TH{D}_i$ to 2.1% for C-MPC and to 2.0% for S-MPC.

The results show that both FCS-MPC control approaches exhibit increased sensitivity to reduced inductance values. If a conventional linear controller was used instead of FCS-MPC, the current THD would be expected to double when the inductance is reduced to half its nominal value. However, it is well known that MPC controllers are inherently more affected by inductance variations, as the reduction not only increases current ripple but also amplifies prediction errors. However, the test case was intentionally designed to be severe, aiming to demonstrate that both C-MPC and S-MPC approaches can still deliver acceptable current quality, even under such extreme conditions.

5.7. Performance Summary

The performance indicators discussed in the previous subsections are summarized in

Table 4. Performance summary.

Test Case	Performance Index	C-MPC	S-MPC
Current reference step reference (20 to 30 A) (Figure 13)	$t_{si}$	0.25 μs	0.20 μs
Time required to balance dc–link capacitor’s voltage (Figure 14)	$t_{sb}$	27 ms	48 ms
Current distortion during balancing (Figure 14)	$TH{D}_i$	10.2%	5.2%
Steady-state current ripple (reference of 20 A) (Figure 10)	$\mathsf{\Delta }i$	2.0 A	2.5 A
Steady-state current distortion (reference of 20 A) (Figure 10)	$TH{D}_i$	4.7%	5.0%
Steady-state current ripple (reference of 30 A) (Figure 18)	$\mathsf{\Delta }i$	3.0 A	4.0 A
Steady-state current distortion (reference of 30 A) (Figure 18)	$TH{D}_i$	3.4%	3.4%
Current ripple for 0.5 L (reference of 30 A) (Figure 18)	$\mathsf{\Delta }i$	9.0 A	9.0 A
Current distortion for 0.5 L (reference of 30 A) (Figure 18)	$TH{D}_i$	9.2%	10.8%
Current ripple for 2 L (reference of 30 A) (Figure 18)	$\mathsf{\Delta }i$	9.0 A	1.0 A
Current distortion for 2 L (reference of 30 A) (Figure 18)	$TH{D}_i$	2.1%	2.0%

, considering the THD of the grid current ($TH{D}_i$), the current ripple ($\mathsf{\Delta }i$), and the settling times of the grid currents ($t_{si}$) and dc–link capacitor voltage balancing ($t_{sb}$). The transient performance was similar for both approaches, with C-MPC achieving dc–link voltage balancing faster than that of S-MPC. Steady-state indicators also presented comparable values, highlighting that S-MPC can deliver consistent performance relative to the conventional FCS-MPC method while avoiding the need for exhaustive weighting factor tuning.

6. Conclusions

This paper presents a detailed comparative analysis of classical MPC and sequential MPC strategies applied to a three-level NPC inverter connected to the grid based on HIL real-time simulation. The S-MPC strategy prioritized control objectives sequentially, eliminating the need for weighting factors and simplifying the controller design process. The real-time results demonstrated that both approaches effectively achieve the control objectives of current tracking and voltage balancing of the dc–link capacitors. In a steady state, both approaches yield an acceptable current THD of 3.4%. Furthermore, the S-MPC maintained the voltage balance between the dc–link capacitors, even under transient conditions, yielding a higher quality output current with half the THD of C-MPC during the first transient cycles.

The viability of sequential predictive controllers, particularly for current control applications, is consolidated through the presented results. The study demonstrates that complex converter topologies can be effectively simulated and validated using cost-effective HIL hardware, thereby promoting the adoption of this technology and maximizing its practical impact.

In addition, this work contributes to the dissemination of practical knowledge regarding the deployment of real-time power electronics simulations on HIL systems with limited computational resources. The test scenarios involve a switching power converter with 24 switching elements, implemented on a conventional HIL simulator without relying on the reduced time-step granularity typically available only in high-end, modern HIL platforms. This shows that complex converter topologies can be effectively simulated and validated using cost-effective hardware, thereby contributing to the dissemination of this technology and maximizing the benefits of its adoption.

Future research can explore the use of intelligent algorithms, such as bio-inspired and heuristic algorithms, to support and refine predictive control strategies. These tools could help fine-tune parameters like the weighting factor in C-MPC or improve how voltage vectors are selected in S-MPC schemes. More broadly, adaptive control methods that learn and adjust to changes in real time could offer better performance, especially when dealing with disturbances or variations in grid and inverter characteristics.