A Fast SOC Balancing Method for MMC-BESS Based on Nonlinear Model-Predictive Control

Abstract

In modular multilevel converter battery energy storage systems (MMC-BESS), state-of-charge (SOC) balancing is essential for ensuring safe and reliable operation. Existing methods based on linear controllers or conventional model-predictive control (MPC) often suffer from slow balancing speed, difficult parameter tuning, and high computational burden. To address these challenges, this paper proposes a fast SOC balancing strategy based on nonlinear MPC. A nonlinear state-space model is first developed and then linearized to enable discrete single-step prediction of arm- and phase-level SOC values. A two-stage control scheme is introduced to coordinate inter-arm and inter-phase SOC balancing, significantly reducing the number of state variables involved in the MPC formulation. The proposed method eliminates the need for circulating current reference calculation and control parameter tuning. Simulation results demonstrate that the proposed method takes approximately 17.5 s and 39 s for inter-arm and inter-phase SOC balancing, respectively, while traditional three-level SOC balancing takes approximately 42 s and 88 s.

1. Introduction

The intermittency and volatility of renewable energy pose significant challenges to power system stability at scale [1,2]. Battery energy storage systems effectively mitigate power fluctuations from renewable sources, making the integration of BESSs with renewable generation essential. Among various converter topologies, the modular multilevel converter-based battery energy storage system (MMC-BESS) stands out as a promising solution for large-capacity storage due to its unique advantages [3,4]. The MMC-BESS distributes batteries across submodules, which prevents the ‘bucket effect’ and eliminates parallel circulating currents commonly found in traditional battery arrays with extensive series-parallel connections. However, balancing the State of Charge (SOC) of submodule batteries is critical for safe and reliable MMC-BESS operation [5,6].

Research on SOC-balancing control for MMC-BESS has advanced considerably. Reference [7] introduced a traditional three-level control scheme, but its open-loop structure and reliance on proportional components resulted in slower SOC balancing. References [8,9] implemented independent PI controllers for each submodule storage system, enhancing SOC-balancing performance while simultaneously increasing system complexity and complicating parameter tuning. References [10,11] developed a three-level SOC-balancing strategy by combining PI controller, PR controller, and modulation wave reconstruction techniques, though the carrier phase shift modulation method employed exhibits limited applicability in high-voltage, high-power scenarios. Furthermore, conventional PI/PR controllers are highly dependent on parameter tuning, directly affecting system dynamic response and stability, while demonstrating poor adaptability to system nonlinearities and time-varying parameters [12].

Model-predictive control (MPC) enables real-time management of complex systems through dynamic prediction and cost function optimization, effectively eliminating control-parameter-tuning challenges [13,14]. Recent years have witnessed notable progress in MPC strategies for MMC-BESS systems. Reference [15] introduces a modulation-based MPC approach that directly computes duty cycles between two predefined voltage levels, eliminating weighting factors while preserving constant switching frequency. References [16,17] develop a switching state selection MPC method, where combinatorial complexity remains challenging ($C_{2N}^N$ valid states) despite limiting active submodules to N per phase. Several enhanced MPC variants address specific challenges: Reference [18] achieves superior current quality by expanding voltage levels from N + 1 to 2N + 1 with minimal computational overhead. For SOC balancing, Reference [19] employs a dual-mode strategy using fixed circulating currents for large imbalances and adaptive coefficients for minor corrections, albeit with increased switching losses. Reference [20] implements a precision dual-loop architecture combining SOC prediction with MPC current tracking, though requiring exact parameter matching.

Advanced control architectures include Reference [21]’s computationally demanding but effective dual-layer solution for low-frequency operation and [22]’s hierarchical approach separating global MPC balancing from local virtual resistance control, offering speed–accuracy compromises. Reference [23] further refines balancing through a three-level algorithm with dynamic coefficients, enhancing stability at the cost of control complexity. Finally, Reference [24] presents an adaptive-weight MPC that dynamically adjusts cost functions based on submodule voltages for optimized MMC performance. Reference [25] proposed a hybrid approach using MPC for output current and circulating current control at the submodule level while still relying on PI control for battery-side SOC balancing, failing to achieve direct MPC over SOC equilibrium. References [26,27] employed traditional double-loop PI control for output currents while incorporating MPC for SOC balancing, indirectly achieving SOC balancing through circulating-current-cost functions but lacking direct control over SOC. References [25,28] introduced an MPC methodology for MMC-embedded storage systems that successfully balanced storage submodule SOC and suppressed current ripple, though this approach is limited to storage submodules with supplementary DC-DC converters and cannot be extended to conventional half bridge energy storage submodules. Also, the cost function is developed based on the current of the energy storage unit. Reference [29] presented an enhanced inner- and outer-loop MPC strategy for output-current control, double-loop PI control for DC/DC converters within storage submodules, and improved inner–outer-loop MPC for SOC balancing. While this method demonstrated effective SOC balancing, it still required PR controllers to calculate circulating-current reference values, maintaining dependency on control parameter tuning.

The existing SOC-balancing control methods for MMC-BESS can be summarized in

Table 1. Comparison of the existing SOC-balancing control methods for MMC-BESS.

Control Method	Technical Features	Main Limitations.
Traditional three-level control [7]	Open-loop proportional control and sequencing strategy	Slow speed and sensitive parameters
PI/PR composite control [8,9,10,11,12]	Multi-stage closed-loop architecture	High complexity and poor dynamic response
Indirect MPC [25,26,27]	The SOC is indirectly balanced through the circulation cost function	The PI/PR controller is needed
Direct MPC [25,28]	Based on the SOC prediction model	Only applicable to the submodule with DC-DC converter
Hybrid MPC [15,29]	MPC with conventional controller cooperation	Still dependent on parameter tuning

. It is evident that the current MPC method for SOC balancing has two significant limitations. First, the predictive model and cost function are based on current rather than SOC, which indirectly reflects SOC characteristics. Second, MPC must be combined with PI/PR control because the current reference required for the cost function needs to be calculated. It can be seen from the above that existing MPC research focused on SOC balancing in MMC-BESS primarily addresses storage submodules equipped with DC-DC converters, while comparatively limited attention has been given to MPC for SOC balancing in traditional half-bridge storage submodules. Most approaches indirectly achieve SOC balancing by minimizing circulating current reference value cost functions, necessitating parameter tuning for proportional, PI, or PR control components. Additionally, these control methodologies share an inherent limitation where balancing speed diminishes as SOC deviation decreases.

To address these challenges, this paper proposes an advanced SOC-rapid-balancing technology for MMC-BESSs based on nonlinear MPC. Key innovations include the following: first, establishing a nonlinear state-space model for average SOC values between upper and lower arms and developing a single-step prediction model with deviation cost function for arm and phase average SOC values through linearization and discretization; second, optimizing control stage division and state variable configuration within the overall MPC scheme to substantially reduce the computational burden. The proposed control strategy offers several advantages: complete SOC control without calculating the circulating current; elimination of traditional control-parameter-tuning requirements; and maintenance of consistent SOC-balancing speed regardless of the SOC deviation magnitude.

2. MMC-BESS Topology and Its Traditional Three-Level SOC-Balancing Control

2.1. Topological Structure

The topology of the MMC-BESS and its Energy Submodule (ESM) is shown in Figure 1. Each phase consists of the upper and lower arms. Each arm includes an inductor L_arm, an equivalent resistor R_arm, and N ESMs. The parameters are as follows:

Grid-side parameters: u_sk (k = a, b, c) represents the three-phase grid voltage; L_s and R_s are the equivalent inductance and resistance between the MMC and the grid.

MMC parameters: u_k (k = a, b, c) represents the output AC voltage of the MMC; i_vk (k = a, b, c) represents the output AC current of the MMC.

Arm electrical parameters: u_pk and u_nk (k = a, b, c), respectively, represent the output voltage of the upper and lower arms of phase-k; i_pk and i_nk, respectively, represent the current of the upper and lower arms of phase k.

ESM parameters: The half-bridge topology is adopted, consisting of two IGBTs and one battery pack, where U_cell is the battery pack voltage; u_bat and i_bat are the output voltage and current of the ESM, respectively.

2.2. Model-Predictive Control of Output Current

The MPC algorithm predicts the single-step output current of MMC-BESS, as shown in Equation (1):

$$i_{\mathrm{v}k}\left(t+T_{\mathrm{s}}\right)={\displaystyle \frac{1}{R_{\mathrm{eq}}+L_{\mathrm{eq}}/T_{\mathrm{s}}}}\left[u_k\left(t+T_{\mathrm{s}}\right)-u_{\mathrm{s}k}\left(t+T_{\mathrm{s}}\right)+{\displaystyle \frac{L_{\mathrm{eq}}}{T_s}}{i}_{\mathrm{v}k}\left(t\right)\right]$$

(1)

where i_vk(t + T_s) and i_vk(t) are the predicted value and measured value of the output current of the phase-k, respectively; u_k(t + T_s) is the predicted value of the AC-side voltage of the kth phase of MMC; u_sk(t + T_s) is the predicted value of the grid voltage; L_eq and R_eq are the equivalent inductance and resistance of the AC side, respectively, with L_eq = L_s + L_arm/2, R_eq = R_s + R_arm/2; T_s is the simulation time step.

The cost function of output current is as follows:

$$J_{\mathrm{i}\mathrm{v}k}=\left|i_{\mathrm{v}k}\ast \left(t+T_{\mathrm{s}}\right)-i_{\mathrm{v}k}\left(t+T_{\mathrm{s}}\right)\right|$$

(2)

where i_vk∗(t + T_s) is the reference value of the output current.

2.3. Traditional SOC-Balancing Control

Traditional SOC-balancing control employs a three-level hierarchical architecture that encompasses inter-phase SOC balancing, inter-arm SOC balancing, and submodule SOC balancing within each arm. An open-loop sorting strategy is typically implemented to minimize controller complexity. The process follows a systematic approach, outlined as follows:

(1)

Calculate the required number of submodules (n*) that need to be activated;

(2)

Sort all submodules within the arm according to their estimated SOC values;

(3)

Apply a current-direction-based selection algorithm: when the arm current causes the battery to discharge, the n submodules with the highest SOC values are activated; when it causes charging, those with the lowest SOC values are prioritized.

The SOC value estimation of the submodule utilizes the Coulomb counting method [30], with the specific calculation methodology detailed in Equation (3):

$$SOC\left(t\right)=SOC\left(t_0\right)-{\displaystyle \frac{1}{3600Q_{\max }}}{\displaystyle {\int }_{t_0}^t{i}_{\mathrm{bat}}\left(t\right)dt}$$

(3)

where Q_max represents the battery capacity.

The block diagram of inter-arm SOC-balancing control is presented in Figure 2. Here, ${\overline{\mathrm{SOC}}}_{\mathrm{p}k}$ and ${\overline{\mathrm{SOC}}}_{\mathrm{n}k}$ represent the average SOC values of the upper and lower arms of phase k, respectively; K₃ is the gain coefficient; and $u_{{\mathrm{SOC}}_{\mathrm{a}\mathrm{r}\mathrm{m}k}}^{*}$ can be obtained, which is the reference voltage for achieving SOC balancing between arms.

The block diagram of inter-phase SOC-balancing control is presented in Figure 3. Here, ${\overline{\mathrm{SOC}}}_k$ represents the average SOC value of phase-k, $\overline{\mathrm{SOC}}$ stands for average SOC value of all submodules in the three phases, K₁ and K₂ are gain coefficients, and LPF refers to a low-pass filter. Finally, $u_{{\mathrm{SOC}}_k}^{*}$ can be obtained, which is the reference voltage value for achieving the inter-phase SOC balancing.

3. Nonlinear State-Space Model and Its Linearization

The traditional three-level SOC-balancing control for MMC-BESS has inherent deficiencies, such as slow balancing speed and difficult parameter tuning. To overcome these technical challenges, this paper proposes an SOC-balancing control strategy based on nonlinear model-predictive control, aimed at achieving fast and precise SOC balancing. The following section first establishes a nonlinear state space model for the MMC-BESS system.

This strategy significantly reduces computational burden by decreasing the number of MPC state variables, eliminates the need for calculating arm circulating current references, and achieves fast SOC balancing by only requiring the setting of maximum submodule numbers.

3.1. Nonlinear State-Space Model of MMC-BESS

As shown in Equations (4) and (5), construct the differential dynamic equations of the upper and lower arms.

$$L_{\mathrm{arm}}{\displaystyle \frac{\mathrm{d}{i}_{\mathrm{p}k}}{\mathrm{d}t}}+R_{\mathrm{arm}}{i}_{\mathrm{p}k}+u_{\mathrm{p}k}={\displaystyle \frac{1}{2}}{U}_{\mathrm{DC}}-u_k$$

(4)

$$L_{\mathrm{arm}}{\displaystyle \frac{\mathrm{d}{i}_{\mathrm{n}k}}{\mathrm{d}t}}+R_{\mathrm{arm}}{i}_{\mathrm{n}k}+u_{\mathrm{n}k}=u_k-{\displaystyle \frac{1}{2}}{U}_{\mathrm{DC}}$$

(5)

where U_DC represents the DC-side voltage of MMC-BESS.

Subtracting Equation (5) from Equation (4) yields the dynamic equation governing the MMC output current. This fundamental relationship enables the development of output-current MPC, as formulated in Equations (1) and (2), which will not be discussed in further detail at this juncture.

When Equations (4) and (5) are summed, the differential dynamic equation can be obtained to characterize the arm circulating current:

$$2L_{\mathrm{arm}}{\displaystyle \frac{\mathrm{d}{i}_{\mathrm{c}\mathrm{i}\mathrm{r}k}}{\mathrm{d}t}}+R_{\mathrm{arm}}{i}_{\mathrm{c}\mathrm{i}\mathrm{r}k}+u_{\mathrm{p}k}+u_{\mathrm{n}k}=U_{\mathrm{DC}}$$

(6)

where i_cirk represents the circulating current of phase k, calculated as i_cirk = 0.5 $\times$ (i_pk + i_nk). The values of u_pk and u_nk depend on the number of submodules activated in the upper and lower arms, as shown below:

$$u_{\mathrm{p}k}=\left(N-n_{1k}^{*}+n_{2k}^{*}\right)\overline{U_{\mathrm{c}\mathrm{p}k}}$$

(7)

$$u_{\mathrm{n}k}=\left(n_{1k}^{*}+n_{2k}^{*}\right)\overline{U_{\mathrm{c}\mathrm{n}k}}$$

(8)

where N denotes the total number of submodules within each arm; $n_{1k}^{*}$ and $n_{2k}^{*}$ represent the reference quantity of submodule activation required by output current MPC and inter-arm SOC-balancing control, respectively; $\overline{U_{\mathrm{c}\mathrm{p}k}}$ and $\overline{U_{\mathrm{c}\mathrm{n}k}}$ correspond to the average voltage values across all submodules in the upper and lower arms of phase k, respectively, and must satisfy the conditions $\overline{U_{\mathrm{c}\mathrm{p}k}} = 3 + 1.2{\overline{\mathrm{SOC}}}_{\mathrm{p}k}$, $\overline{U_{\mathrm{c}\mathrm{n}k}} = 3 + 1.2{\overline{\mathrm{SOC}}}_{\mathrm{n}k}$ [5]. It should be noted that the relationship between SOC and the voltage of the battery is nonlinear due to many factors, such as battery material, temperature, etc. In engineering applications, it is necessary to first measure the SOC characteristics of the batteries and fit their nonlinear expressions. Here, the SOC characteristic is simplified to linear expression for analyzing easily. It is important to note that while $n_{1k}^{*}\ge 0$, $n_{2k}^{*}$ can be negative values, indicating the flexibility to increase or decrease the number of activated submodules relative to the baseline established by $n_{1k}^{*}$.

Substituting Equations (7) and (8) into Equation (6), the differential dynamic equation of the phase-k arm circulating current can be obtained.

$$\begin{array}{ll}2L_{\mathrm{arm}}{\displaystyle \frac{\mathrm{d}{i}_{\mathrm{c}\mathrm{i}\mathrm{r}k}}{\mathrm{d}t}}& =U_{\mathrm{DC}}-2R_{\mathrm{arm}}{i}_{\mathrm{c}\mathrm{i}\mathrm{r}k}-1.2\left(N-n_{1k}^{*}+n_{2k}^{*}\right){\overline{SOC}}_{\mathrm{p}k}\\ & +1.2\left(n_{1k}^{*}+n_{2k}^{*}\right){\overline{SOC}}_{\mathrm{n}k}-3\left(N+2n_{2k}^{*}\right)\end{array}$$

(9)

Taking the upper arm of phase-k as an example, assume that the number of submodules put into operation at time t is $(N-n_{1k}^{*}+n_{2k}^{*})$, then it can be obtained that

$$Q_{\max }{\displaystyle \frac{\mathrm{d}{\displaystyle \sum _{i=1}^{N}SO{C}_{\mathrm{p}ki}}}{\mathrm{d}t}}=\left(N-n_{1k}^{*}+n_{2k}^{*}\right)i_{\mathrm{p}k}$$

(10)

Due to

$${\displaystyle \frac{1}{N}}{\displaystyle \sum _{i=1}^{N}SO{C}_{\mathrm{p}ki}}={\overline{SOC}}_{\mathrm{p}k}$$

(11)

Substitute Equation (11) into Equation (10), and considering that i_pk = i_cirk − 0.5i_vk at the same time, this yields

$$Q_{\max }{\displaystyle \frac{\mathrm{d}{\overline{SOC}}_{\mathrm{p}k}}{\mathrm{d}t}}={\displaystyle \frac{N-n_{1k}^{*}+n_{2k}^{*}}{N}}(i_{\mathrm{c}\mathrm{i}\mathrm{r}k}-0.5i_{\mathrm{v}k})$$

(12)

Equation (12) indicates that the average SOC dynamics are primarily governed by three factors: the number of activated submodules, the arm-circulating current, and the output current. Considering that the output current can accurately track its reference value (i.e., i_vk = i*_vk), to simplify the design of the nonlinear MPC controller, Equation (12) can be rewritten as follows:

$$Q_{\max }{\displaystyle \frac{\mathrm{d}{\overline{SOC}}_{\mathrm{p}k}}{\mathrm{d}t}}={\displaystyle \frac{N-n_{1k}^{*}+n_{2k}^{*}}{N}}(i_{\mathrm{c}\mathrm{i}\mathrm{r}k}-0.5i_{\mathrm{v}k}^{*})$$

(13)

Equation (13) demonstrates that, after the aforementioned simplification, the dynamic characteristics of the arm’s average SOC have been completely decoupled from the output current. Following the same derivation process, the dynamic equation for the lower arm’s average SOC can be expressed as in Equation (14):

$$Q_{\max }{\displaystyle \frac{\mathrm{d}{\overline{SOC}}_{\mathrm{n}k}}{\mathrm{d}t}}={\displaystyle \frac{n_{1k}^{*}+n_{2k}^{*}}{N}}(i_{\mathrm{c}\mathrm{i}\mathrm{r}k}+0.5i_{\mathrm{v}k}^{*})$$

(14)

In summary, Equations (9), (13) and (14) constitute the state space model for the average SOC values of the upper and lower arms. Next, we will proceed with the linearization of this state space model.

3.2. Linearization Processing of State-Space Model

Based on the analysis of Equations (9), (13) and (14), it is evident that in the MMC-BESS, there exists a complex coupling relationship between the control variable $n_{1k}^{*}$ and $n_{2k}^{*}$ for output current and SOC balancing, and the state variables i_cirk, ${\overline{\mathrm{SOC}}}_{\mathrm{p}k}$, and ${\overline{\mathrm{SOC}}}_{\mathrm{n}k}$ This results in significant nonlinear characteristics in the state-space model of the average SOC values for the upper and lower arms. Therefore, it is not possible to perform single-step prediction directly based on the discretized differential dynamic equations.

To effectively predict the state of the MMC-BESS, it is necessary to linearize the nonlinear state-space model of the system at each control cycle [31]. The specific linearization process first requires reconstructing Equations (9), (13) and (14) into a standard nonlinear state space model form:

$$\dot{\mathit{x}}=\mathit{f}\left(\mathit{x},\mathit{u}\right)$$

(15)

where x = [i_cirk, ${\overline{\mathrm{SOC}}}_{\mathrm{p}k}$, ${\overline{\mathrm{SOC}}}_{\mathrm{p}k}$]T, u = [$n_{2k}^{*}$].

It is worth noting that, due to the previous decoupling of the arm SOC dynamics from the output current dynamics, there is no need to treat $n_{1k}^{*}$ as an input variable in this model. In practice, it can be viewed as a time-varying system parameter that always can be treated as a constant.

By applying Taylor expansion to Equation (15) at the operating point (x₀, u₀) at time t and neglecting the higher order terms beyond second order, the following can be obtained:

$$\Delta \dot{\mathit{x}}={\left.{\displaystyle \frac{\partial \mathit{f}}{\partial \mathit{x}}}\right|}_{{\mathit{x}}_0}\Delta \mathit{x}+{\left.{\displaystyle \frac{\partial \mathit{f}}{\partial \mathit{u}}}\right|}_{{\mathit{u}}_0}\Delta \mathit{u}=\mathit{A}\Delta \mathit{x}+\mathit{B}\Delta \mathit{u}$$

(16)

where Δx = x − x₀, and Δu = u − u₀. Let A be the system matrix and B be the input matrix. By substituting Equations (9), (13) and (14) into Equation (16), the following can be obtained:

$$\mathit{A}=\left[\begin{array}{ccc}{\displaystyle \frac{R_{\mathrm{arm}}}{L_{\mathrm{arm}}}}& {\displaystyle \frac{0.6\left(n_{1k}^{*}-n_{2k}^{*}-N\right)}{L_{\mathrm{arm}}}}& {\displaystyle \frac{0.6\left(n_{1k}^{*}+n_{2k}^{*}\right)}{L_{\mathrm{arm}}}}\\ {\displaystyle \frac{N-n_{1k}^{*}+n_{2k}^{*}}{N{Q}_{\max }}}& 0& 0\\ {\displaystyle \frac{n_{1k}^{*}+n_{2k}^{*}}{N{Q}_{\max }}}& 0& 0\end{array}\right]$$

(17)

$$\mathit{B}=\left[\begin{array}{c}{\displaystyle \frac{-3-0.6{\overline{SOC}}_{\mathrm{p}k}+0.6{\overline{SOC}}_{\mathrm{n}k}}{L_{\mathrm{arm}}}}\\ {\displaystyle \frac{i_{\mathrm{c}\mathrm{i}\mathrm{r}k}-0.5i_{\mathrm{v}k}^{*}}{N{Q}_{\max }}}\\ {\displaystyle \frac{i_{\mathrm{c}\mathrm{i}\mathrm{r}k}+0.5i_{\mathrm{v}k}^{*}}{N{Q}_{\max }}}\end{array}\right]$$

(18)

Equations (16) and (18) represent the linearized state space model of the arm’s average SOC at time t₀. Similarly to the output-current MPC, we apply the forward Euler method [32] to approximate the discretization of this model. The discretized expression is shown in Equation (19):

$$\Delta \mathit{x}\left(t+T_{\mathrm{s}}\right)=\left(T_{\mathrm{s}}\mathit{A}+\mathit{I}\right)\Delta \mathit{x}\left(t\right)+T_{\mathrm{s}}\mathit{B}\Delta \mathit{u}\left(t+T_{\mathrm{s}}\right)$$

(19)

It should be noted that at time t, when the system is linearized at the operating point and has not been disturbed by changes in input variables, Δx(t) = 0. Therefore, Equation (19) can be simplified to the following:

$$\Delta \mathit{x}\left(t+T_{\mathrm{s}}\right)=T_{\mathrm{s}}\mathit{B}\Delta \mathit{u}\left(t+T_{\mathrm{s}}\right)$$

(20)

Due to

$$\mathit{x}\left(t+T_{\mathrm{s}}\right)=\mathit{x}\left(t\right)+\Delta \mathit{x}\left(t+T_{\mathrm{s}}\right)$$

(21)

Based on Equations (20) and (21), single-step prediction of the target variables that need to be controlled can be performed, which subsequently facilitates the design of the cost function.

4. SOC-Balancing Control Strategy Based on Model-Predictive Control

4.1. MPC for Inter-Arm SOC Balancing

Based on Equations (20) and (21), the SOC-balancing controller between the upper and lower arms is first constructed. Single-step predictions of average SOC values for upper and lower arms of phase k are performed separately. The prediction equations are shown in Equations (22) and (23):

$${\overline{SOC}}_{\mathrm{p}k}\left(t+T_{\mathrm{s}}\right)={\displaystyle \frac{T_{\mathrm{s}}\left(i_{\mathrm{c}\mathrm{i}\mathrm{r}k}\left(t\right)-0.5i_{\mathrm{v}k}^{*}\left(t\right)\right)}{N{Q}_{\max }}}\left(n_{2k}^{*}\left(t+T_{\mathrm{s}}\right)-n_{2k}^{*}\left(t\right)\right)+{\overline{SOC}}_{\mathrm{p}k}\left(t\right)$$

(22)

$${\overline{SOC}}_{\mathrm{n}k}\left(t+T_{\mathrm{s}}\right)={\displaystyle \frac{T_{\mathrm{s}}\left(i_{\mathrm{c}\mathrm{i}\mathrm{r}k}\left(t\right)+0.5i_{\mathrm{v}k}^{*}\left(t\right)\right)}{N{Q}_{\max }}}\left(n_{2k}^{*}\left(t+T_{\mathrm{s}}\right)-n_{2k}^{*}\left(t\right)\right)+{\overline{SOC}}_{\mathrm{n}k}\left(t\right)$$

(23)

The cost function of the inter-arm SOC balancing can be designed as follows:

$$J_{\mathrm{SOC\_arm}}=\left|{\overline{SOC}}_{\mathrm{p}k}\left(t+T_{\mathrm{s}}\right)-{\overline{SOC}}_{\mathrm{n}k}\left(t+T_{\mathrm{s}}\right)\right|$$

(24)

Considering the computational efficiency requirements for practical controller applications, this paper retains the sorting-control method described in Section 2.3 for SOC-balancing control among submodules within each arm. This design strategy significantly reduces the number of switching state combinations that need to be considered, thereby effectively simplifying the complexity of the model-predictive controller design and making it more suitable for practical simulation verification and hardware implementation.

4.2. MPC for Inter-Phase SOC Balancing

For inter-phase SOC-balancing control, by adding Equations (22) and (23), the single-step prediction value of the average SOC for a phase can be obtained as follows:

$$\begin{array}{cc}{\overline{SOC}}_k\left(t+T_{\mathrm{s}}\right)& =0.5\left({\overline{SOC}}_{\mathrm{p}k}\left(t+T_{\mathrm{s}}\right)+{\overline{SOC}}_{\mathrm{n}k}\left(t+T_{\mathrm{s}}\right)\right)\hfill \\ & ={\displaystyle \frac{T_{\mathrm{s}}{i}_{\mathrm{c}\mathrm{i}\mathrm{r}k}\left(t\right)}{N{Q}_{\max }}}\left(n_{2k}^{*}\left(t+T_{\mathrm{s}}\right)-n_{2k}^{*}\left(t\right)\right)+{\overline{SOC}}_k\left(t\right)\end{array}$$

(25)

The average value of the three phase SOC can be expressed as follows:

$$\overline{SOC}\left(t+T_{\mathrm{s}}\right)={\displaystyle \frac{{\overline{SOC}}_{\mathrm{a}}\left(t+T_{\mathrm{s}}\right)+{\overline{SOC}}_{\mathrm{b}}\left(t+T_{\mathrm{s}}\right)+{\overline{SOC}}_{\mathrm{c}}\left(t+T_{\mathrm{s}}\right)}{3}}$$

(26)

For the inter-phase SOC balance control, its cost function can be designed as follows:

$$\begin{array}{ll}{J}_{\mathrm{SOC\_pha}}=& \left|\overline{SOC}\left(t+T_{\mathrm{s}}\right)-{\overline{SOC}}_{\mathrm{a}}\left(t+T_{\mathrm{s}}\right)\right|+\\ & \left|\overline{SOC}\left(t+T_{\mathrm{s}}\right)-{\overline{SOC}}_{\mathrm{b}}\left(t+T_{\mathrm{s}}\right)\right|+\\ & \left|\overline{SOC}\left(t+T_{\mathrm{s}}\right)-{\overline{SOC}}_{\mathrm{c}}\left(t+T_{\mathrm{s}}\right)\right|\end{array}$$

(27)

4.3. MPC Scheme Design Considering Inter-Arm and Inter-Phase SOC Balancing

By integrating the strategies proposed in Section 2.2, Section 4.1 and Section 4.2, an overall MPC strategy for MMC-BESS that considers both inter-arm and inter-phase SOC balancing can be constructed. Based on the different number of control states, this paper proposes two design schemes.

(1)

Design Scheme One: Unified Control Approach

This scheme adopts a unified cost function to simultaneously achieve both inter-arm and inter-phase SOC-balancing control. Specifically, $n_{2k}^{*}$ is obtained by optimizing the cost function and then added to the $n_{1k}^{*}$ to determine the number of submodules to be inserted in the upper and lower arms of each phase. Combining Equations (24) and (27), the unified SOC-balancing cost function can be expressed as follows:

$$J_{\mathrm{SOC}}={\lambda }_1{J}_{\mathrm{SOC\_arm}}+{\lambda }_2{J}_{\mathrm{SOC\_pha}}$$

(28)

where λ₁ and λ₂ are the weighting coefficients for inter-arm and inter-phase SOC balancing, respectively.

This scheme enables simultaneous inter-arm and inter-phase SOC balancing between arms and phases, with the flexibility to control the balancing speed at different levels by adjusting the weighting coefficients. However, this design scheme also presents significant computational burden issues. The specific analysis is as follows:

Assume the maximum number of submodules for output current control and SOC balancing are N₁ and N₂, respectively, with N₁ + N₂ = N, then $n_{2k}^{*}$ must satisfy the following:

$$-N_2\le n_{2k}^{*}\le N_2, n_{2k}^{*}\in {\mathbf{N}}^{+}$$

(29)

From Equation (29), it can be seen that $n_{2k}^{*}$ includes (2N₂ + 1) state variables. When calculating the cost function in Equation (27), nested loops through $n_{2k}^{*}$ of all three phases are required, resulting in (2N₂ + 1)³ states to be processed at each control step. The prediction of average SOC values for upper and lower arms and phase units must be calculated at each step. When a faster SOC balancing speed is required, a larger value of N₂ causes the number of states to grow exponentially as a cubic function, imposing a significant computational burden.

(2)

Design Scheme Two: Staged Control Approach

To reduce the computational complexity of the MPC, this paper proposes a staged control design scheme. This approach implements inter-arm and inter-phase SOC balancing separately, with the following control strategy: The system prioritizes SOC-balancing control between the upper and lower arms of each phase. When $\left|\overline{{SOC}_{pk} }-\overline{{ SOC}_{nk}}\right|$ is detected to be less than a preset error threshold δ_arm, the controller automatically switches to inter-phase SOC-balancing mode, while temporarily suspending inter-arm SOC balancing. If $\left|\overline{{SOC}_{pk} }-\overline{{SOC}_{nk}}\right|$ subsequently exceeds the preset error threshold δ_arm, inter-arm SOC-balancing control is reactivated.

In this scheme, the maximum number of submodules for upper- and lower-arm SOC balancing and inter-phase SOC balancing is set as N₂₁ and N₂₂, respectively, with N₂₁ + N₂₂ = N₂. According to the analysis in Equation (24), the number of states to consider for inter-arm SOC-balancing control is 2N₂₁ + 1, and the three phases can be computed in parallel without nested loops; inter-phase SOC-balancing control considers (2N₂₂ + 1)³ states. Compared to the first scheme, this design significantly reduces the number of switching states.

Further analysis shows that the number of states for inter-phase SOC-balancing control can be further optimized. This is because inter-phase SOC balancing is essentially achieved by adjusting the DC component of the circulating current in each phase arm. When additional submodules are simultaneously inserted in both the upper and lower arms of a phase, the DC-side voltage of that phase momentarily increases relative to the other two phases, causing the incremental circulating current to accelerate the discharge process of the ESM, thereby reducing the average SOC value of that phase.

Based on this analysis, in inter-phase SOC-balancing control, it is only necessary to insert additional submodules in the two phases with higher average SOC values, while the phase with the lowest SOC average does not require extra control, to achieve convergence of the three phase SOC averages. This optimization means that the two phases with higher SOC only need to consider the number of additional submodules to be inserted, without considering removal operations, while the phase with the lowest SOC requires no additional control. Therefore, the number of switching states for inter-phase SOC-balancing control can be further reduced to (N₂₂ + 1)².

Through in depth analysis of the control performance of the two design schemes, research has found that the second design scheme offers significant computational efficiency advantages, reducing the computational complexity from cubic exponential to square exponential, effectively alleviating the computational burden on the controller. Although this scheme has certain limitations in terms of the utilization efficiency of submodule regulation capability and requires additional optimization of the N₂₁ and N₂₂ parameters, considering the key requirements of the system’s actual operational performance, especially the important impact of computational burden on the control system, this paper ultimately chooses to adopt this staged control strategy as the overall MPC scheme for SOC balancing in MMC-BESS. The specific implementation process of this control scheme is shown in Figure 4.

As shown in Figure 4, the stage control scheme consists of two parts: MPC for output current and MPC for SOC balancing. These two components operate in parallel without interfering with each other. The output current MPC can be divided into three steps:

Step 1: Initialize J_{_ivk} as infinity.

Step 2: Iteratively compute i_vk(t + T_s) and J_{_ivk} within the interval [0, N₁] based on Equations (1) and (2).

Step 3: Obtain the control input n*_1k that minimizes J_{_ivk}.

Similarly, the SOC balancing MPC can also be divided into three steps:

Step 1: Initially, perform a conditional judgment of J_{SOC_arm}. If J_{SOC_arm} is not less than δ_arm, the inter-arm SOC is not considered balanced, and J_{SOC_arm} is continuously updated through a simple for-loop over [−N₂₁, N₂₁] according to Equations (22)–(24) until the control input n*_2k that minimizes J_{SOC_arm} is found and J_{SOC_arm} < δ_arm.

Step 2: If J_{SOC_arm} < δ_arm, the inter-arm SOC is balanced. Then, the two phases with higher average SOC_k are selected to insert additional sub-modules. J_{SOC_pha} is continuously updated through double for-loops over [0, N₂₂] according to Equations (25)–(27) to find the control input n*_2k that minimizes J_{SOC_pha}.

Step 3: The upper and lower arm control signals (N − n*_1k + n*_2k) and (n*_1k + n*_2k) are obtained, respectively. It should be noted that the control modes for inter-arm and inter-phase SOC balancing dynamically switch during the operation of the MMC-BESS to ensure stable operation.

5. Simulation Verification

5.1. Simulation Parameters

To verify the effectiveness of the proposed overall MPC strategy and demonstrate its advantages over traditional SOC-balancing control methods, this section builds a complete MMC-BESS system simulation model based on the MATLAB(R2022b)/SIMULINK simulation platform. The topology of the simulation system is shown in Figure 1, and the main simulation parameters are shown in

Table 2. Simulation parameters of MMC-BESS system.

Type	Items	Values
Circuit parameters	Grid voltage	35 kV
	Rated output power	50 MW
	Equivalent inductance (Ls)	2.2 mH
	Equivalent resistance (Rs)	10 mΩ
	No. of ESMs within each arm (N)	80
	Arm inductance (Larm)	0.6 mH
	Arm equivalent resistance (Rarm)	200 mΩ
	Rated capacity of battery pack (Qmax)	1000 Ah
	Rated battery pack voltage (Ucell)	800 V
Control parameters	Control step size	100 μs
	No. of ESMs for output current (N1)	75
	No. of ESMs for SOC balancing (N2)	5
	No. of ESMs for inter-arm SOC balancing (N21)	3
	No. of ESMs for inter-phase SOC balancing (N22)	2

.

The parameter selection in Table 2 was carefully designed based on both theoretical requirements and practical engineering considerations:

Circuit Parameters: The 35 kV/50 MW configuration represents a popular medium-voltage application for renewable energy integration in China. The arm inductance (0.6 mH) and resistance (200 mΩ) were calculated to limit the circulating-current ripple below 10% of the rated current. The 800 V battery voltage was selected to maintain a safe 2:1 margin below the 1700 V IGBT rating, ensuring robust switching operation. The 80 submodules per arm provide sufficient voltage resolution for 35 kV grid integration while allowing redundancy for fault tolerance.

Control Optimization: The 100 μs control step balances computational feasibility with control precision. The submodule allocation (N₁ = 75, N₂ = 5) maximizes output current control (N₁ covers > 90% normal operation) while reserving adequate modules (N₂) for balancing. As demonstrated in Section 5.4, the N₂₁:N₂₂ = 3:2 ratio achieves optimal balancing efficiency.

5.2. Simulation Results of the Proposed SOC-Balancing Control

The initial simulation conditions are set as follows: the average SOC values of the upper- and lower-arms of phase-a are ${\overline{\mathrm{SOC}}}_{\mathrm{pa}}\left(0\right)$ = 100% and ${\overline{\mathrm{SOC}}}_{\mathrm{na}}\left(0\right)$ = 99.5%, respectively; the average SOC values of the upper and lower arms of phase b are ${\overline{\mathrm{SOC}}}_{\mathrm{pb}}\left(0\right)$ = 99.5% and ${\overline{\mathrm{SOC}}}_{\mathrm{nb}}\left(0\right)$ = 99%, respectively; and the average SOC values of the upper and lower arms of phase-c are ${\overline{\mathrm{SOC}}}_{\mathrm{pc}}\left(0\right)$ = 99% and ${\overline{\mathrm{SOC}}}_{\mathrm{nc}}\left(0\right)$ = 98.5%, respectively. The overall MPC strategy is activated at 0 s, and the simulation results are shown in Figure 5 and Figure 6. Figure 5 shows the dynamic response characteristics of the AC-side current and voltage of the MMC-BESS system, and Figure 6 presents the dynamic change processes of the upper- and lower-arm average SOC values, inter-phase average SOC values, and circulating currents of each bridge arm.

As shown in Figure 5, the proposed control strategy can ensure the stable operation of MMC-BESS. Specifically, MMC-BESS can output stable fundamental frequency output voltage and output current. It is worth noting that during the inter-arm SOC-balancing control process, the basic electrical characteristics of MMC-BESS are not significantly disturbed, maintaining good dynamic performance.

The overall MPC strategy proposed in this paper demonstrates good dynamic characteristics during the SOC-balancing process, as shown in Figure 6. The control process can be divided into two main stages: inter-arm SOC balancing and inter-phase SOC balancing.

In the first stage (0–17.5 s), the system prioritizes SOC balancing between the upper and lower arms of each phase. Figure 6a,b show that the arms with higher average SOC values exhibit a decreasing trend, while those with lower values gradually increase. When the deviation of average SOC values between the upper and lower arms of each phase drops below the preset threshold δ_arm (0.001%), it marks the completion of inter-arm SOC balancing.

The second stage (17.5–39.0 s) mainly achieves inter-phase SOC balancing. Since phase-a and phase-b have higher initial average SOC values, the system prioritizes inserting additional submodules in these two phases. First, phase-a, which has the highest average SOC value, inserts additional submodules, causing its average SOC value to decrease while driving the average SOC values of other phases to increase. At 30.0 s, the average SOC value of phase-a approaches the total average SOC value of the three phases. Subsequently, phase-b becomes the new phase with the highest SOC and begins to insert additional submodules. Since phase-a maintains the insertion of additional submodules, phase-b submodules do not discharge to phase-a, keeping phase a SOC stable while phase-b SOC decreases and phase-c SOC continues to increase. Finally, at 39.0 s, the system achieves complete inter-phase SOC balancing.

The dynamic characteristics of the circulating currents (Figure 6c) clearly demonstrate the four stages of the entire control process. During the inter-arm SOC-balancing stage, the circulating currents are dominated by output-current components, which are used to eliminate SOC deviations between arms. After 17.5 s, the circulating currents transform to primarily DC components, manifested as negative values for phase a and positive values for phases b and c, indicating that phase a is charging phases b and c. Around 30.0 s, when phase b inserts additional submodules, since the SOC deviation temporarily exceeds the threshold δ_arm, the system briefly resumes inter-arm balancing control, and output current components reappear in the circulating currents. After the inter-arm SOC is rebalanced, the system continues with inter-phase balancing control, and finally achieves comprehensive balancing at 39 s, with the three phase-circulating currents reduced to zero.

5.3. Comparison with Traditional SOC-Balancing Control Method

To comprehensively verify the advantages of the MPC scheme proposed in this paper over traditional three-level SOC-balancing control, this section conducts a comparative analysis in the same MMC-BESS simulation system. Using the traditional control system described in Section 2.3, maintaining the initial average SOC values of each arm consistent with Section 5.1, and setting control parameters K₁ = 100, K₂ = 5, K₃ = 4. After enabling the three-level SOC-balancing control at 0 s, the dynamic response characteristics of the system are shown in Figure 7.

The results indicate that the traditional scheme suffers from considerably longer balancing times: SOC balancing between the upper and lower arms of each phase takes approximately 42.0 s, while the proposed scheme requires only 17.5 s; SOC balancing between phases takes approximately 88 s, while the proposed scheme requires only 39.0 s. This comparison clearly highlights the superiority of the MPC strategy proposed in this paper in improving SOC-balancing rates.

Detailed analysis reveals the following limitations of traditional three-level SOC-balancing control: First, the selection of control parameters faces a dilemma. Although the balancing rate can be changed by adjusting K₁, K₂, and K₃, excessive adjustment will cause overshoot in the reference values of arm voltage, affecting system operational stability. In contrast, the MPC strategy proposed in this paper does not require parameter tuning, only needing to select the maximum number of submodules for each control stage under the premise of satisfying total quantity constraints, fundamentally avoiding the overshoot problem. Second, due to the use of proportional control, the balancing speed of the traditional scheme is positively correlated with SOC deviation, resulting in slower speed as the deviation decreases. Even introducing an integral component cannot completely solve this problem. However, the MPC strategy proposed in this paper, as shown in Figure 6, achieves linear SOC reduction in each control stage, maintaining a stable balancing speed. These analysis results fully demonstrate the comprehensive advantages of the control strategy proposed in this paper in terms of balancing speed, parameter design, and dynamic characteristics.

5.4. Comparison of SOC Balancing Rates with Different Submodule Number Proportions

Although the MPC system proposed in this paper cannot adjust the SOC balancing speed through traditional proportional or integral components, it can achieve balancing rate adjustment by optimizing the number of MPC submodules for inter-arm and inter-phase SOC balancing (N₂₁ and N₂₂).

To thoroughly investigate the impact of submodule number proportions on balancing performance, this section conducted a detailed analysis of four different proportion schemes while keeping N₁ and N₂ constant: (N₂₁ = 1, N₂₂ = 4), (N₂₁ = 2, N₂₂ = 3), (N₂₁ = 3, N₂₂ = 2), and (N₂₁ = 4, N₂₂ = 1). The simulation system used the same initial SOC conditions as in Section 4.2, focusing on examining the variation characteristics of the inter-arm SOC cost function J_{SOC_arm} (using phase a as an example) and the inter-phase cost function J_{SOC_pha}. The results are shown in Figure 8.

From Figure 8, three key findings can be found as follows: First, increasing N₂₁ and decreasing N₂₂ result in shorter inter-arm SOC-balancing time and improved inter-phase SOC-balancing speed.

Table 3. Comparison of SOC-balancing time.

Condition	Inter-Arm	Inter-Phase	Overall
(N21 = 1, N22 = 4)	54.5 s	15.5 s	70.0 s
(N21 = 2, N22 = 3)	26.0 s	17.5 s	43.5 s
(N21 = 3, N22 = 2)	17.5 s	21.5 s	39.0 s
(N21 = 4, N22 = 1)	13.0 s	43.0 s	56.0 s

lists detailed balancing time data for each proportion scheme, showing that the maximum number of submodules for each control section is positively correlated with the balancing rate. However, this enhancement effect exhibits diminishing returns, meaning that as the number of submodules increases, the magnitude of reduction in balancing time gradually decreases. Also, it can be seen from Figure 8b that the declining rate of J_{SOC_pha} is not always the same which has a turning point. The reason for this phenomenon is two phase units reach SOC balancing after a certain time during the inter-phase SOC-balancing control mode.

Second, in terms of overall SOC balancing time, simply increasing N₂₁ or N₂₂ cannot effectively shorten the system’s overall balancing time. Research has found that when the values of N₂₁ and N₂₂ are close, the system can achieve relatively optimal overall balancing performance. This finding provides important guidance for parameter selection in engineering practice.

Finally, it is worth noting that although increasing N₂ can also shorten SOC balancing time, this will correspondingly reduce the value of N₁, thereby affecting the maximum output power of MMC-BESS. Therefore, the value of N₂ should be determined based on the maximum output power requirements of MMC-BESS.

5.5. Comparison of Computation Burden Between Unified and Staged-Control Approach

In order to verify the advantages of staged control over unified control in terms of computational burden, Simulink Profiler is used to analyze the computation time of the MPC part in the simulation model under the two control schemes. The operating system is Windows 10, the CPU is i5-13600KF, and the simulation duration is set to 15 s. The CPU time results are presented in

Table 4. Comparison of CPU time between unified and staged-control scheme.

Control Scheme	CPU Time
Unified Control	45.682 s
Staged Control (N21 = 1, N22 = 4)	4.882 s
Staged Control (N21 = 2, N22 = 3)	4.837 s
Staged Control (N21 = 3, N22 = 2)	4.808 s
Staged Control (N21 = 4, N22 = 1)	4.796 s

below. It can be observed that the CPU time increases slightly as N₂₂ increases gradually, indicating that the computational burden of staged control is marginally influenced by N₂₂. In contrast, the CPU time for unified control is nearly 45 s, which is approximately 10 times higher than that of staged control, imposing a significantly greater computational burden on the CPU. Therefore, staged control substantially reduces the computational burden compared to unified control.

6. Conclusions

This paper proposes a fast SOC-balancing strategy for MMC-BESS based on nonlinear model-predictive control. By constructing and linearizing a nonlinear state-space model, the proposed method enables direct prediction of inter-arm and inter-phase SOC estimations with minimal computational overhead. The staged-control strategy eliminates the need for circulating current reference calculation and parameter tuning while maintaining consistent balancing speed. Simulation results indicate that the proposed method achieves inter-arm SOC balancing in approximately 17.5 s and inter-phase SOC balancing in approximately 39.0 s. In comparison, traditional three-level SOC balancing requires approximately 42.0 s and 88 s, respectively, representing reductions of 58% and 56% in balancing times for inter-arm and inter-phase SOC, respectively. Additionally, the analysis of various submodule allocation strategies offers practical insights into parameter optimization. However, the Coulomb counting method employed for SOC estimation in this study is prone to accumulating errors over time, which may lead to inaccurate SOC predictions and degrade the performance of NMPC. Future research will focus on integrating more precise SOC estimation models to enhance the balancing accuracy.