An Improved Space Vector PWM Algorithm with a Seven-Stage Switching Sequence for Three-Level Neutral Point Clamped Voltage Source Inverters

Abstract

The main purpose of this research is to develop an improved space vector pulse-width modulation (SVPWM) algorithm for three-level (3L) neutral point clamped (NPC) voltage source inverters (VSIs). The results of experiments conducted on the three-level power converter laboratory setup showed that the proposed SVPWM algorithm with a seven-stage switching sequence (SS) can reduce a VSI’s switching frequency by 43.48% compared to the SVPWM algorithm with the base SS. It also improves the neutral point (NP) voltage balance in the VSI DC link by 4.2% by controlling the duty factor of distributed base vectors in each SVPWM period based on phase load currents. It reduced the values of the 5th- and 7th-order harmonics of the VSI output voltage by 19% and 15.7%, respectively. The results show that the usage of the improved SVPWM algorithm helps increase the efficiency of a 3L NPC VSI by 0.6% and reduce the higher harmonics. The obtained results confirm the efficiency of the suggested algorithm and its great potential for power converters in industry.

1. Introduction

In recent decades, the production of electronic components, including semiconductor modules, has seen rapid growth, leading to the deployment of new frequency converter (FC) technologies. The world’s largest control and automation companies like Rockwell Automation Inc. (Milwaukee, WI, USA), Schneider Electric (Rueil-Malmaison, France), Honeywell Automation (Maharashtra, India), Siemens Industry Inc. (München, Germany), ABB Ltd. (Zurich, Switzerland), Fuji Electric Co. (Kawasaki, Japan), etc., are investing in the development of semiconductor technologies and microchips. These efforts promote the emergence of high-efficiency converter modules used in controlled electric drives (EDs) [1,2].

Multiple FC topologies have been developed based on voltage source inverters (VSIs) to accommodate high power and voltage ratings. Based on design features, these can be divided into two main groups: direct-frequency converters (DFCs) and back-to-back-frequency converters (BBFCs). DFCs are based on reversible thyristor converters that transmit the voltage from the power grid directly to the motor through controlled power modules. BBFCs include two links: the first link is the rectifier, and the second is the inverter. Today, BBFC solutions are more popular in high-power electric drives as they support a wide electric motor speed control range and two-way energy exchange between the load and the grid.

BBFCs based on a three-level (3L) topology with the neutral point clamped (NPC) were first proposed by A. Nabae, I. Takahashi, and H. Akagi in 1981 [3] and became one of the most popular options in the energy sector and industries. The space vector pulse-width modulation (SVPWM) algorithm is often used in industrial FCs based on VSIs. Apart from improving the converted power quality, it can also solve problems like reducing switching loss, ensuring neutral point (NP) voltage balance, and reducing the common-mode (CM) voltage [4]. Due to its functionality, the SVPWM algorithm remains relevant and has the capacity for further development, especially in the context of improving energy efficiency and providing electromagnetic compatibility.

Currently, various methods are used to balance NP voltage in 3L VSIs. These include known solutions related to hardware implementation using separate DC sources to maintain the voltage of each capacitor [5] or using a special additional circuit [6,7]. When the first approach is applied, a direct current source is generally obtained using a transformer and a diode bridge rectifier. However, such a source is large, heavy, inefficient, and expensive, and it can also have a detrimental effect on the quality of electricity consumed. The second approach involves the use of auxiliary power equipment, for example, power modules and reactors that inject an external current into a neutral point to compensate for the voltage difference between two DC-link capacitors. A common disadvantage of these two methods is the increase in the converter weight, dimensions, cost, and reliability. Therefore, the development of control algorithms for NP voltage balancing without the use of additional power equipment remains a relevant task.

A variety of PWM methods have been proposed for 3L NPC VSIs. These methods include the sinusoidal PWM algorithm based on carrier signals [8] and SVPWM [9]. On the basis of these methods, many ways to control the NP voltage have been developed. Thus, in [10,11], methods for controlling the NP voltage balance using a sinusoidal PWM based on carrier signals are provided. However, the effectiveness of these methods strongly depends on the reactance of the load and the modulation index. In addition, there are inherent disadvantages of the carrier-based PWM algorithm, such as limited control flexibility, high switching loss, low efficiency, etc. In [12], a virtual SVPWM was proposed in which the spatial voltage vector is synthesized from virtual vectors based on the already existing base vectors of the VSI. During operation, virtual vectors are formed in such a way that the NP current tends towards zero. This control method provides a sufficiently high level of NP voltage balance under any inverter condition. However, the switching frequency increases dramatically here, thus causing a deterioration in the inverter efficiency.

Another approach is to change the switching sequence (SS) for the SVPWM algorithm. In [13], the proposed control system uses a large number of base vector combinations to suppress the NP current, which inevitably causes an increase in the VSI switching loss. Therefore, in terms of minimizing VIS switching loss, a seven-stage SS is of great interest, where the NP voltage is controlled by regulating the turn-on/off of small base vector combinations [14,15]. In these papers, the NP voltage balance can be carried out in both open and closed systems due to the feedback signal on the voltage deviation of the two DC-link capacitors. In both cases, the proposed algorithms make it possible to reduce the level of NP voltage imbalance but do not eliminate it, which makes it urgent to develop algorithms for controlling NP voltage balance with a minimum error level.

The novelty of this research consists in suggesting a new and improved SVPWM algorithm with a seven-stage switching sequence (SS) that can reduce the amount of power key switching per one period of the main frequency at the inverter output by 43.3% on average across the inverter duty factor change range compared to the 3L NPC VSI control methods. It also suggests the improvement of the NP voltage balance in the DC link by controlling the duty factor of distributed base vectors in each PWM period based on phase load currents, thus improving the quality of output voltage and current. The energy efficiency of the proposed algorithm has been confirmed with the three-level power converter laboratory setup and computer modeling.

2. SVPWM Algorithm with the Base Switching Sequence for the 3L NPC VSI

The SVPWM algorithm proved itself as one of the most promising approaches to 3L NPC VSI control due to its high flexibility and applicability in a wide range of problems depending on the specific requirements of the ED system. This algorithm does not calculate instant voltage values when implemented. Instead, it calculates the moments and durations of power key activation to generate a spatial voltage vector represented by a system of three-phase voltages [16,17]

$${\overrightarrow{u}}_S={\displaystyle \frac{2}{3}}\left(u_a+u_b\cdot e^{j{\displaystyle \frac{2\pi }{3}}}+u_c\cdot e^{j{\displaystyle \frac{4\pi }{3}}}\right)$$

(1)

Based on the (1) conversion, base voltage vectors are created whose numbers are determined by the number of VSI levels. For 3L NPC VSIs, there are 19 base vectors, which correspond to 27 state combinations. These vectors form a vector diagram split into 6 sectors composed of 4 segments a. Depending on the length, these base vectors can be divided into 6 large ${\overline{U}}_{\mathrm{L}1}$…${\overline{U}}_{\mathrm{L}6}$; 6 medium ${\overline{U}}_{\mathrm{M}1}$…${\overline{U}}_{\mathrm{M}6}$; 6 small vectors ${\overline{U}}_{\mathrm{S}1}$…${\overline{U}}_{\mathrm{S}6}$, and 1 zero vector ${\overline{U}}_0$ [18,19]. Small base vectors are formed from 12 combinations, 6 of which are p-type (no state [N]), while the other 6 are n-type (no state [P]).

The control parameters of the algorithm include spatial vector coordinates (module and rotation angle) set by the durations of base vector activation. Normally, the spatial vector ${\overline{U}}_s$ is modulated based on the three nearest base vectors following the volt-second balance principle [20]. For instance, for segment 1 (sector II) (see Figure 1), vector ${\overline{U}}_s$ can be represented as a system of equations:

$$\left\{\begin{array}{l}{\overline{U}}_s={\gamma }_1{\overline{U}}_{\mathrm{S}2}+{\gamma }_2{\overline{U}}_{\mathrm{S}3}+{\gamma }_3{\overline{U}}_0;\\ {\gamma }_1+{\gamma }_2+{\gamma }_3=1,\end{array}\right.$$

(2)

where ${\gamma }_1=t_1/T_{PWM}$; ${\gamma }_2=t_2/T_{PWM}$; and ${\gamma }_3=t_3/T_{PWM}$ are relative durations of activation for base vectors ${\overline{U}}_{\mathrm{S}2}$, ${\overline{U}}_{\mathrm{S}3}$, and, respectively, and t₁, t₂, and t₃ are their absolute values.

The projections of the spatial vector ${\overline{U}}_s$ on the edges of the respective sector can be calculated using the following expressions:

$$\left\{\begin{array}{l}{\overline{U}}_{1s}={\displaystyle \frac{2}{\sqrt{3}}}{m}_s\sin \left(N_{\sec }\cdot {\displaystyle \frac{\pi }{3}}-{\theta }_s\right);\\ {\overline{U}}_{2s}={\displaystyle \frac{2}{\sqrt{3}}}{m}_s\sin \left[{\theta }_s-\left(N_{\sec }-1\right)\cdot {\displaystyle \frac{\pi }{3}}\right],\end{array}\right.$$

(3)

where $m_s={\displaystyle \frac{U_s}{U_{dc}/\sqrt{3}}}$ is the modulation factor; θ_s is the rotation angle of the vector ${\overline{U}}_s$; and N_sec = 1…6 is the number of the sector containing the vector ${\overline{U}}_s$.

These expressions evaluate the projections of the spatial vector ${\overline{U}}_s$ on sector borders in any of the four segments. Expressions (3) show that these projections depend on the modulation index m_s, which affects the length of the vector ${\overline{U}}_s$, sector number N_sec, and current control angle θ_s, which changes in real time when the vector ${\overline{U}}_s$ rotates.

The sector number and the relative duration of the nearest base vector activation duration can be determined using the expressions in

Table 1. Determining relative durations γ₁, γ₂, γ₃, and the segment number.

Segment	Nseg = 1	Nseg = 2	Nseg = 3	Nseg = 4
Condition	$\left\{\begin{array}{l}{\overline{U}}_{1s}\le 1/\sqrt{3};\\ {\overline{U}}_{2s}\le 1/\sqrt{3};\\ {\overline{U}}_{1s}+{\overline{U}}_{2s}\le 1/\sqrt{3}.\end{array}\right.$	${\overline{U}}_{1s}>1/\sqrt{3}$	$\left\{\begin{array}{l}{\overline{U}}_{1s}\le 1/\sqrt{3};\\ {\overline{U}}_{2s}\le 1/\sqrt{3};\\ {\overline{U}}_{1s}+{\overline{U}}_{2s}>1/\sqrt{3}.\end{array}\right.$	${\overline{U}}_{2s}>1/\sqrt{3}$
Values γ1, γ2, γ3	$\left\{\begin{array}{l}{\gamma }_1=\sqrt{3}\cdot {\overline{U}}_{1s};\\ {\gamma }_2=\sqrt{3}\cdot {\overline{U}}_{2s};\\ {\gamma }_3=1-{\gamma }_1-{\gamma }_2.\end{array}\right.$	$\left\{\begin{array}{l}{\gamma }_1=\sqrt{3}\cdot {\overline{U}}_{1s}-1;\\ {\gamma }_2=\sqrt{3}\cdot {\overline{U}}_{2s};\\ {\gamma }_3=1-{\gamma }_1-{\gamma }_2.\end{array}\right.$	$\left\{\begin{array}{l}{\gamma }_1=1-\sqrt{3}\cdot {\overline{U}}_{2s};\\ {\gamma }_2=1-\sqrt{3}\cdot {\overline{U}}_{1s};\\ {\gamma }_3=1-{\gamma }_1-{\gamma }_2.\end{array}\right.$	$\left\{\begin{array}{l}{\gamma }_1=\sqrt{3}\cdot {\overline{U}}_{1s};\\ {\gamma }_2=\sqrt{3}\cdot {\overline{U}}_{2s}-1;\\ {\gamma }_3=1-{\gamma }_1-{\gamma }_2.\end{array}\right.$

.

In 3L NPC VSIs, the imbalance of voltage between the two capacitors C_d1 and C_d2 in the DC link (neutral point voltage imbalance) is one of the inevitable technical problems causing the following negative effects: (1) overvoltage on passive and active circuit elements, which may result in the reduction in their service life and even failure; (2) output voltage asymmetry causing voltage and current curve distortions on the inverter output. The authors of [21] studied the impact of base vectors on the neutral point (NP) voltage. The results of their research are presented in

Table 2. Impact of base vectors on NP voltage.

Base Vector	Zero	Large	Medium	Small
				p-Type	N-Type
Switching state	[PPP], [OOO], [NNN]	[PNN], [PPN], [NPN], [NPP], [NNP], [PNP]	[PON], [OPN], [NPO], [NOP], [ONP], [PNO]	[POO], [PPO], [OPO], [OPP], [OOP], [POP]	[ONN], [OON], [NON], [NOO], [NNO], [ONO]
NP current	$i_{NP}=0$	$i_{NP}=0$	$i_{NP}\ne 0$	$i_{NP}>0$	$i_{NP}<0$
NP voltage	unchanged	unchanged	increased/decreased	increased	decreased

. It was established that in the motoring mode, large and zero base vectors do not affect the NP voltage. At the same time, in small base vectors, p-type combinations increase the NP voltage while n-type combinations result in its reduction. Average base vectors may increase or decrease the NP voltage depending on their direction and the duration of impact.

To synthesize the vector ${\overline{U}}_s$, whose end is in segment 1 of sector II (see Figure 1, b), we can use various versions of base vectors ${\overline{U}}_{\mathrm{S}2}$, ${\overline{U}}_{\mathrm{S}3}$, and ${\overline{U}}_0$:

$$\left\{\begin{array}{l}{\overline{U}}_S={\gamma }_1{\overline{U}}_{\mathrm{S}2}\left\{\begin{array}{c}[\mathrm{OON}]\\ [\mathrm{PPO}]\end{array}\right\}+{\gamma }_2{\overline{U}}_{\mathrm{S}3}\left\{\begin{array}{c}[\mathrm{NON}]\\ [\mathrm{OPO}]\end{array}\right\}+{\gamma }_3{\overline{U}}_0\left\{\begin{array}{c}[\mathrm{PPP}]\\ [\mathrm{OOO}]\\ [\mathrm{NNN}]\end{array}\right\};\\ {\gamma }_1+{\gamma }_2+{\gamma }_3=1.\end{array}\right.$$

(4)

From the system of Equation (4), we can obtain multiple switching sequence options due to the excessive combination of small and zero base vectors. High-power EDs require low switching frequency due to significant switching losses, which, in turn, leads to significant voltage and current curve deviations from the perfect sine form. Among the classic SS, the base SS is the most suitable one because it ensures the best voltage and current quality on the inverter output [22]. This SS uses all the excessive small and zero base vector state combinations (see Figure 2), which results in increased switching loss. The simultaneous presence of p-type and n-type combinations in the base SS helps maintain the NP voltage balance through the even distribution of their activation duration over the PWM period.

In each of the PWM periods, segment 1 requires 12 power key switching pairs, segment 3 requires 8 pairs, and segments 2 and 4 require 6 pairs. According to Figure 2, switching losses are at their highest when the modulation index m_s changes within the range of 0–0.5, because, in this case, the end of the spatial vector ${\overline{U}}_s$ is only located in segment 1. When modulation factor values are between 0.5 and $1/\sqrt{3}$, the end of the vector ${\overline{U}}_s$ passes through segments 1 and 3, which results in a reduced switching loss. When the modulation factor increases further from $1/\sqrt{3}$ to 1 and segment 1 is absent, the operating regions of segments 2 and 4 are expanded, and that of segment 3 is shrunk, which also results in the reduction in the switching loss.

Despite the high quality of voltage and current on the VSI output, the base SS causes the most switching losses in SVPWM. Therefore, minimizing the amount of switching while preserving acceptable electricity quality is a relevant research problem.

3. Improved SVPWM Algorithm with the Seven-Stage Switching Sequence for the 3L NPC VSI

This section suggests an improved SVPWM algorithm with a seven-stage SS. The key feature of a seven-stage SS is its capability to control NP voltage through the adjustment of activation duration for various types of small base vector state combinations using a specific methodology.

Figure 3 shows a seven-stage SS that performs 6 base vectors per one PWM period. Unlike the base SS, the seven-stage SS excludes combinations [PPP] and [NNN] for the zero base vector in segment 1. The NP voltage in segments 2 and 4 is controlled using only one small base vector with a total activation duration for p-type and n-type state combinations distributed evenly over one quantization period $T_{\mathrm{PWM}}$. Segments 1 and 3 simultaneously use two small base vectors, where the even distribution over the period $T_{\mathrm{PWM}}$ is only provided for one vector with a longer activation duration. This vector is referred to as the dominant small base vector. For instance, if the spatial voltage vector ${\overline{U}}_s$ is in sector II and segments 1a or 3a (Figure 1, b), then the vector ${\overline{U}}_{\mathrm{S}1}$ can be selected as the dominant small base vector. In segments 1b or 3b, it is the vector ${\overline{U}}_{\mathrm{S}2}$. This SS requires 6 power key switching pairs for each PWM period and 2 additional pairs while transitioning to regions a and b.

Thus, a seven-stage SS can control NP voltage through the distribution of activation durations of p-type and n-type state combinations of the small base vector (for segments 2 and 4) or the dominant small base vector (for segments 1 and 3) during the PWM period. This vector is referred to as the distributed base vector, and its relative duration for p-type and n-type states can be determined using the following expression [17]:

$$\left\{\begin{array}{l}{\gamma }_{jp}={\displaystyle \frac{{\gamma }_j}{2}}\cdot \left(1+\Delta \gamma \right);\\ {\gamma }_{jn}={\displaystyle \frac{{\gamma }_j}{2}}\cdot \left(1-\Delta \gamma \right),\end{array}\right.$$

(5)

where Δγ is the control range of relative durations for p-type and n-type state combinations of the distributed vector over one PWM period that can change over the range $-1\le \Delta \gamma \le 1$; j = 1…3 is the relative duration index of the distributed vector.

Over a PWM period, the average value of the NP current ${\overline{i}}_{NP}$ generated by base vectors in the seven-stage SS can be determined with the following expression:

$${\overline{i}}_{NP}={\displaystyle \sum {\gamma }_k{i}_{NP.k}},$$

(6)

where k is the relative duration index for state combinations of base vectors in the selected seven-stage SS; i_NP.k is the NP current generated by the combination of base vector states with index k.

For the mathematical description of the inverter, the three states of the x-phase of the inverter [N], [O], [P] can be recorded using logical signals $s_x=\left[-1; 0; 1\right]$. In this case, the output phase voltage $u_x$ can be expressed as a function of power key states and the condenser $u_{d1}$ and $u_{d2}$ voltages [18]:

$$\left\{\begin{array}{l}{u}_x=u_{Cd2}\cdot \left(F_{d2x}-{\displaystyle \frac{1}{3}}{\displaystyle \sum _{m=a}^{b,c}{F}_{d2m}}\right)-u_{Cd1}\cdot \left(F_{d1x}-{\displaystyle \frac{1}{3}}{\displaystyle \sum _{m=a}^{b,c}{F}_{d1m}}\right);\\ u_{Cd1}+u_{Cd2}=U_{dc}.\end{array}\right.$$

(7)

Here, $F_{d2x}$ and $F_{d1x}$ are the functions of the x-phase state determining the state of connection between the DC link and each phase calculated using the following expressions:

$$\left\{\begin{array}{l}{F}_{d2x}=s_x\left(s_x+1\right)/2;\\ F_{d1x}=s_x\left(s_x-1\right)/2.\end{array}\right.$$

(8)

The NP voltage deviation inevitably results in neutral point current i_NP determined depending on the state functions and inverter output phase currents:

$$i_{NP}={\displaystyle \sum _x^{a,b,c}\left(F_{d2x}+F_{d1x}\right)\cdot i_x}={\displaystyle \sum _x^{a,b,c}{s}_x^2\cdot i_x},$$

(9)

where i_x is the phase load current (x—phase a, b, and c).

We can insert the logical states of base vectors in the expression above to achieve the neutral point current definition. For instance, see vector ${\overline{U}}_{S2n}$[OON]:

$$i_{\mathrm{NP}}={\displaystyle \sum _x^{a,b,c}{s}_x^2\cdot i_x}=s_a^2\cdot i_a+s_b^2\cdot i_b+s_c^2\cdot i_c=0^2\cdot i_a+0^2\cdot i_b+{\left(-1\right)}^2\cdot i_c=i_c.$$

(10)

Using the Laplace transform, we obtain the deviation of the NP voltage as follows, according to the current direction,

$$\left\{\begin{array}{l}{i}_{Cd1}-i_{Cd2}=i_{NP};\\ u_{Cd1}+u_{Cd1}=u_{dc};\\ u_{Cd1}={\displaystyle \frac{1}{C_{d1}}}{\displaystyle \int i_{Cd1}dt;}\\ u_{Cd2}={\displaystyle \frac{1}{C_{d2}}}{\displaystyle \int i_{Cd2}dt.}\end{array}\right.$$

(11)

Using the Laplace transform, we obtain the following:

$$\left\{\begin{array}{l}{\dot{I}}_{Cd1}-{\dot{I}}_{Cd2}={\dot{I}}_{NP};\\ {\dot{U}}_{Cd1}+{\dot{U}}_{Cd1}={\dot{U}}_{dc};\\ {\dot{U}}_{Cd1}={\displaystyle \frac{{\dot{I}}_{Cd1}}{s{C}_{d1}}};\\ {\dot{U}}_{Cd2}={\displaystyle \frac{{\dot{I}}_{Cd2}}{s{C}_{d2}}}.\end{array}\right.$$

(12)

Solving this system of equations, we obtain the following:

$$\left\{\begin{array}{l}{\dot{U}}_{Cd1}={\displaystyle \frac{C_{d2}}{C_{d1}+C_{d2}}}\cdot {\dot{U}}_{dc}+{\displaystyle \frac{1}{C_{d1}+C_{d2}}}\cdot {\displaystyle \frac{{\dot{I}}_{NP}}{s}};\\ {\dot{U}}_{Cd2}={\displaystyle \frac{C_{d1}}{C_{d1}+C_{d2}}}\cdot {\dot{U}}_{dc}-{\displaystyle \frac{1}{C_{d1}+C_{d2}}}\cdot {\displaystyle \frac{{\dot{I}}_{NP}}{s}}.\end{array}\right.$$

(13)

Thus,

$$\Delta {\dot{U}}_{NP}={\dot{U}}_{Cd1}-{\dot{U}}_{Cd2}={\displaystyle \frac{C_{d2}-C_{d1}}{C_{d1}+C_{d2}}}\cdot {\dot{U}}_{dc}+{\displaystyle \frac{2}{C_{d1}+C_{d2}}}\cdot {\displaystyle \frac{{\dot{I}}_{NP}}{s}}.$$

(14)

Based on the reverse Laplace transform, we obtain the following:

$$\Delta u_{NP}=u_{Cd1}-u_{Cd2}={\displaystyle \frac{C_{d2}-C_{d1}}{C_{d2}+C_{d1}}}\cdot U_{dc}+{\displaystyle \frac{2}{C_{d2}+C_{d1}}}{\displaystyle \int i_{NP}dt}.$$

(15)

Expression (15) shows that, apart from factors associated with the hardware side (U_dc, C_d1, C_d2), NP voltage deviation is also affected by the NP current generated by base vectors (through the value of s_x) and the load (phase current i_x) following Expression (9). As mentioned before, the NP voltage imbalance causes voltage and current curve distortion on the inverter output. Therefore, minimizing the NP voltage deviations helps improve the quality of electric power conversion. This can be achieved by adjusting the average value of the NP current to zero using the Δγ value (see Formulas (6) and (5)).

The results for the equation ${\overline{i}}_{NP}=0$ are provided in

Table 3. Values of Δγ for segments and sectors.

Position ${\overline{\mathit{U}}}_{\mathit{S}}$	Segment 1a	Segment 1b	Segment 2	Segment 3a	Segment 3b	Segment 4
Sector I	$-{\displaystyle \frac{{\gamma }_2{i}_c}{{\gamma }_1{i}_a}}$	${\displaystyle \frac{{\gamma }_1{i}_a}{{\gamma }_2{i}_c}}$	${\displaystyle \frac{{\gamma }_2{i}_b}{{\gamma }_3{i}_a}}$	${\displaystyle \frac{{\gamma }_3{i}_b-{\gamma }_2{i}_c}{{\gamma }_1{i}_a}}$	$-{\displaystyle \frac{{\gamma }_3{i}_b-{\gamma }_1{i}_a}{{\gamma }_2{i}_c}}$	$-{\displaystyle \frac{{\gamma }_1{i}_b}{{\gamma }_3{i}_c}}$
Sector II	${\displaystyle \frac{{\gamma }_2{i}_b}{{\gamma }_1{i}_c}}$	$-{\displaystyle \frac{{\gamma }_1{i}_c}{{\gamma }_2{i}_b}}$	$-{\displaystyle \frac{{\gamma }_2{i}_a}{{\gamma }_3{i}_c}}$	$-{\displaystyle \frac{{\gamma }_3{i}_a-{\gamma }_2{i}_b}{{\gamma }_1{i}_c}}$	${\displaystyle \frac{{\gamma }_3{i}_a-{\gamma }_1{i}_c}{{\gamma }_2{i}_b}}$	${\displaystyle \frac{{\gamma }_1{i}_a}{{\gamma }_3{i}_b}}$
Sector III	$-{\displaystyle \frac{{\gamma }_2{i}_a}{{\gamma }_1{i}_b}}$	${\displaystyle \frac{{\gamma }_1{i}_b}{{\gamma }_2{i}_a}}$	${\displaystyle \frac{{\gamma }_2{i}_c}{{\gamma }_3{i}_b}}$	${\displaystyle \frac{{\gamma }_3{i}_c-{\gamma }_2{i}_a}{{\gamma }_1{i}_b}}$	$-{\displaystyle \frac{{\gamma }_3{i}_c-{\gamma }_1{i}_b}{{\gamma }_2{i}_a}}$	$-{\displaystyle \frac{{\gamma }_1{i}_c}{{\gamma }_3{i}_a}}$
Sector IV	${\displaystyle \frac{{\gamma }_2{i}_c}{{\gamma }_1{i}_a}}$	$-{\displaystyle \frac{{\gamma }_1{i}_a}{{\gamma }_2{i}_c}}$	$-{\displaystyle \frac{{\gamma }_2{i}_b}{{\gamma }_3{i}_a}}$	$-{\displaystyle \frac{{\gamma }_3{i}_b-{\gamma }_2{i}_c}{{\gamma }_1{i}_a}}$	${\displaystyle \frac{{\gamma }_3{i}_b-{\gamma }_1{i}_a}{{\gamma }_2{i}_c}}$	${\displaystyle \frac{{\gamma }_1{i}_b}{{\gamma }_3{i}_c}}$
Sector V	$-{\displaystyle \frac{{\gamma }_2{i}_b}{{\gamma }_1{i}_c}}$	${\displaystyle \frac{{\gamma }_1{i}_c}{{\gamma }_2{i}_b}}$	${\displaystyle \frac{{\gamma }_2{i}_a}{{\gamma }_3{i}_c}}$	${\displaystyle \frac{{\gamma }_3{i}_a-{\gamma }_2{i}_b}{{\gamma }_1{i}_c}}$	$-{\displaystyle \frac{{\gamma }_3{i}_a-{\gamma }_1{i}_c}{{\gamma }_2{i}_b}}$	$-{\displaystyle \frac{{\gamma }_1{i}_a}{{\gamma }_3{i}_b}}$
Sector VI	${\displaystyle \frac{{\gamma }_2{i}_a}{{\gamma }_1{i}_b}}$	$-{\displaystyle \frac{{\gamma }_1{i}_b}{{\gamma }_2{i}_a}}$	$-{\displaystyle \frac{{\gamma }_2{i}_c}{{\gamma }_3{i}_b}}$	$-{\displaystyle \frac{{\gamma }_3{i}_c-{\gamma }_2{i}_a}{{\gamma }_1{i}_b}}$	${\displaystyle \frac{{\gamma }_3{i}_c-{\gamma }_1{i}_b}{{\gamma }_2{i}_a}}$	${\displaystyle \frac{{\gamma }_1{i}_c}{{\gamma }_3{i}_a}}$

, and they help determine the Δγ values that are integrated with the VSI control system.

The block diagram of the improved SVPWM algorithm with the seven-stage SS for the 3L NPC VSI is shown in Figure 4. The control system adjusts the inverter voltage and frequency through the set parameters U_s and f_s. The system includes several key functional blocks: rotation angle generator (RAG), sawtooth voltage generator (SVG), synchronizing pulse generator (SPG), SVPWM computer, and SVPWM modulator.

The RAG block is an integrator calculating the rotation angle θ for the spatial vector of voltage ${\overline{U}}_s$.

The SVG generates symmetrical sawtooth voltage u_saw with the PWM frequency f_PWM.

The SPG generates synchronizing pulses f_sync when the signal u_saw crosses the zero level.

The SVPWM modulator generates 12 logical control signals for inverter power keys and is composed of the following blocks: Δγ computer, switching level (SL) computer, comparison block, and memory block.

The Δγ computer calculates the value of Δγ following Table 3 using phase load currents i_a, i_b, and i_c to minimize the NP voltage deviation.

The SL computer calculates three SLs depending on the position of the end of the spatial voltage vector ${\overline{U}}_s$.

The comparison block compares the sawtooth voltage u_saw and the SL to determine the torques when base vectors are activated in each PWM period. The output data are coded with a two-bit code N_bit containing the information on the address of the memory cell that stores the information about the activation of a specific base vector.

The memory block stores the information on the power key activation state codes depending on the sector number N_sec and the segment number N_seg, as well as the binary code N_bit.

4. Experimental Research of the Improved SVPWM Algorithm with a Seven-Stage Switching Sequence

To test the efficiency of the improved SVPWM algorithm with a seven-stage SS (see Figure 4), we used a three-level power converter laboratory setup from Imperix Ltd (1950 Sion, Switzerland). This setup includes (Figure 5) a personal computer (1), filters (5) for 380 V three-phase AC grid connection (2), three integral semiconductor racks with NPC based on IGBT modules Vincotech P924F33, (4), a BoomBox control platform (3), and a 4 kW asynchronous motor (AM) (6).

We used specialized program blocks from the Imperix Blockset library in Matlab/Simulink 2017b to program three SVPWM algorithms featuring base SS (see Section 2), classic seven-stage SS (see Figure 4 with Δγ = 0), and an improved algorithm with a seven-stage SS (see Figure 4, Δγ ≠ 0). In all algorithms, voltage and frequency were controlled following U/f = const with a voltage boost in the low-frequency area of 5% of the nominal AM stator voltage.

After that, the program codes of algorithms were compiled in C/C++ and integrated with the BoomBox platform via a JTAG emulator. We used a USB connector to connect to the BoomBox Control and software platform to obtain a graphic representation and manage the data loaded from Matlab/Simulink 2017b to the TMS320C28346 central signal processor of the BoomBox control platform during the first stage. BoomBox RCP is a Rapid Control Prototyping (RCP) platform based on the TMS320C28346 digital signal processor (DSP) and the Xilinx XC9536XL-10VQG44C field programmable logic device (FPLD). It ensures the flexibility of programming and supports the implementation of even the most complex control algorithms. The BoomBox platform also supports real-time monitoring and debugging. Phase currents and voltages were measured and displayed at a sampling rate of 50 usec. The obtained data were imported into Matlab/Simulink 2017b for further analysis. The key laboratory setup parameters are presented in

Table 4. Key parameters of the three-level power converter laboratory setup.

Technical Parameters		Value
VSI	DC-link voltage, Udc	540 V
	DC-link capacitor capacity, Cd1 = Cd2	517 uF
	P924F33 Vincotech IGBT modules	600 V, 30 A, 50 kHz
	LEM HLSR 20-P/SP33 current probes	±20 A; bandwidth 450 kHz; measurement error ± 0.5%
	Avago ACPL-C87B voltage probes	bandwidth 25 kHz; measurement error ± 0.1%
	FPGA	Xilinx XC9536XL-10VQG44C
	TMS320C28346	300 MHz, 256 MB NOR flash memory, 2 MB RAM, and 300 MIPS
	SVPWM, fPWM	2000 Hz
	Control method	U/f = const
AM	Rate power, Pr	4 kW
	Linear voltage, Ul.	380 V
	Rate stator current, Is	8.6 A
	Rate frequency, fs.r	50 Hz

.

Figure 6 shows the instant voltage values on the two capacities in the DC link at a normalized set frequency of f^*_s = 0.8 and nominal motor load for SVPWM algorithms with a base and classic seven-stage SS (Δγ = 0) and the improved SVPWM algorithm with a seven-stage SS [23,24]. Here, the normalized set frequency is calculated using the following formula:

$$f_s^{*}={\displaystyle \frac{f_s}{f_{s.r}}}.$$

(16)

where f_s.r = 50 Hz is the rated AM stator frequency.

When the DC link voltage is 540 V and the NP voltage balance is perfect, the voltage on each capacitor is 270 V (red curve; see Figure 6). However, as mentioned before, the NP voltage inevitably becomes unbalanced during the operation of the 3L NPC VSI. Unlike the SVPWM algorithms with the base SS and the classic seven-stage SS, the improved SVPWM algorithm can reduce the maximum NP voltage deviation by 40% and 52.6%, respectively. This helps improve the shape of the inverter output current (Figure 7). Unlike the established SVPWM algorithms, odd harmonic components of the orders 43–57 in the suggested algorithm increase insignificantly in the phase output current spectrum. Simultaneously, lower-frequency 5th-order harmonics are reduced from 1.5% and 1.8% to 0.65%, while the 7th-order harmonics are reduced from 1.8% and 1.95% to 0.75%. As a result, the THD current distortion factor is reduced from 2.83% and 3.25% to 2.66%.

The complex efficiency assessment of the improved SVPWM algorithm with a seven-stage SS used the following parameters:

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The number of power key switching pairs per one period of the fundamental harmonic on the output of the inverter N_sw;

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The maximum relative NP voltage deviation,

$$\delta u_{NP.m}={\displaystyle \frac{\Delta u_{NP.m}}{U_{dc}}}\cdot 100\%={\displaystyle \frac{{\left|u_{Cd1}-u_{Cd2}\right|}_{\max }}{U_{dc}}}\cdot 100\%,$$

(17)

where u_Cd1 and u_Cd2 are voltages on capacitors C_d1 and C_d2 in the VSI DC link and U_dc is the constant inverter power voltage;

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The total harmonic distortion factor (THD) of the inverter output current,

$$K_i={\displaystyle \frac{\sqrt{{\displaystyle \sum _{n=2}^{\infty }{I}_{m\left(n\right)}^2}}}{I_{m(1)}}}\cdot 100\%,$$

(18)

where I_m(1), I_m(n) is the amplitude of the first (fundamental) harmonic and harmonic n;

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The distortion factors of 5th and 7th harmonics (K_i(5) and K_i(7)) in the inverter output current spectrum

$$K_{i(5)}={\displaystyle \frac{I_{m\left(5\right)}}{I_{m(1)}}}\cdot 100\%;\hspace{0.17em}\hspace{0.17em}{K}_{i(7)}={\displaystyle \frac{I_{m\left(7\right)}}{I_{m(1)}}}\cdot 100\%$$

(19)

Figure 8 and Figure 9 show the experimental dependencies between the number of power key switching pairs N_sw per one period of the fundamental harmonic on the inverter output, the relative NP voltage error δu_NP.m, and harmonic current distortion factors K_i, K_i(5), and K_i(7), depending on the normalized set frequency f^*_s, and their average values ${\overline{N}}_{sw}$, ${\overline{\delta u}}_{NP.m}$, ${\overline{K}}_i$, ${\overline{K}}_{i(5)}$, and ${\overline{K}}_{i(7)}$ over the entire range of frequency f^*_s (0 to 1.0) for the three SVPWM algorithms: with the base SS, the classic seven-stage SS, and the improved SVPWM algorithm with a seven-stage SS.

The analysis of dependencies shown in Figure 8 and their average values (Figure 9) allows us to draw the following conclusions:

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The improved SVPWM algorithm with a seven-stage SS has the least number of power key switching pairs N_sw over the entire range of frequency f^*_s compared to the established algorithms (see Figure 9, a). For instance, compared to the SVPWM algorithm with the base SS, the suggested algorithm significantly reduces the number of power key switchings by about 51.5%, especially in the range of frequency f^*_s from 0 to 0.5. This can be attributed to the significant excess of base vector switching in each PWM period in the base SS (see Figure 2, segment 1). The average switching value ${\overline{N}}_{sw}$ over the range of frequency f^*_s, in this case, is reduced from 414 to 234 pairs, which corresponds to a 43.48% reduction (see Figure 9). Compared to the algorithm with the classic seven-stage SS, the improved SVPWM algorithm may also reduce the average number of switchings ${\overline{N}}_{sw}$ from 252 to 234 pairs (see Figure 9), which is equivalent to a 7.14% reduction. This can be attributed to the increase in factor Δγ to the maximum value of ±1.0, which results in the reduction in switching levels in each PWM period.

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The SVPWM algorithm with the base SS minimizes the impact of small base vectors on the NP voltage due to the even distribution of activation durations of p-type and n-type small base vectors but it does not account for the impact of medium vectors used in segments 2, 3, and 4 (see Figure 2). Because of this, factor δu_NP.m is at the minimum at frequency f^*_s between 0 and 0.5, but it increases dramatically when f^*_s is in the range of 0.5 and 1, reaching the maximum of 5.8% at f^*_s = 1 (see Figure 9, b).

5. Analysis and Discussion

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The SVPWM algorithm with the classic seven-stage SS (Δγ = 0), used as the basis for the development of the improved algorithm, does not support NP voltage control. This results in a high level of deviation δu_NP.m, reaching a maximum value of δu_NP.m = 9.2% at f^*_s = 0.5 (see Figure 8, b), when the activation duration of small base vectors in each PWM period reaches the highest value.

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The improved SVPWM algorithm with a seven-stage SS provides the best NP voltage control among the considered algorithms by controlling the duty factor Δγ of distributed base vectors in each PWM period based on phase load currents. Thus, the average value of error ${\overline{\delta u}}_{NP}$ over the entire range of frequency f^*_s for the improved SVPWM algorithm is 2.74% (see Figure 9), which is 64.4% lower than for the SVPWM with the classic seven-stage SS (δu_NP = 7.69%) and 4.2% lower than for the SVPWM with the base SS (δu_NP = 2.86%).

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In the frequency range f^*_s of 0 to 0.5, the value of deviation δu_NP.m for the improved SVPWM algorithm is slightly higher than for the established SVPWM algorithm with the base SS (see Figure 8, b), because, in this range, NP voltage in the suggested algorithm is only controlled with a single dominant small base vector while the second small base vector remains uncontrolled. When f^*_s > 0.5, deviation δu_NP.m in the improved SVPWM algorithm becomes smaller than in the established SVPWM algorithm with the base SS, which can be explained by the heavy influence of medium base vectors in the established algorithm.

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When f^*_s > 0.8, errors δu_NP.m in the improved SVPWM algorithm increase significantly and reach 5.1% at f^*_s = 1 (see Figure 8, b), like in the established SVPWM algorithm with the base SS. This can be explained by the fact that this region has significantly shorter small base vector activation durations, which restricts the NP voltage balance control in the suggested algorithm. To reduce this error, we suggest increasing either the capacity of condensers C_d1 and C_d2 of the inverter DC link or the frequency of PWM. The first option is preferred as it only leads to an increase in the inverter’s price, weight, and dimensions, while in the other case, the efficiency of the converter drops due to the increased switching loss.

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The total current distortion factor K_i for all of the considered algorithms (see Figure 8, c) directly depends on the NP voltage error δu_NP.m and is similar to the dependencies shown in Figure 8, b. This can be attributed to the fact that the NP voltage imbalance leads to voltage asymmetry in capacitors C_d1 and C_d2 of the DC link and, as a result, causes voltage and current curve distortions on the inverter output.

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In terms of the average total current distortion factor ${\overline{K}}_i$, the suggested SVPWM algorithm only loses 0.1% of the absolute value across the entire frequency range f^*_s compared to the established SVPWM algorithm with the base SS (see Figure 9), but its average values of low-frequency current harmonic factors ${\overline{K}}_{i(5)}$ and ${\overline{K}}_{i(7)}$ are 19% and 15.7% better, respectively. Note that the odd low-frequency harmonics (5, 7, …) have the greatest negative impact and may lead to increased magnetic core losses and reduced motor efficiency, increased losses in windings causing motor overheating and service life reduction, and disruptions in the evenness of the rotating magnetic field of the motor, which leads to increased vibration and noise levels.

6. Conclusions

This article demonstrates an improved SVPWM algorithm with a seven-stage switching sequence for 3L NPC VSIs. The proposed algorithm calculates relative durations for p-type and n-type state combinations using the load phase currents. The suggested SVPWM provides the lowest loss, as well as the best NP voltage balance among the established algorithms, while preserving the quality of the inverter output current comparable to the established SVPWM algorithm with the base SS. The obtained results confirm the efficiency of the suggested algorithm and its great potential for power converters in industry.