Review on Short-Circuit Protection Methods for SiC MOSFETs

Abstract

SiC MOSFETs have been a game-changer in the domain of power electronics, thanks to their exceptional electrical traits. They are endowed with a high breakdown voltage, reduced on-resistance, and superior thermal conductivity, which make them supremely suitable for high-power and resilient applications across aviation, automotive, and renewable energy sectors. Despite their intrinsic advantages, SiC MOSFETs also necessitate advanced safeguarding mechanisms to counteract the vulnerability to short-circuit conditions due to their lower short-circuit robustness. This review paper offers an in-depth analysis of the array of short-circuit protection (SCP) methods applied to SiC MOSFETs. This paper scrutinizes techniques such as desaturation detection, di/dt detection, gate charge characteristics monitoring, two-dimensional monitoring, Rogowski coil-based detection, and two-stage turn-off strategies. The paper meticulously explores the operational principles, merits, and limitations of each method, with an emphasis on their adaptability to various fault types, including hard switching faults and load-induced faults. This review acts as a thorough compendium, guiding the choice of pertinent SCP strategies, ensuring the secure and efficient functioning of SiC MOSFETs in demanding applications.

1. Introduction

The rapid advancement in power electronics has led to the widespread adoption of silicon carbide (SiC) MOSFETs, especially in applications demanding high efficiency, high switching frequency, and superior thermal performance [1,2]. SiC metal–oxide–semiconductor field-effect transistors (MOSFETs), owing to their inherent material advantages over traditional silicon (Si) counterparts, have emerged as a pivotal component in modern power electronic systems; also, the integration of SiC MOSFETs with advanced transformer models, such as those operating in the ISM band, can potentially lead to more efficient and reliable power conversion systems [3]. These devices exhibit lower on-resistance, higher breakdown voltage, and significantly better thermal conductivity, making them ideal for high-voltage, high-temperature, and high-frequency applications [4,5,6,7,8].

One of the critical challenges associated with the deployment of SiC MOSFETs is ensuring reliable operation under fault conditions [9], particularly short-circuit (SC) events [10,11,12,13,14]. To lessen the negative impact of the subpar SiC/SiO₂ interface on the device’s on-state resistance (R_ds,on), SiC MOSFETs have a shorter channel length and a thinner gate oxide layer [15,16]. Thus, SiC MOSFETs’ maximum short-circuit current (I_SC) can exceed their rated current by up to 10 times [17,18,19]. Furthermore, SiC MOSFETs have a lower heat capacity and a higher short-circuit current density due to their smaller chip size when compared to Si insulated-gate bipolar transistor (IGBT) with identical voltage and current ratings [18]. As such, SiC MOSFETs have a poorer short-circuit tolerance capability than Si IGBTs, which causes SiC MOSFETs to break within a few microseconds as a result of gate failure or thermal runaway in a short-circuit event [11,20,21,22]. Therefore, short circuit protection (SCP) is essential to prevent catastrophic failures and enhance the longevity and reliability of power systems incorporating SiC MOSFETs [23,24]. Traditional protection methods used for Si-based devices often fail when applied to SiC devices due to the distinct electrical and thermal characteristics of SiC [25,26]. As a result, SiC MOSFETs demand much faster reaction times due to their higher switching speeds and lower energy loss during switching events, making traditional, slower protection methods inadequate [9,27]. Additionally, SiC devices operate over a wider temperature range, typically from 200 K to 450 K, requiring more robust thermal management and protection strategies that traditional methods fail to provide [28]. Furthermore, in aerospace power systems, the complexity and reliability of the protection topology are crucial due to stringent requirements regarding electromagnetic interference (EMI) and power isolation [27]. Traditional methods often cannot meet these high-frequency operation conditions and stringent EMI standards without compromising reliability [25,26]. Therefore, specialized protection methods tailored to the unique characteristics of SiC devices are necessary to ensure their safe and efficient operation in advanced applications [29].

SCP for SiC MOSFETs is typically divided into two sections: SC detection and soft turn-off (STO), as shown in Figure 1. The detection phase involves identifying the occurrence of a short circuit as fast as possible, which is crucial for minimizing damage to the device and ensuring system reliability. Several SC detection methods have been proposed and implemented in recent years, as shown in Figure 1, each with its unique advantages and limitations. V_GS is the voltage between the gate and the source of the MOSFET, Q_G is the charge entering the gate, V_DS is a drain-to-source voltage, and I_DS is a drain-to-source current. These methods include desaturation detection [30], di/dt detection [31], gate charge (Q_G) monitoring [32], two-dimensional monitoring [33], power loss estimation [34], and the use of Rogowski coils [35], among others. Each method offers a different approach to detecting and mitigating short circuits, with varying degrees of effectiveness, complexity, and suitability for various applications. Once a short circuit is detected, the STO phase is initiated. Unlike abrupt turn-off methods, the STO process gradually reduces the gate voltage, allowing the MOSFET to transition smoothly from its conducting state to the non-conducting state [36]. This controlled reduction in current flow helps to minimize voltage overshoot and electromagnetic interference, reducing stress on the device and improving overall system stability. By combining effective detection mechanisms with an STO strategy, the short-circuit protection system ensures a robust response to fault conditions, safeguarding the device and enhancing its operational lifespan.

This paper provides a comprehensive review of the existing SCP methods for SiC MOSFETs. We analyze their working principles, advantages, and limitations, offering insights into their applicability in various power electronic systems. By understanding the strengths and weaknesses of these protection strategies, we aim to guide future research and development toward more robust and efficient SCP solutions for SiC MOSFETs. This review not only serves as a reference for engineers and researchers but also highlights the need for continued innovation in SCP technologies to fully harness the potential of SiC MOSFETs in next-generation power electronics.

2. Analysis of Short-Circuit Types

The following section cover the two main types of short circuits; hard-switching faults (HSFs) and faults under loads (FULs). HSF typically occurs during the rapid transition of a MOSFET from the off-state to the on-state. This situation is characterized by high levels of current flow while the voltage remains elevated, causing significant power dissipation. Such conditions are often caused by inadequate timing control or synchronization during the switching sequence, leading to premature activation of the MOSFET. Conversely, An FUL arises when a short circuit develops in the circuit while the MOSFET is already conducting load current. This can occur due to unexpected short circuits in the load, sudden increases in load demand that exceed the device’s rated capacity, or failures in other components within the circuit, such as capacitors or inductors, which result in excessive currents. Figure 2a shows the schematic for test bench to simulate the HSF and FUL faults. Both fault conditions are discussed further in the following section.

2.1. HSF-Type Fault

An HSF occurs when a MOSFET is abruptly switched on into a short-circuit condition. From Figure 2a, when Q₁ (upper switch) is turned on, the current bypasses the load and flows through Q₁, where PWM₁ (pulse width modulation) and PWM₂ are gate signals for Q₁ and Q_DUT (device under test, i.e., the SiC MOSFET). By activating Q₁ before Q_DUT (device under test, i.e., the SiC MOSFET), an HSF is simulated, as a high short-circuit current will flow through the circuit when Q_DUT turns on. Figure 2b shows the behavior of the SiC MOSFET’s different parameters under an HSF, which can be useful in detecting fault conditions. This fault typically arises during the turn-on phase when the device is expected to conduct current but encounters a direct short circuit instead. An HSF is characterized by a high current spike upon turning on, leading to a very high peak current [37,38]. Simultaneously, V_DS drops rapidly to near zero as the MOSFET attempts to conduct the excessive current, resulting in a high rate of voltage change (dv/dt). This sudden transition subjects the device to significant thermal stress due to the instantaneous high-power dissipation. The protection challenge posed by HSFs necessitates extremely fast detection and response mechanisms to prevent device damage. Consequently, additional circuitry is typically required to quickly shut down the device upon fault detection, thereby protecting it from thermal and electrical overstress.

2.2. FUL-Type Fault

An FUL occurs when a MOSFET is already conducting current under normal operating conditions and then encounters a short-circuit fault. As shown in Figure 2a, the current path initially includes the load while Q₁ is off (and Q_DUT is on), indicating that the circuit is operating under normal load conditions. However, once Q₁ is turned on, the current bypasses the load and flows through Q₁ instead, simulating an FUL condition. The behavior of the various SiC MOSFET parameters under an FUL is shown in Figure 2c, which can help identify fault conditions. This type of fault can result from external factors such as load malfunction or a sudden short in the load path [39,40]. An FUL is characterized by a moderate rise in current, which increases to a high level but not as instantaneously as in an HSF, given that the device is already in the on-state and conducting current. The MOSFET may sustain this high current for a longer period, leading to gradual thermal stress buildup if the fault is not cleared promptly. Effective protection against FUL requires robust fault detection and protection mechanisms capable of managing a prolonged high current without immediate destruction. The protection scheme must also distinguish between normal load conditions and fault conditions to avoid false triggering and unnecessary interruptions.

Both HSF and FUL necessitate efficient short-circuit protection mechanisms to ensure the reliability and longevity of SiC MOSFETs. While an HSF demands ultrafast detection and response due to its abrupt nature, an FUL requires sustained current handling and reliable detection over an extended period. Advanced sensing techniques combined with rapid response circuitry are crucial for safeguarding SiC MOSFETs against these faults, particularly in high-performance applications such as aviation and other demanding environments.

3. SC Withstand Time Limits with the Usage of SiC MOSFETs

The short-circuit withstand time (SCWT) of SiC MOSFETs and Si IGBTs significantly differs due to their distinct material properties and device structures. SiC MOSFETs generally have a shorter SCWT compared to Si IGBTs. This discrepancy arises from the higher current density and smaller heat capacity of SiC MOSFETs, which result in faster thermal runaway during a short-circuit event [41].

Temperature and DC bus voltage also affect the SCWT of SiC MOSFETs [42]. According to [43], the SCWT for CREE 1st Generation (1G) SiC MOSFETs (1.2 kV) at 25 °C and 600 V DC bus voltage is 12 µs, decreasing to 11 µs at 200 °C, as described in

Table 1. Comparison of SCWT for CREE 1G, CREE 2G, and ROHM SiC MOSFETs at various temperatures and DC bus voltages.

SiC MOSFETs (1.2 kV)	Temperature/DC Bus Voltage	SCWT
CREE 1G	25 °C/600 V	12 µs
	200 °C/600 V	11 µs
	200 °C/750 V	7 µs
CREE 2G	25 °C/600 V	8 µs
	200 °C/600 V	8 µs
	200 °C/750 V	5 µs
ROHM	25 °C/600 V	17 µs
	200 °C/600 V	13 µs
	200 °C/750 V	11 µs

. At 750 V and 200 °C, the SCWT further reduces to 7 µs. CREE 2nd Generation (2G) (1.2 kV) devices have an SCWT of 8 µs at 25 °C and 600 V, which decreases to 5 µs at 750 V and 200 °C. In contrast, 1.2 kV SiC MOSFETs from ROHMS exhibit a longer SCWT, i.e., 17 µs at 25 °C and 600 V, decreasing to 13 µs at 200 °C and 600 V, and further reducing to 11 µs at 200 °C and 750 V. These results indicate that the SCWT of SiC MOSFETs generally decreases with increasing temperature and DC bus voltage, underscoring the temperature-dependent nature of their short-circuit capability.

According to [44], the SCWT for the IKW25N120H3 IGBT (1.2 kV/25 A) is approximately 33 μs, with critical energy (Ecr) values of 2772 mWs for HSFs and 2928 mWs for FULs at 25 °C, as shown in Figure 3. In comparison, the SCWT and Ecr for the SiC MOSFET (C2M160120D) are around 10 µs and 400 mWs, respectively. Additionally, the SiC MOSFET (SCT2160KEC) has an SCWT of approximately 22 µs and an Ecr of 900 mWs, as shown in Figure 3. The data reveal that SiC MOSFETs have a much shorter SCWT and lower Ecr compared to IGBTs, meaning they can withstand a short circuit for a shorter duration and with less energy before failure occurs. This comparison is critical for understanding the trade-offs between SiC MOSFETs and IGBTs in high-power applications.

4. Challenges in Short-Circuit Protection of SiC MOSFETs

In order to have a deeper comprehension of the obstacles and requirements related to the short-circuit protection of SiC MOSFETs, the corresponding challenges are presented as follows.

4.1. Device Structure of SiC MOSFET

The device structure of SiC MOSFETs is carefully engineered to balance R_ds,on and short-circuit withstand capability. SiC MOSFETs often feature shorter channel lengths and thinner gate oxide layers to mitigate the negative impact of the poor quality SiC/SiO₂ interface on the device’s R_ds,on. This design choice, however, introduces a trade-off [45,46,47]. Figure 4 shows the trade-off between short-circuit withstand time and normalized R_ds,on for SiC MOSFET [48]. Thinner gate oxide layers make the gate more vulnerable to damage due to high electric fields and leakage currents during short-circuit events [11,45]. Additionally, shorter channels lead to a more pronounced drain-induced barrier-lowering (DIBL) effect compared to Si IGBTs, causing a drift in threshold voltage (V_th). As described in [49], V_th decreases with increased V_DS, and the saturation current (I_C) can be expressed as:

$$I_C=\left({\displaystyle \frac{Z·{\mu }_i·C_x\left(V_{\mathrm{GS}}-V_{\mathrm{th}}\right)}{2L_{ch}}}\right)$$

(1)

where $L_{ch}$ is the channel length, $C_x$ is the gate oxide capacitance, ${\mu }_i$ indicates the electron mobility in the inversion layer, and $Z$ indicates the channel width. Because of Equation (1), a drop in V_th results in a larger saturation current [50,51].

The channel resistance, which is a significant component of R_ds,on, contributes to the overall performance of SiC MOSFETs. To reduce R_ds,on, a thinner gate oxide layer and a shorter channel are designed, but these modifications can lower the short-circuit withstand capability. This structural vulnerability is further exacerbated by the DIBL effect, which affects the transconductance and causes the I_DS of SiC MOSFETs to vary widely with V_DS, as shown in Figure 5 [52]. This variation makes it challenging to detect short-circuit events based solely on the operating area.

Another critical aspect is the chip area, which is typically smaller in SiC MOSFETs compared to their Si counterparts, resulting in lower heat capacity [18]. During a short-circuit event, the relation between short-circuit energy (E_SC) and temperature variation (ΔT) is given by:

$$E_{\mathrm{SC}}=cm\mathsf{\Delta }\mathrm{T}$$

(2)

where c is the heat capacity, m is mass, and $\mathsf{\Delta }\mathrm{T}$ represents temperature variation. Due to the smaller heat capacity, the junction temperature (T_j) of SiC MOSFETs rises more rapidly than that of Si IGBTs for the same short-circuit energy. Figure 6 shows the TCAD simulation of the SiC MOSFET’s lattice temperature during short-circuit events showing that the maximum lattice temperature can exceed 1000 K and reach the melting temperature of the aluminum electrode within microseconds [53].

Under repetitive short-circuit conditions, the rapid rise in temperature within SiC MOSFETs can lead to severe consequences, particularly due to the thermal limits of the materials involved. As the junction temperature increases, especially near critical regions like the gate and drift regions, the heat can reach levels where aluminum, commonly used in the device’s metallization, begins to melt. Aluminum has a melting point of approximately 660 °C, and if the localized temperature approaches this threshold, the integrity of the metal contacts can be compromised, potentially leading to catastrophic device failure [18].

Moreover, the elevated temperatures pose a significant risk to the insulation between the gate and drift regions, which is typically provided by a gate oxide layer made of silicon dioxide (SiO₂) [54]. This oxide layer is crucial for maintaining the electric field insulation between the gate and the underlying semiconductor material. However, excessive temperatures can degrade the gate oxide, resulting in several detrimental effects. First, the insulating properties of the oxide may diminish, increasing the likelihood of gate leakage currents, which can cause the MOSFET to lose control and behave unpredictably. Second, if the thermal stress becomes too great, it can lead to electrical breakdown of the gate oxide, allowing current to flow directly between the gate and the drift region, effectively short-circuiting the device internally.

Furthermore, high temperatures can induce a shift in the threshold voltage (V_th) of the MOSFET, altering its switching behavior and reducing its efficiency. The combination of these factors, the melting of aluminum contacts, degradation of the gate oxide, and changes in electrical characteristics, significantly shortens the device’s lifespan and reliability.

4.2. Switching Speed of SiC MOSFETs

SiC MOSFETs are known for their fast-switching speed, which is one of the primary advantages over their Si counterparts. This high-speed switching capability stems from several intrinsic properties of SiC as a material, as well as the design characteristics of SiC MOSFETs.

SiC has a wide bandgap of 3.26 eV, compared to Si’s 1.12 eV [55]. This wide bandgap allows SiC devices to operate at higher temperatures and voltages with reduced leakage currents, facilitating faster switching transitions [56]. The higher critical electric field of SiC (approximately 10 times that of Si) enables the fabrication of devices with thinner drift regions and lower R_ds,on, contributing to the rapid switching performance.

Another significant factor is the low intrinsic carrier concentration in SiC, which reduces the charge storage in the device during switching [57]. This reduction minimizes the turn-off delay time and the total switching loss. The lower charge storage allows SiC MOSFETs to switch on and off more quickly, achieving higher frequencies with greater efficiency [58].

Furthermore, the fast-switching speed of SiC MOSFETs is advantageous in various applications, including power converters, motor drives, and high-frequency power supplies [59,60,61,62]. It allows for smaller passive components, reduced EMI, and higher efficiency in power conversion systems. The capability to operate at higher frequencies also leads to more compact and lightweight designs, which is particularly beneficial in applications like electric vehicles (EVs) and aerospace systems where size and weight are critical considerations.

Despite these benefits, the fast-switching speed of SiC MOSFETs poses some challenges. High dv/dt and di/dt associated with fast switching can induce significant EMI and noise in the system, which requires careful design and filtering to mitigate [63,64]. Additionally, the gate drive circuitry for SiC MOSFETs must be robust and capable of handling fast transients to ensure reliable operation.

5. Short-Circuit Detection Methods

SC detection for SiC MOSFETs is essential due to their unique electrical and thermal properties, which differ significantly from traditional Si-based devices. It usually consists of two parts, SC detection and STO.

SiC MOSFETs offer higher dv/dt and di/dt capabilities, faster-switching speeds, and higher operating temperatures, making conventional protection methods inadequate. To address these challenges, several innovative SC detection methods have been developed, each with specific advantages and limitations. These methods ensure the reliable operation of SiC MOSFETs, particularly in demanding applications like aerospace and automotive systems. The following sections explore these methods in detail, highlighting their working principles, benefits, and potential drawbacks. The current approaches for detecting short circuits can be classified into four groups based on the parameters being monitored V_DS-based detection, gate charge-based detection, I_DS-based detection, and combination detection method. These methods are listed in

Table 2. Short-circuit detection methods for SiC MOSFET.

Parameters	Methods	Detectable Faults	Ref.
VDS	VDS	HSF and FUL	[30,65,66,67]
	dVDS/dt	HSF	[68]
	$\int V_{\mathrm{DS}}\mathrm{d}t$	HSF and FUL	[69]
ID	Rogowski coil	HSF and FUL	[35,70,71,72,73,74,75,76,77,78]
	dIDS/dt	HSF and FUL	[30,79,80,81,82,83,84]
	TMR sensor	HSF and FUL	[73,85]
Gate	QG	HSF	[86,87,88,89]
	Gate leakage current	HSF and FUL	[32,86,90]
Combined	VGS and dIDS/dt	HSF and FUL	[33,91,92,93]
	VDS and ID	HSF and FUL	[34]

.

5.1. SC Detection Method Based on V_DS Monitoring

The desaturation method, as shown in Figure 7a, is a straightforward approach that monitors the V_DS to detect saturation, indicative of an SC [30,38,67,94,95,96,97,98,99,100,101,102]. When an SC occurs, V_DS quickly rises, triggering a shutdown. The desaturation detection circuit consists of a resistor, a blanking capacitor, and a diode, as shown in Figure 7a. When the device turns on, a current source charges the blanking capacitor and the diode starts conducting. During normal operation, the capacitor voltage is clamped at the forward voltage of the device. When an SC happens, the capacitor voltage is quickly charged to the threshold voltage, triggering the device shutdown. However, this method is very slow. As per [96], the desaturation method’s SC detection time for a third-generation 10 kV SiC MOSFET under HSFs and FULs is approximately 1.5 µs.

In [103], the blanking time for each switching period is adjusted by recording the V_DS fall time during each turn-on event and setting it as the blanking time for the next period, as shown in Figure 7b. This self-adjustive approach allows for a quick response to changes in the operating state without false triggering during normal switching transients. However, it introduces an adaptation delay ranging from several hundred nanoseconds to one microsecond. In [30], a Zener diode is added to block high-voltage pulses across blanking capacitor, and an extra diode is added across the resistor to fast discharge the capacitor during turn-off time, as shown in Figure 8a. Based on the short-circuit characteristic of SiC MOSFETs, where the short-circuit withstand time decreases as the DC bus voltage increases [104], the desaturation conduction voltage integral ($\int V_{\mathrm{DS}}\mathrm{d}t$)-based SC detection method was proposed in [69] and is shown in Figure 8b. This method’s response speed for SC detection improves with the increase in DC bus voltage. The dv/dt detection method for SiC MOSFETs operates by monitoring the rate of change in V_DS [68]. During a short-circuit event, the V_DS increases rapidly, generating a significant dv/dt signal. This rapid change is detected by a dedicated circuit, which typically includes a high-speed comparator and a threshold-setting component, as shown in Figure 9.

5.2. SC Detection Method Based on I_DS Monitoring

One of the direct I_S measurement methods is based on Rogowski coil for non-intrusive current sensing, providing a lightweight and non-intrusive design [35,70,71,72,73,74,75,76,77,78,90], as shown in Figure 10. The article in [35] introduces a PCB coil design based on a single interconnect trace for TO-247-4 L-packaged SiC MOSFETs. The interconnect, connecting the DC busbar to the SiC MOSFET terminal, generates flux linkages with a nearby PCB coil, achieving a mutual inductance of 0.175 nH per mm³. This mutual inductance is significantly higher than that of a laminated busbar PCB coil design and attests to the efficacy of this design in extracting a high sensitivity with a compact coil size. The compact coil not only minimizes intrusion within the power loop but also yields a high natural frequency of 469 MHz. This high frequency enables a broad bandwidth for the current sensor, essential for implementing an ultrafast protection scheme. Additionally, the coil design, intricately linked to the interconnect trace length, allows control over mutual inductance and power-loop stray inductance by adjusting the trace length. Three-dimensional finite-element method simulations in COMSOL guide the selection of the interconnect trace length, minimizing power-loop stray inductance. This design methodology was applied to demonstrate a half-bridge circuit with PCB coils for current sensing of TO-packaged devices, showcasing a novel protection circuit with an impressive response time improvement from 86 ns to 25 ns compared to the existing state of the art. However, it comes with integration complexity, has a specific bandwidth, and is costly to produce.

A second I_DS-based detection method is Tunnel Magnetoresistance (TMR)-based SC detection method. These sensors are highly sensitive, respond quickly, and resist electromagnetic interference, making them ideal for SiC MOSFET applications. The TMR sensor detects changes in the magnetic field caused by a high current flow during a short circuit and promptly signals the protection circuit to shut down the MOSFET, preventing damage. A TMR current sensor, depicted in Figure 11, consists of a Wheatstone bridge and a gain amplifier [73]. The TMR chip’s output voltage (ΔV) is directly proportional to the magnetic flux density (B), which, according to Ampere’s law, is proportional to the detected I_DS. Through linear amplification, the sensor’s output voltage (v_m) maintains a proportional relationship with the current I_S.

A few more direct I_DS-based detection methods include Hall effect sensor, shunt, current transformer, on-chip sensor, etc. [105,106]. These current sensors can accurately monitor I_D, effectively preventing I_SC from rising to critical levels. However, many of these sensors have limitations when it comes to short-circuit detection applications.

Hall effect sensors detect the induced voltage generated by the measured current’s magnetic field [107]. Hall effect sensors can measure current accurately, but they are expensive and susceptible to loop magnetic fields [108]. Although shunts are simple to install, they lead to increased switching loss and conduction loss [109]. Based on magnetoresistance effects, magneto-resistive current sensors are compact and exhibit a high sensitivity [106].

The indirect detection method is to detect the rate of change in current (di/dt) flowing through the parasitic inductance of the device [30,79,80,81,82,83,84], as shown in Figure 12a. This detected di/dt is then processed through a resistive–capacitive (RC) low-pass filter designed to restore the fast-changing current dynamics. The filtered di/dt is subsequently compared with a predefined threshold value, and if the calculated di/dt surpasses this threshold, indicative of a rapid change in current associated with an SC, the protective circuit is activated. However, under various fault scenarios, especially under FULs, it does not yield consistent outcomes [31], leading to detection failure as C_S discharges after I_DS becomes steady after turn-on and rises again at the FUL. However, the rise in I_D under an FUL is less than under an HSF; thus, it requires two different thresholds for HSFs and FULs. Therefore, in [31], a different di/dt-RCD (RC + diode) protective circuit has been suggested to provide more precise and reliable results regardless of the fault types, as shown in Figure 12b, by adding a diode in series with R_S and L_SS to prevent C_S from discharging when the current is constant. While RC and RCD perform similarly for HSFs, i.e., the SCP time is around 100 ns, the RCD method demonstrates a faster detection time for FULs, achieving 72 ns compared to the RC method’s 100 ns.

5.3. SC Detection Method Based on Gate Charge Monitoring

The gate charge-based SC detection method is a sophisticated approach used to identify and protect against short-circuit conditions in power semiconductor devices, such as SiC MOSFETs [32,86,87,88,89]. This method focuses on monitoring the gate charge dynamics to distinguish between normal operation and short-circuit events. In SiC MOSFETs, the total gate charge (Q_G) during the turn-on process consists of several stages: the initial charging of the gate-source capacitance (C_GS), the charging of the gate-drain capacitance (C_GD) during the Miller plateau, and the final charge saturation as the device reaches full conduction. As shown in Figure 13, under normal operating conditions, the presence of the Miller plateau results in a prolonged turn-on time, where both C_GS and C_GD charge gradually. During normal operation, the gate charge curve exhibits a clear Miller plateau characterized by simultaneous charging of C_GS and C_GD from the initial time to the Miller plateau, followed by a period dominated by the C_GD charge. The total gate charge (Q_nor) is the sum of charges during these intervals, resulting in a higher overall charge compared to fault conditions.

In contrast, during a short-circuit event like HSF, the V_GS rapidly reaches the preset level, quickly charging C_GS and C_GD without the typical delay caused by the Miller plateau. This results in a lower total gate charge (Q_SC) compared to normal operation, as the absence of a Miller plateau shortens the overall charging duration. The gate charge-based SC detection method leverages the difference in total gate charge between normal and fault conditions. As shown in Figure 14, by monitoring the V_GS and comparing the total gate charge to a reference threshold (Q_ref), the system can accurately detect short-circuit events. The protection mechanism is triggered when V_GS exceeds a predefined reference value, and the total gate charge remains below Q_ref, indicating an abnormal charging pattern indicative of a short circuit. This method offers precise detection of short-circuit events by focusing on the unique charging characteristics of the gate, allowing for rapid response times. It reduces false positives by analyzing the total gate charge alongside V_GS, distinguishing between normal switching transients and genuine fault conditions. Additionally, the gate charge-based method is particularly well suited for SiC MOSFETs, characterized by fast switching speeds and sensitive gate charge dynamics. Overall, the gate charge-based short-circuit detection method provides a sophisticated and effective means of identifying and mitigating short-circuit events in power semiconductor devices, enhancing the reliability and safety of power electronic systems, especially those utilizing SiC MOSFETs.

5.4. Two-Dimensional SC Detection Method

The two-dimensional method enhances fault detection by simultaneously monitoring both V_GS and I_DS [33,91,92,93]. As shown in Figure 15, it relies on the premise that specific fault conditions, such as SCs or abnormal load scenarios, induce distinctive changes in the V_GS and I_D characteristics. By analyzing the coordinated behavior of these parameters, the protection circuit distinguishes normal operation from potential fault conditions. The method involves establishing criteria for fault detection based on the relationship between V_GS and I_DS, allowing for a more comprehensive approach to identifying deviations from expected behavior. Monitored V_GS and I_D values are compared with predetermined threshold levels, and if deviations beyond these thresholds are detected, the protection mechanism is promptly activated. The response often entails the immediate shutdown of the SiC MOSFET to prevent further damage. While offering enhanced sensitivity and comprehensive fault detection capabilities, the method may introduce increased circuit complexity compared to single-parameter approaches, necessitating precise threshold calibration for accurate fault detection. The two-dimensional method finds applications in critical systems where a thorough understanding of both V_GS and I_D behavior is crucial for effective fault detection and rapid protective response. This versatility makes it suitable for various fault conditions, though it requires additional circuits, potentially introducing complexity.

Another combined method is power loss estimation, which estimates the power loss of a SiC MOSFET by monitoring V_DS and I_D to identify abnormal conditions [34]. Inspired by the abovementioned method, an indirect power dissipation level short-circuit protection (IPDL-SCP) method is proposed in [34], while using as few components as possible. The method monitors the voltage oscillation of the source parasitic inductance (V_SS) combined with the V_DS of the SiC MOSFET, as shown in Figure 16. The protection is activated when both characteristics exceed safety values, indicating that the SiC MOSFET has already operated in overpowering conditions. While offering insights into power dissipation, this method demands accurate calibration and introduces additional losses.

Table 3. Comparison between conventional SC detection methods.

Parameters	Methods	Noise Immunity	Temp. Effect	Cost/Complexity	Response Time		Ref.
					HSF	FUL
VDS	VDS	Low	High	Low/simple	450 ns~1.5 µs	1.5 µs	[30,65,66,67]
	dVDS/dt	Low	High	Low/moderate	250 ns	-	[68]
		Low	High	Low/moderate	700 ns	1.5 µs	[69]
ID	Rogowski coil	High	Low	High/complex	<100 ns	<100 ns	[35,70,71,72,73,74,75,76,77,78,90]
	dIDS/dt	Moderate	Low	Moderate/moderate	<100 ns	<100 ns	[30,79,80,81,82,83,84]
	TMR sensor	High	Low	High/complex	<100 ns	<100 ns	[73,85]
Gate	QG	Low	High	Moderate/moderate	173 ns	-	[86,87,88,110]
	Gate leakage current	Low	High	Moderate/complex	137 ns	86 ns	[90]
Combined	VGS and dIDS/dt	Moderate	Moderate	High/complex	<50 ns	<100 ns	[33,91,92,93]
	VDS and ID	Moderate	Low	High/complex	-	170 ns	[34]

summarizes all the conventional methods.

6. Soft Turn-Off Strategy for SiC MOSFETs during SC

After detecting a short circuit, the next step is to initiate the turn-off process to prevent the device from overheating and potential damage. In case of a short circuit, a SiC MOSFET cannot be abruptly turned off due to the potential for dangerous voltage spikes in V_DS. Voltage spikes occur when the current flow is abruptly stopped due to the inductive elements present in the circuit, such as inductors, transformers, or even parasitic inductances within components and wiring. Inductive components store energy in their magnetic fields while current flows through them. When this current is suddenly interrupted, the stored energy has no gradual path for dissipation, resulting in a high voltage spike as the inductor attempts to maintain current flow. Instead of abruptly stopping current flow, which can cause high voltage spikes and potential damage, STO gradually reduces the current, minimizing excessive voltage transients and stress on both the device and surrounding circuitry. This gradual reduction also helps prevent high voltage spikes that could exceed the device’s voltage ratings, thus avoiding breakdown or failure. Additionally, STO mitigates EMI by lowering the rate of change in current and voltage, which contributes to overall circuit stability. It also reduces thermal and electrical stress on the device, protecting it from damage and thermal runaway, which can lead to catastrophic failure. By smoothing the transition from the on to off state, STO improves the device’s reliability and longevity, extending its operational life and enhancing overall system performance. Several STO methods are described below, including the soft slope turn-off, two-step turn-off, and multi-step turn-off methods [36,67].

STO significantly influences the junction temperature and lifecycle of SiC MOSFETs during short-circuit conditions. By gradually reducing the current flow rather than abruptly stopping it, STO helps control the rate of thermal rise within the device, effectively managing the junction temperature. This gradual decrease in current minimizes sudden heat generation, reducing thermal stress and preventing rapid temperature spikes. As a result, the junction temperature remains within safer limits, reducing the risk of thermal runaway and damage. Additionally, STO extends the operational lifespan of SiC MOSFETs by mitigating high thermal and electrical stresses that could otherwise lead to premature degradation of the device. Improved thermal management and reduced mechanical stress contribute to enhanced reliability and performance, ensuring that the device remains intact and functional over a longer period. Several STO methods are described below, including the soft slope turn-off, two-step turn-off, and multi-step turn-off (MSTO) methods [36,67].

6.1. Soft Slope Turn-Off Method

The soft slope turn-off method gradually reduces the gate voltage, allowing for a controlled decrease in drain current, as shown in Figure 17. This approach uses an adjustable STO current determined by a resistor (R_soft), which makes it relatively easy to implement on-chip. However, it requires customization for different SiC MOSFETs due to input capacitance (C_GS) variations across devices. The STO time must be optimized for various SiC MOSFET sizes and current capacities, often necessitating additional circuitry for proper adjustment.

6.2. Two-Step Turn-Off Method

In contrast, the two-step turn-off method employs a two-stage approach using a Zener diode and a sinking MOSFET, as shown in Figure 18. Initially, it clamps the V_GS to an intermediate level, allowing for a gradual decrease in drain current, followed by a complete turn-off by the main driver [36]. This method provides a more consistent STO time regardless of the SiC MOSFET’s current capacity, making it easier to implement across different devices without extensive customization. However, it may produce two V_DS spikes during the two-stage clamping operation. Both methods aim to reduce stress on the SiC MOSFET during turn-off under short-circuit conditions, offering different trade-offs regarding implementation complexity and performance across various device specifications.

6.3. Multi-Step Turn-Off Method

In multi-step STO as shown in Figure 19, a MOSFET array controlled by an 8-bit digit is integrated in the gate driver [111]. After an overcurrent signal is generated, the MSTO circuit begins to sense V_DS by connecting with the external capacitor, to control the MOSFET array according to the VDS variation. An external capacitor is applied, coupling V_DS with V_CPL. In addition, the MSTO controller has a delay of ~15 ns, including a settling time of V_CPL after connecting to the external capacitor, propagation, and comparison delay of the controller. The V_CPL voltage is converted to an 8-bit thermometer code through the flash ADC in real time. The 8-bit codes determine the number of on/off MOSFETs required in the MOSFET array. This allows for real-time control of the number of MOSFETs turned off. This adjustment helps manage the sinking current and reduces VDS overshoot, enhancing the reliability of SiC devices in high-voltage applications. A comparison of different STO techniques is presented in

Table 4. Comparison between different STO methods.

STO Methods	Advantages	Disadvantages	Delay Time
SOFT-SLOPE STO	- Reduced voltage spikes - Improved EMI performance - Enhanced device reliability - Simple design	- Slower response time - Increased switching losses	- 900 ns [36]
TWO-STEP STO	- Optimized trade-off between switching speed and voltage spikes - Reduced EMI - Moderate circuit design	- Potential VDS peak - Moderate switching losses - Potential for intermediate stress	- 500 ns [36]
MULTI-STEP STO	- Enhanced control over switching - Minimized voltage spikes and EMI - Superior protection	- Highest complexity - Implementation challenges - Increased overall losses	- 166 ns~1642 ns [111]

.

7. Conclusions

This article offered a detailed overview of the latest research on short-circuit protection for SiC MOSFETs. It began by outlining the challenges related to the device structure and the consequences of faster switching speeds. The paper then categorized and described advanced short-circuit detection methods into four key types: V_DS-based detection, gate charge-based detection, I_DS-based detection, and two-dimensional (2D) detection methods. Each method’s principles, advantages, and limitations were thoroughly examined. The article also reviewed STO techniques used in short-circuit situations. Advancing SiC MOSFET protection will support broader use in high-power applications, driving innovation and efficiency in power electronics. This review provides a foundation for future research, aiming for more reliable and efficient power systems across industries.