Quasi-Resonant Single-Switch High-Voltage-Gain DC-DC Converter with Coupled Inductor and Voltage Multiplier Cell

Abstract

This paper introduces a quasi-resonant high-efficiency high-step-up DC–DC converter requiring a reduced number of components. The proposed circuit uses a coupled inductor associated with voltage multiplier cells to ensure high-voltage-gain operation without the necessity of an extremely high number of turns ratio. Quasi-resonant operation guarantees zero current switching (ZCS) for some diodes of the converter. A detailed steady-state analysis is carried out aiming at the adequate design of the circuit. Experimental results taken from the testing of a 400 W prototype operating in closed loop with an input voltage range of 25–48 V, output voltage of 400 V and switching frequency of 100 kHz validate the analysis carried out and demonstrate the feasibility of the proposed converter.

1. Introduction

Techniques associated with the generation of electrical energy have been improved to address the challenges associated with climate change and contribute to sustainable development. In this sense, production of electrical energy from renewable resources, such as wind, solar and biomass, is not an alternative anymore but a necessity [1,2]. Considering photovoltaic (PV) and fuel cell (FC) systems, the voltage levels are usually low and in the form of direct current (DC), diverging from the usual alternate current (AC) system that prevails in the distribution of electricity in most segments [3]. Thus, in order to adapt the voltage levels while taking into account technical and economic aspects, electronic energy processing is mandatory, from which low cost and high efficiency are expected. In this sense, high-step-up DC–DC converters are widely employed in applications where the primary energy source is characterized by a voltage level much lower than that required for the end use [4,5,6,7,8].

Providing energy to a DC distribution system or conditioning the voltage as an intermediate stage of a DC–AC conversion system are some applications of DC–DC converters. One of the main challenges in the use of such converters is to avoid expressive switching and conduction losses. Therefore, using circuits with a reduced number of components, featuring low-voltage stress on the semiconductors and with the ability of recycling the leakage energy are key to improving the overall system efficiency. However, achieving all these characteristics is not an easy task. One classic example is the boost converter, which is indeed a simple circuit but exhibits poor performance under high-voltage-gain conditions [9]. Addressing the limitations of the boost converter by the use of techniques to improve the voltage gain has been extensively investigated in the literature [10,11,12]. Among the several techniques discussed in [12], one can be highlighted: boost-based solutions using a single active switch, a single coupled inductor and voltage multiplier cells (VMCs), such as the boost-flyback and the boost associated with VMCs introduced in [13] and [14], respectively, in addition to other solutions recently reported in the literature [15,16,17,18,19]. In all these examples, voltage gain is dependent on the duty cycle (D) and on the number of turns ratio (n) of the coupled inductor. As a result, higher voltage conversion ratios can be achieved without extreme duty cycle values, and therefore a higher efficiency is expected, since conduction and switching losses are lower compared to the conventional step-up converters.

Converters employing a single active switch and reduced number of diodes and capacitors are usually not suited for applications where the power processed is higher than a few hundred watts. However, these circuits are interesting for processing energy from PV modules rated in the range of 200–600 W. In this sense, this work introduces a high-voltage-gain DC–DC converter based on the boost configuration using coupled inductor and voltage multiplier cells, as depicted in Figure 1. The key features of the proposed circuit that make it suitable for PV applications are: high efficiency; reduced number of components; low voltage stress on the semiconductors; and voltage distribution among the output capacitors. In addition, quasi-resonant characteristics guarantee ZCS operation for diodes D₂ and D₃, thus contributing to improving the system efficiency [20,21,22]. In addition, a high voltage conversion ratio can be achieved if compared with similar topologies, even though a relatively low number of turns ratio of the coupled inductor is adopted. Therefore, weight, volume and magnetic losses can be minimized.

2. Principle of Operation in Steady State

The proposed high-step-up DC–DC converter depicted in Figure 1 contains a VMC composed of the winding N_s of the coupled inductor associated with the pairs D₂/C₂ and D₃/C₃. Since this topology is able to impose high voltage levels on the capacitors, adopting a number of turns ratio close to one is possible without the need for overly high values of duty cycle. The steady-state analysis of the proposed converter is carried out for deriving a mathematical model that allows the proper choice of every component contained in the circuit. In this sense, the following assumptions are made:

• All elements are considered ideal, except for the leakage inductance of the coupled inductor;
• The voltage on the capacitors and the magnetizing current are assumed to be ripple free;
• The analysis is carried out within one period of the switching frequency f_s.

Six operating stages are verified from the analysis of the converter during one switching period, as depicted in Figure 2. From these six stages, only four are relevant in terms of the energy processed by the system. Hence, transition stages regarding the intervals ∆t₁ and ∆t₄ will be neglected from the mathematical analysis.

During the second and third stages, which correspond to the intervals ∆t₂ and ∆t₃, respectively, switch S is turned on, the magnetizing inductance L_m stores energy, and capacitors C₂ and C₃ provide energy that has been stored during the previous stages to the system. These intervals are characterized as linear stages, since resonance between the leakage inductance L_k and the capacitors contained in the circuit is not expressive. This operational condition is finished when S is turned off.

The fifth and sixth stages, defined by the intervals ∆t₅ and ∆t₆, occur when S remains in the off state. During these stages, energy stored in L_m is provided to the circuit. Resonance between L_k, C₁ and C₃ becomes expressive during the fifth stage. In this sense, if it is guaranteed that the resonant frequency is higher than the switching frequency, D₂ operates with ZCS, thus contributing to increasing the system efficiency. It is noteworthy that the fifth stage plays a crucial role in defining the voltage gain of the converter. Regarding the sixth stage, the converter returns to a linear operating characteristic.

Figure 3 presents the main theoretical waveforms regarding the converter operation in steady state. As can be seen, an abrupt change in i_Lk occurs at the end of interval ∆t₃, which is a simplifying assumption justified by the fact that the fourth stage corresponds to a very brief transition state, during which the energy processed can be neglected.

3. Mathematical Model

Fundamental information regarding the operation of the proposed converter can be extracted from the mathematical model of the circuit, such as the voltage conversion ratio and voltage stress on the semiconductor devices. Such knowledge is key to designing the circuit properly, aiming at reduced conduction and switching losses to ensure high-efficiency operation.

3.1. Steady-State Analysis

The proposed mathematical model takes into consideration the following definitions:

$$\begin{array}{l}\Delta t_i=t_i-t_{i-1}; T_s=\frac{1}{f_s}; n=\frac{N_s}{N_p}; \lambda =\frac{L_k}{L_m}; k=\frac{L_m}{L_k+L_m};\\ M=\frac{V_o}{V_{in}}; M_{C1}=\frac{V_{C1}}{V_{in}}; M_{C2}=\frac{V_{C2}}{V_{in}}; M_{C3}=\frac{V_{C3}}{V_{in}},\end{array}$$

(1)

where i defines the interval of each stage beginning at t_i−1 and ending at t_i; T_s corresponds to the switching period; f_s is the switching frequency; n defines the number of turns ratio of the coupled inductor; the factors λ and k relate the magnetizing and leakage inductances; and M, M_C1, M_C2 e M_C3 correspond to the total and partial static gains of the circuit.

The fundamental equation for i_Lk(t) valid for the interval ∆t₂ is given by (2).

$$I_{Lm}=I_{Lk1}+\left(1-\frac{M_{C1}-M_{C2}}{n}\right)\frac{\Delta t_2}{\lambda L_m}{V}_{in}$$

(2)

The energy balance of the algebraic sum of the leakage and magnetizing inductances yields (3).

$$M_{C2}+M_{C3}-M_{C1}=\frac{1}{1-D}$$

(3)

Equation (4) can be determined from the analysis of the equivalent circuit of the second stage depicted in Figure 2b.

$$M_{C1}-M_{C2}=nk$$

(4)

As previously mentioned, resonance between L_k and the pair C₁/C₃ is expressive during the fifth stage of the proposed high-step-up DC–DC converter. Thus, the analysis of this stage can be carried out using the current and voltage on these elements.

Currents on C₁ and C₃ can be written in terms of i_Lk(t) as given by (5) and (6), respectively.

$$i_{C1}(t)=\frac{I_{Lm}}{n}-\frac{\left(1+n\right)}{n}{i}_{Lk}(t)$$

(5)

$$i_{C3}(t)=-\left(\frac{I_{Lm}}{n}+I_o\right)+\frac{\left(1+n\right)}{n}{i}_{Lk}(t)$$

(6)

Equation (7) provides the voltage on the leakage inductance during the resonant stage.

$$v_{Lk}(t)=V_{in}-V_o+\frac{\left(1+n\right)}{n}{v}_{C1}(t)-\frac{1}{n}{v}_{C3}(t)$$

(7)

Differentiating (7) results in

$$\frac{d{v}_{Lk}(t)}{dt}=\frac{\left(1+n\right)}{n}\frac{d{v}_{C1}(t)}{dt}-\frac{1}{n}\frac{d{v}_{C3}(t)}{dt}.$$

(8)

Equation (8) can be rewritten in terms of the currents on C₁ and C₃, as given by

$$L_k\frac{d^2{i}_{Lk}(t)}{d{t}^2}=\frac{(1+n)}{n{C}_1}{i}_{C1}(t)-\frac{1}{n{C}_3}{i}_{C3}(t).$$

(9)

Substituting (5) and (6) into (9) results in the differential equation

$$L_k{C}_{eq}\frac{d^2{i}_{Lk}(t)}{d{t}^2}+i_{Lk}(t)=A,$$

(10)

where

$$C_{eq}=\frac{n^2}{\left(1+n\right)}\left[\frac{C_1{C}_3}{C_1+\left(1+n\right)C_3}\right],$$

(11)

$$A=\frac{1}{\left(1+n\right)}\left[I_{Lm}+\frac{n{C}_1}{C_1+\left(1+n\right)C_3}{I}_o\right].$$

(12)

Applying the Laplace transform in (10) results in (13), which represents the current i_Lk(t) in the s domain.

$$I_{Lk}(s)=\frac{\frac{A{\omega }_o^2}{s}+s{I}_{Lk2}}{s^2+{\omega }_o^2}$$

(13)

where

$${\omega }_o=\frac{1}{\sqrt{L_k{C}_{eq}}}.$$

(14)

At this time, current i_Lk(t) during the fifth stage can be determined by applying the inverse Laplace transform in (13), as given by (15). It is noteworthy that the resonant frequency f_o must be higher than the switching frequency f_s to guarantee ZCS for D₃.

$$i_{Lk}(t)=\left(V_o-\frac{1+nD}{1-D}{V}_{in}-V_{C3}\right)\frac{\sin \left({\omega }_{o}t\right)}{n{L}_k{\omega }_o}+A+\left(I_{Lk2}-A\right)\cos \left({\omega }_{o}t\right)$$

(15)

Differentiating (15) and multiplying the result by L_k provides the value of v_Lk, as given by

$$v_{Lk}(t)=\frac{1}{n}\left[V_o-V_{C3}-\frac{\left(1+nD\right)V_{in}}{\left(1-D\right)}\right]\cos \left({\omega }_{o}t\right)+{\omega }_o{L}_k\left(I_{Lk3}-A\right)\sin \left({\omega }_{o}t\right).$$

(16)

Assuming that at t = 0 v_Lk is approximately equal to 0, one can derive the partial static gain M_C3 as

$$M_{C3}=M-\frac{1+nD}{1-D}.$$

(17)

The circuit analysis reveals that the static gain M corresponds to the sum of M_C2 and M_C3, as given by (18), which allows computing M_C2 as (19).

$$M=M_{C2}+M_{C3}$$

(18)

$$M_{C2}=\frac{1+nD}{1-D}$$

(19)

Substituting (19) into (4) yields the value of M_C1 given by

$$M_{C1}=\frac{1+n}{1-D}+n k .$$

(20)

Lastly, the total voltage gain M can be determined by substituting (4) and (17) into (3).

$$M=\frac{2+n D}{1-D}+n k$$

(21)

It can be concluded from (21) that lower values of k yield lower voltage conversion ratios. On the other hand, if the leakage inductance is low, the factor k tends toward one, and consequently the voltage gain converges to an ideal operating condition. In addition, the impact of k is minimized when the number of turns ratio is lower.

Figure 4 presents several curves of the voltage gain M as a function of the duty cycle D for different values of n and k. For the condition n = 1, it is evident that the influence of k is neglectable. On the other hand, as n increases and k decreases, the voltage gain deviates from the ideal case.

The unknowns I_Lk1 and I_Lk2, as well as the intervals ∆t₂ and ∆t₅, can be determined using (2) and (15) along with the average current on D₂ e D₃, which in turn are equivalent to the average output current I_o and are given by (22) and (23), respectively.

$$\frac{1}{T_s}{\displaystyle {\int }_0^{\Delta t_5}{i}_{C1}(t) dt}=I_o$$

(22)

$$\left(\frac{I_{Lk1}-I_{Lm}}{2n}\right)\frac{\Delta t_2}{T_s}=I_o$$

(23)

To complete the mathematical model of the proposed converter, it is fundamental that the equations defining the values of C₁, C₂ and C₃, the magnetizing inductance L_m and the voltage stress on the semiconductor devices are derived.

Based on the operating stages depicted in Figure 2, it is possible to conclude that the values of C₁, C₂ and C₃ can be determined by (24), (25) and (26), respectively. However, C₁ and C₃ can also be determined using the resonance criterion given by (14) and (11), which is used in this work to calculate these capacitances.

$$C_1=\frac{1}{\Delta V_{C1}}{\displaystyle {\int }_0^{\Delta t_5}{i}_{C1}(t) dt}$$

(24)

$$C_2=\frac{1}{\Delta V_{C2}}\left[{\displaystyle {\int }_0^{\Delta t_5}\left(\frac{i_{Lk}(t)}{n}-I_o\right)dt+\frac{I_{Lm}}{1+n}\Delta t_6}\right]$$

(25)

$$C_3=\frac{D{T}_s{I}_o}{\Delta V_{C3}}$$

(26)

where ∆V_C1, ∆V_C2, ∆V_C3 are the voltage ripples on C₁, C₂ and C₃, respectively.

The magnetizing inductance L_m can be computed using

$$L_m=\frac{\left(1-D\right)\left(V_{C1}-V_{C3}\right)T_s}{n\Delta I_{Lm}},$$

(27)

where ∆I_Lm is the current ripple on L_m.

It can be concluded from Figure 2b,e that the voltage stress on D₁ and D₂ is equal to the voltage on C₁ given by (20).

$$V_{D1}=V_{D2}=\left(\frac{1+n}{1-D}+n k\right)V_{in}$$

(28)

The voltage stress on S and D₃ can be determined from the analysis of the second and fifth operating stages, resulting in

$$V_S=V_{D3}=\frac{V_{in}}{1-D}.$$

(29)

The proposed converter can be designed and validated in the laboratory based on the mathematical analysis detailed so far. Moreover, a detailed efficiency analysis can be performed to determine the advantages of the proposed circuit for the intended applications, especially PV and FC systems.

3.2. Control Strategy

As known, PV and FC systems require a proper control system to ensure maximum power point tracking (MPPT) operation. In such a system, the DC–DC converter stage is directly responsible for MPPT realization by means of controlling the input voltage or current. In this paper, a control strategy aiming at controlling the input current is adopted, in accordance with the schematic depicted in Figure 5.

In the proposed scheme, input voltage and current are measured using the digital signal processor TMS320F28377S, in which an input current compensator is implemented. First-order filters with a cutoff frequency of 1 kHz are used for signal conditioning and analog-to-digital conversion is performed with a sampling frequency equal to 100 kHz. In this work, a proportional–integral (PI) controller with proportional and integral gains of 0.005 and 15, respectively, is used to adjust the input current, which in turn allows MPPT to be realized. It is noteworthy that the small-signal analysis of the proposed circuit is very extensive due to the high number of operating stages and quasi-resonant operation, and therefore it will not be detailed in this paper. Nevertheless, closed-loop operation will be investigated to demonstrate the suitability of the proposed converter for PV and FC applications.

4. Experimental Results

The experimental verification of the proposed converter is carried out using a 400 W prototype designed in consideration of the specifications shown in

Table 1. Design specifications for a 400 W prototype.

Symbol	Description	Value
Vin	Input voltage	48 V
fs	Switching frequency	100 kHz
Po	Output power	400 W
Vo	Output voltage	400 V
n	Number of turns ratio	1
k	Inductance factor	95%
Lk	Leakage inductance	2 µH
fo	Resonant frequency	1.6·fs
∆ILm	Current ripple on Lm	45% of Iin
∆VC3	Voltage ripple on C3	1% of VC3

.

As previously mentioned, the resonance criterion was adopted to determine the capacitances C₁, C₂ and C₃. In this sense, the leakage inductance was initially estimated as L_k = 2 µH. Next, Equation (14) was used to determine C_eq, which in turn can be used to calculate C₁ and C₃ using (11). It is noteworthy that f_o was chosen to be higher than f_s, and thus ZCS is guaranteed for D₃. Based on the knowledge that the most expressive resonance occurs in the fifth stage, which corresponds to the interval ∆t₅ that can last as long as (1 − D) ·T_s, it was decided that f_o = 1.6·f_s. The main results obtained from the design of the proposed converter are listed in

Table 2. Main design results.

Parameter	Value
D	0.644
Lm	80 µH, E42/15, Np = Ns = 16
C1	3 µF/400 V
C2	3 µF/400 V
C3	3 µF/400 V
D1, D2 and D3	MUR 840
S	IRFP4668PBF

and a picture of the prototype is shown in Figure 6.

Voltage and current at the input and output are depicted in Figure 7a. Input current was measured before the decoupling capacitor C_in, resulting in a filtered low-current ripple waveform. Figure 7b shows the voltage on capacitors C₁, C₂ and C₃. The results are in accordance with the theoretical predictions given by (20), (19) and (17), respectively. The voltage and current on the switch S are depicted in Figure 8a. The waveforms indicate dissipative commutation, but it is evident that the drain-to-source voltage is much lower than the output voltage. Consequently, a low-R_DSon MOSFET can be used, thus minimizing the conduction and switching losses on this device. Voltage and current on D₁, D₂ and D₃ are shown in Figure 8b and Figure 9a,b, respectively. These results confirm that the commutation of D₁ is dissipative, as a considerable reverse recovery current is observed. However, this reverse current does not appear on the switch current (c.f., Figure 8a), and therefore its impact on the switching losses becomes limited. It can be also verified that D₂ and D₃ operate with ZCS as a result of the resonant characteristic of the current on these devices. The most expressive resonance occurring during the fifth stage and predicted in the theoretical analysis is evident on the waveform of the current on D₃. The measured resonant frequency was approximately 190 kHz, deviating from the 160 kHz (1.6·f_s) defined in Table 1. This difference was expected, because the actual leakage inductance of the coupled inductor measured in laboratory was L_k = 1.45 µH, a value lower than the 2 µH estimated during design.

Efficiency measurements were taken using the power precision analyzer Yokogawa WT500 and are presented in Figure 10. Tests under three different situations were performed to create conditions in accordance with the specifications of 250–400 W solar modules. Figure 10a presents the efficiency curve versus output power considering input and output voltages fixed at 48 V and 400 V, respectively. A maximum efficiency of 96.9% was measured at 60% of rated output power, while the full-load efficiency was 96.46%. Efficiency versus input voltage variation, maintaining the output power fixed at 400 W, is shown in Figure 10b. It is evident that the efficiency is considerably reduced at low input voltage due to increased current levels. A more realistic situation is when the output power decreases as the input voltage is reduced. Figure 10c shows the efficiency versus input voltage considering an output power variation of 250–400 W. Although an efficiency reduction is also observed as the input voltage decreases, the impact is not as severe as that verified in the test with P_o fixed at 400 W.

Finally, closed-loop operation with the output voltage fixed at 400 V is demonstrated in Figure 11. Steps in the input current reference from 4.25 A to 8.75 A and from 8.75 A to 4.25 A were applied, and the response demonstrates the proper operation of the converter using the control strategy depicted in Figure 5. In the tests, the output voltage was regulated at 400 V by the electronic load NHR9430 operating in the constant voltage mode to emulate the behavior of a grid-tied inverter stage. It is also noteworthy that the input current was measured before the filter capacitor C_in, and hence its ripple is lower than the theoretical prediction depicted in the waveform of i_Lk (c.f., Figure 3).

Comparative Analysis

The proposed converter is compared with the high-voltage-gain topologies proposed in [5,6,13,14,15,16,17], as summarized in

Table 3. Comparison between boost-based high-step-up DC–DC converters using a single active switch and one coupled inductor with only two windings.

Reference	Voltage Gain (Vo/Vin)	Voltage Stress on the Switch	Voltage Stress on the Diodes			Number of Capacitors	Number of Diodes	Efficiency η
			VD1	VD2	VD3
Proposed	$\frac{2+n }{1-D}$	$\frac{V_{in}}{1-D}$	$\left(\frac{1+n}{1-D}+n\right)V_{in}$	$\left(\frac{1+n}{1-D}+n\right)V_{in}$	$\frac{ V_{in}}{1-D}$	3	3	96.5% @400 W, 100 kHz, n = 1
[5]	$\frac{1+n }{1-D}$	$\frac{1+n }{1-D}{V}_{in}$	$\left(\frac{1+n }{1-D}-n+1\right)V_{in}$	$\frac{1+n }{1-D}{V}_{in}$	-	2	2	94% @300 W, 100 kHz, n = 3
[6]	$\frac{1+n }{1-D}$	$\frac{V_{in}}{1-D}$	$\frac{V_{in}}{1-D}$	$\frac{n{V}_{in}}{1-D}$	$\frac{n{V}_{in}}{1-D}$	3	3	96.5% @400 W, 90 kHz, n = 1.72
[13]	$\frac{1+nD }{1-D}$	$\frac{V_{in}}{1-D}$	$\frac{V_{in}}{1-D}$	Limited by the RCD snubber 1	Voltage stress on the snubber diode 1	3	3	93% @35 W, 38 kHz, n = 2
[14]	$\frac{1+n }{1-D}$	$\frac{V_{in}}{1-D}$	$\frac{V_{in}}{1-D}$	$\frac{n{V}_{in}}{1-D}$	$\frac{n{V}_{in}}{1-D}$	3	3	Not reported, 20 kHz, n = 1
[15] 2	$\frac{1+n }{1-D}+n$	$\frac{V_{in}}{1-D}$	$\frac{V_{in}}{1-D}$	$\frac{n{V}_{in}}{1-D}$	$\frac{n{V}_{in}}{1-D}$	4	4	94.3% @400 W, 50 kHz, n = 1
[16]	$\frac{1+n }{1-D}$	$\frac{V_{in}}{1-D}$	$\frac{V_{in}}{1-D}$	$\frac{n{V}_{in}}{1-D}$	$\frac{n{V}_{in}}{1-D}$	3	3	94% @300 W, 100 kHz, n = 6
[17] 3	$\frac{2+n }{{\left(1-D\right)}^2}$	$\frac{V_{in}}{{\left(1-D\right)}^2}$	$\frac{ V_{in}}{1-D}$	$\frac{D{V}_{in}}{{\left(1-D\right)}^2}$	$\frac{V_{in}}{{\left(1-D\right)}^2}$	4	5	91.1% @500 W, 40 kHz, n = 1.86

¹ Voltage stresses were not reported in the paper. ² Voltage stress on the fourth diode is similar to D₂ and D₃. ³ Voltage stresses on D_r1 and D_o are not included.

. In this comparative analysis, only circuits containing a single active switch and one coupled inductor with two windings are considered. In addition, it is assumed that the leakage inductance of the coupled inductor is much smaller than its magnetizing inductance. As can be concluded from Table 3, both the voltage gain M and the voltage stresses on the semiconductors are usually related to the number of diodes and capacitors contained in the circuits. The circuits proposed in [5,13] contain only two diodes and two capacitors, although in [5] the voltage stress on the switch and on the diode D₂ is equal to the entire output voltage level. As a result, higher conduction and switching losses are expected. The converters introduced in [15,17] exhibit the higher voltage gains, but more diodes and capacitors are employed. The boost-flyback converter proposed in [13] presents the lower voltage conversion ratio, and also requires the use of an auxiliar snubber to prevent potentially destructive voltage spikes on D₃. As a consequence, if the same duty cycle is adopted, a higher number of turns ratio is required to reach the same voltage gain, and therefore weight and cost of the coupled inductor are also increased. It is also noteworthy that the snubber required for proper operation increases the losses of the circuit, which has an impact on the overall system efficiency. The converters proposed in [6,14,16] present similar constructive and operational characteristics. The highest efficiencies are verified in the proposed converter and in the circuit introduced in [6]. However, the proposed converter has a higher voltage gain and was tested with a higher switching frequency.

5. Conclusions

A novel high-step-up DC–DC converter based on the boost converter employing one coupled inductor and voltage multiplier cells was proposed in this paper. The circuit contains a single active switch, three diodes and three capacitors, and is capable of achieving a high conversion ratio even when a low number of turns ratio is adopted. It was demonstrated that using a low number of turns ratio minimizes the influence of the leakage inductance on the voltage gain. In addition, the resonant characteristic of the circuit provides ZCS operation for two of its diodes, thus reducing the switching losses and improving the system efficiency. A detailed efficiency analysis was performed in the laboratory, and the results demonstrate that the proposed converter is a viable solution for applications with a power rating on the order of a few hundred watts, since it is capable of providing high voltage gain with a reduced number of components.