#
An Efficiency Analysis of 27 Level Single-Phase Asymmetric Inverter without Regeneration^{ †}

^{1}

^{2}

^{3}

^{4}

^{5}

^{*}

^{†}

## Abstract

**:**

^{n}= 27 levels is obtained, using n = 3 inverters in cascade and NLM modulation, which generates a flow power of the load to the inverters (regeneration). This work analyzes the semiconductor losses (switching and conduction) and the THD of the AC output voltage in function of index modulation, considering a non-regenerative modulation technique for a 27-level single-phase asymmetric inverter. To confirm the theoretical analyzes, simulation and experimental results are shown.

## 1. Introduction

_{a}(t) THD and its efficiency, evaluating the semiconductors losses before the variations of modulation index, variation of the DC voltage in the power cells, and variation of the power factor of the load that this inverter feeds. All of the above, in steady-state. Transient state analysis is not considered in this work because under this condition, the physical variables must have their limits both in value and time, such as blocking voltage, recovery current, dissipated power, collector current in the IGBT, and voltage and current in the load, etc. Furthermore, the modulation strategy analyzed considers the THD’s minimization in the voltage at the load, which is calculated for a steady-state waveform. To demonstrate the theoretical analyzes, simulation and experimental results will be shown.

## 2. Methodology

_{DCi}, I

_{DCi}, v

_{ai}, (with i = 1, 2, 3), and others are common of the power cell, as load parameters (Z

_{L}, R

_{L}, L

_{L}, θ) and load current I

_{L}.

_{DC}values are not high (experimental results with low power prototype). These parameters are used to characterize the IGBT turn-on, IGBT turn-off, and diode turn-off.

## 3. Topology

_{a}(t) has 27 levels, obtaining a low THD. Commonly for this type of asymmetric inverter, the NLM modulation technique is used, which generates power flow between the power cells, Figure 3a, for specific values of the modulation index, regardless of the type of load it feeds [16,17,18,19]. The use of AFE rectifiers or dissipation resistors is necessary for specific applications, such as AC drives.

_{i}is done by minimizing the THD of the AC voltage, Figure 1b, considering as limitation that the voltages of each inverter v

_{ai}

_{,1}, i = 1, 2, 3, are greater than or equal to zero. Avoiding the existence of regeneration [24], Figure 3b, but obtaining an output voltage with low THD (<3.0% for m = 1.0), Figure 1c. This solution eliminates the flow of power between the power cells, simplifying the converter’s topology and control.

## 4. Semiconductors Losses

#### 4.1. Switching Losses

#### 4.2. Conduction Losses

_{sat}, and the current flowing through it [29]. A first-order approximation is used to model the saturation voltage, considering threshold voltage V

_{T}, and series resistance R

_{T}, thus,

_{AVG}corresponds to the average value of the current flowing through the semiconductor, and I

_{RMS}is the RMS value of the semiconductor current. Finally, the energy dissipated during a period is,

_{COND}is the conduction time of the semiconductor. In this work (3) is used to calculate conduction losses.

## 5. Switching Frequency

_{i}; they tend to a 90°. Consequently, the inverter’s levels of the total output voltage are decreasing.

_{swdev}) of 50 Hz, until m = 0.33; in the remaining two secondary inverters (named in this way for the power supply to the load), their switching frequencies will depend on the pattern of firing of semiconductors and index modulation, Figure 6. For the secondary inverters of 27-level single-phase inverter without regeneration, the second inverter has f

_{swdev}= 250 Hz, and for the third inverter, f

_{swdev}= 850 Hz, the indicated values are for m = 1.0, where the switching frequency is maximum, and THD is minimum, Figure 5b. The gating pattern for m = 1.0 is shown in Figure 6a. As indicated aforementioned, when m decreases, the switching frequency changes in the semiconductor device, in Figure 6b shown the gating pattern for m = 0.7. Similarly, the gating signal activates the semiconductor device, in this case, IGBT with diode in antiparallel, but the activation of one of these two will depend on the voltage’s polarity the current in the load. If the polarity of the voltage and current load is the same, IGBT is on, otherwise the diode is turned on.

## 6. Simulated Results

#### 6.1. Steady-State Analysis

^{®}[30]. The simulation’s schematic is shown in Figure 7, and the parameters are shown in Table 1, and the values of the α

_{i}used are presented in Table 2.

_{a}(t). This voltage has 27 levels, with a THD of 3%. The load current is highly sinusoidal with a THD less than 1.0%. The spectrum harmonic of the load voltage is shown in Figure 8b, where the harmonics’ amplitude does not exceed 1.0%. Figure 8c shows the output voltage in each power cells v

_{ai}(t); these are in phase allowing the harmonics generated by them to cancel each other, not appearing in the load voltage v

_{a}(t); this condition is imposed by the THD minimization algorithm [24]. The above can be verified by Figure 8b,d.

_{a}(t) is shown, Figure 9a, which has 17 levels, a low harmonic content with a THD of 5.3% Figure 9b, and the load current is sinusoidal with a low THD of 1.3%. The NLM modulation technique presents current circulation between the inverters with lower DC link voltage [16,17,18,19], Figure 3a; this is because the phase between the voltage and the load current are 180° out of phase, even though the load is purely resistive. In the case of the analyzed technique [21], the inverter does not present current circulation between the inverters, Figure 9c; this agrees with what is shown in Figure 3b.

_{a}

_{2}(n) and v

_{a}

_{3}(n) for the value of m = 0.7, Figure 9d; this is imposed by the modulation technique proposed in [24]. With this, it is avoided that the asymmetric inverter’s secondary power cells have a power flow between them. Avoiding regeneration.

_{a}(t) of 3%, considered the values shown in Table 1 and Table 2. The semiconductor losses distribution in Figure 10a is shown for the conditions listed above. It extends the previous analysis for the entire range of the modulation index 0.0 < m < 1.0, but the same load, Figure 10b. It is appreciated that the 27 levels single-phase asymmetric inverter without regeneration for a range 0.8 < m < 1.0, the output voltage has a THD < 5%, with an efficiency close to 96%.

#### 6.2. Analysis before Disturbances

## 7. Experimental Results

_{a}(t), has a THD of 3.45%, and the load current i

_{a}(t) is almost sinusoidal with a THD < 2%, Figure 12a. The voltage and current load is very similar to that shown in Figure 8a. The harmonic spectrum of v

_{a}(t) is the depicted in Figure 12b, this has low-frequency harmonics, but amplitude is less than 2%. Compared with Figure 8b, it is slightly different due to the sampling time used, T

_{S}= 50 [µS]. With this T

_{S}, the amount of points for a period is 400, with a resolution of 0.9°, affecting the firing pulses for semiconductor devices. Then, the individual voltages v

_{ai}(t) and load current i

_{a}(t) are depicted in Figure 12c; these are similar are shown in Figure 8c. As the asymmetric inverter feeds an RL load with a power factor of 0.8 (i), in some instances, the load current and individual voltages have not the same polarity; with this, the antiparallel diode in the IGBT is turned on. Thus, the diode’s forward voltage is significant concerning V

_{DC}

_{2}and V

_{DC}

_{3}, Table 3, generating an offset DC in v

_{a}

_{2}(t) and v

_{a}

_{3}(t). Finally, Figure 12d shown the harmonic spectrum of the individual voltages v

_{ai}(t); these are similar to the ones shown in Figure 8d.

_{a}(t) and load current i

_{a}(t), which is similar to the one shown in Figure 9a, v

_{a}(t) has 17 levels and low harmonic content with a 6.5% THD. The harmonic spectrum of v

_{a}(t) in Figure 13b, is similar at shown in Figure 9b. As mentioned above, the difference between the simulated and experimental results is due to the resolution of 0.9° by point. The individual voltages v

_{ai}(t) and load current i

_{a}(t) are depicted in Figure 13c; the phase shift present between the voltage and current is due to the load power factor. In this case, the NLM approach presents a circulating current, creating regeneration in the lower DC voltage inverters. Figure 13d shows the experimental spectra of v

_{a}

_{1}(n), v

_{a}

_{2}(n) and v

_{a}

_{3}(n), where the fundamental component of v

_{a}

_{2}(n) and v

_{a}

_{3}(n) is zero. On the other hand, the diode voltage drop in the IGBT is significant, due to the low DC voltages used in the experimental setup. Generating a slight displacement in v

_{a}

_{2}(t) and v

_{a}

_{3}(t). Despite the above, the modulation technique avoids power flow between the power cells with lower DC voltage.

## 8. Conclusions

_{a}(t) and the semiconductors losses as a function of the modulation index, DC voltage variation, and load power factor variation.

_{a}(t) 3%. Considering a wider modulation index range, 0.8 < m < 1.0, the efficiency is near (η ≈ 96%) with a THD of v

_{a}(t) < 5%. Furthermore, the analysis shows that when faced with variations in each power cell’s DC voltage, the efficiency does not changes much. The opposite case is with variations in the load power factor, where the efficiency can vary up to 5%, the worst case being an efficiency of 91.81% for m = 0.01.

## Author Contributions

## Funding

## Institutional Review Board Statement

## Informed Consent Statement

## Data Availability Statement

## Acknowledgments

## Conflicts of Interest

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**Figure 1.**(

**a**) Topology single-phase Cascaded H-Bridge for asymmetric inverters with 27 levels with regeneration, (

**b**) individual output voltage for m =1.0, (

**c**) output voltage for m = 1.0.

**Figure 2.**Methodology used to compute efficiency in 27 levels single-phase asymmetric inverter without regeneration.

**Figure 3.**Active power distribution. (

**a**) 27-level single—phase asymmetric inverter with regeneration, (

**b**) 27-level single—phase asymmetric inverter without regeneration.

**Figure 4.**Non-linear characteristic IGBT switching process. (

**a**) IGBT Turn on, (

**b**) IGBT Turn off, (

**c**) Diode turn off.

**Figure 5.**(

**a**) Comparison THD output voltage, comparison between NLM and no regenerative modulation technique [22] (

**b**) Switching frequency distribution by semiconductor device.

**Figure 6.**Gate signals for semiconductors devices of 27-level single–phase asymmetric inverter with regeneration. (

**a**) m = 1.0, (

**b**) m =0.7.

**Figure 8.**Simulation results 27 levels single-phase asymmetric Inverter without regeneration for m = 1.0. (

**a**) Output voltage and current, (

**b**) Harmonic spectrum for output voltage v

_{a}(t), (

**c**) Individual inverter output voltages, (

**d**) Harmonic spectrum v

_{a}

_{1}(n), v

_{a}

_{2}(n), and v

_{a}

_{3}(n).

**Figure 9.**Simulation results 27 levels single-phase asymmetric Inverter without regeneration for m = 0.7. (

**a**) Output voltage and current, (

**b**) Harmonic spectrum for output voltage v

_{a}(t), (

**c**) Individual inverter output voltages, (

**d**) Harmonic spectrum v

_{a}

_{1}(n), v

_{a}

_{2}(n), and v

_{a}

_{3}(n).

**Figure 10.**(

**a**) Semiconductor losses distribution for m = 1.0, (

**b**) comparison between THD

_{va}and efficiency and 27 levels single—phase asymmetric inverter without regeneration, for all m.

**Figure 11.**Efficiency analysis in the event of disturbances. (

**a**) V

_{DCi}variation v/s m, (

**b**) θ(i) variation v/s m.

**Figure 12.**Experimental key waveforms for m = 1.0. (

**a**) output voltage v

_{a}(t) and load current i

_{a}(t), (

**b**) Harmonic spectrum for output voltage v

_{a}(n), (

**c**) Individual inverter output voltages v

_{ai}(t) and load current i

_{a}(t), (

**d**) Harmonic spectrum v

_{a}

_{1}(n), v

_{a}

_{2}(n), and v

_{a}

_{3}(n).

**Figure 13.**Experimental key waveforms for m = 0.7. (

**a**) output voltage v

_{a}(t) and load current i

_{a}(t), (

**b**) Harmonic spectrum for output voltage v

_{a}(n), (

**c**) Individual inverter output voltages v

_{ai}(t) and load current i

_{a}(t), (

**d**) Harmonic spectrum v

_{a}

_{1}(n), v

_{a}

_{2}(n), and v

_{a}

_{3}(n).

m | V_{DC1} | V_{DC2} | V_{DC3} | v_{a,1} | v_{a1,1} | v_{a2,1} | v_{a3,1} | i_{a,1} | v_{a,rms} | i_{a,rms} | R_{L} | L_{L} |
---|---|---|---|---|---|---|---|---|---|---|---|---|

1.0 | 900[V] | 300[V] | 100[V] | 1318[V] | 1077[V] | 206.9[V] | 34.75[V] | 9.265[A] | 1319[V] | 9.268[A] | 114.1[Ω] | 27.23[mH] |

0.7 | 923.1[V] | 923.1[V] | 0.000[V] | 0.000[V] | 6.484[A] | 924.4[V] | 6.484[A] |

m | α_{1} | α_{2} | α_{3} | α_{4} | α_{5} | α_{6} | α_{7} | α_{8} | α_{9} | α_{10} | α_{11} | α_{12} | α_{13} |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|

1.0 | 2.13° | 6.48° | 10.9° | 15.2° | 19.9° | 24.8° | 29.6° | 34.7° | 40.2° | 46.1° | 52.7° | 60.6° | 71.1° |

0.7 | 3.00° | 8.92° | 15.4° | 21.7° | 36.3° | 36.3° | 44.1° | 51.4° | 65.3° | 90.0° | 90.0° | 90.0° | 90.0° |

m | V_{DC1} | V_{DC2} | V_{DC3} | v_{a,1} | v_{a1,1} | v_{a2,1} | v_{a3,1} | i_{a,1} | v_{a,rms} | i_{a,rms} | R_{L} | L_{L} |
---|---|---|---|---|---|---|---|---|---|---|---|---|

1.0 | 90[V] | 30[V] | 10[V] | 132.1[V] | 109.1[V] | 20.58[V] | 6.769[V] | 1.750[A] | 132.1[V] | 1.792[A] | 58[Ω] | 138[mH] |

0.7 | 92.88[V] | 93.33[V] | 1.476[V] | 1.223[V] | 1.279[A] | 93.07[V] | 1.285[A] |

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**MDPI and ACS Style**

Espinosa, E.; Melín, P.; Baier, C.; Espinoza, J.; Garcés, H. An Efficiency Analysis of 27 Level Single-Phase Asymmetric Inverter without Regeneration. *Energies* **2021**, *14*, 1459.
https://doi.org/10.3390/en14051459

**AMA Style**

Espinosa E, Melín P, Baier C, Espinoza J, Garcés H. An Efficiency Analysis of 27 Level Single-Phase Asymmetric Inverter without Regeneration. *Energies*. 2021; 14(5):1459.
https://doi.org/10.3390/en14051459

**Chicago/Turabian Style**

Espinosa, Eduardo, Pedro Melín, Carlos Baier, José Espinoza, and Hugo Garcés. 2021. "An Efficiency Analysis of 27 Level Single-Phase Asymmetric Inverter without Regeneration" *Energies* 14, no. 5: 1459.
https://doi.org/10.3390/en14051459