Realization of 485 Level Inverter Using Tri-State Architecture for Renewable Energy Systems

Abstract

In this paper, a ‘k’-state inverter producing a higher number of voltage levels was designed, and we studied the inverter’s working. Further, a tri-state inverter was derived from the ‘k’-state inverter, which could build a maximum number of output voltage levels with the requirement of fewer components, thereby reducing the cost and size. A single Tri-state architecture generates three direct current (D.C.) voltage levels; therefore, cascading five tri-state architectures can generate 242 levels of DC voltages. Further, the inversion is done via the H bridge, which leads to 485 levels of the output voltage. Algorithms to design the amplitude of voltage sources and the generation of pulses are discussed in this paper. The proposed tri-state inverter takes a significant role in advancing renewable energy systems in utilizing inverter technology. A simulation study validated the operation of the proposed inverter. Moreover, an experimental setup was built for a single-phase 485-level inverter, and the structure’s performance was verified through the experimental results.

1. Introduction

The Multilevel Inverter (MLI) gets attention due to its low electrical stress, common-mode voltage, harmonic distortion, and electromagnetic interference. With fewer components, this MLI plays a vital role in applications such as electric vehicles, renewable energy systems, and High Voltage Direct Current (HVDC) [1,2,3,4]. A complete review of MLI with fewer components is done in Reference [5,6]. Moreover, new topologies of inverters were investigated in References [7,8] to reduce the harmonic contents.

In [9], a nine-level MLI with a voltage Total Harmonic distortion (THD) of 13.51% for a resistive load is proposed. Additionally, the authors have compared MLI’s performance in terms of THD and ripple normalized mean square for various modulation indices. In [10], an 11 level MLI is developed in real-time with fewer components. Besides, three algorithms are discussed by the authors to design the values of DC sources. In [11], an 11 level symmetric MLI with 12 IGBT’s and 15 levels asymmetric MLI with 10 IGBT’s are presented in view of reduced circuit components. Furthermore, hybrid MLI topology is designed for high voltage applications.

In [12], a symmetric 13 level and 15 level MLI with only ten switches are constructed. In [13], a design of 15 level MLI and 25 level MLI with 10 and 12 switches, respectively, is carried out. In [14], the authors proposed a 16 level basic unit with a low switch count and sources. In [15], a 17 step inverter with eight switches and four DC sources is presented. Furthermore, the 17 step inversion is obtained without any additional circuit at the output.

In [16], the development of 15 and 25 output voltage levels with 12 switches is carried out. The THD obtained for 25 level output voltage is 3.35%. In [17], using switched capacitor units, the authors designed a 25 level inverter with only 12 switches. The voltage levels at the output can be doubled without a transformer. In [18], a 49 voltage level inverter with a new H-bridge structure using 12 switches, two diodes, and two DC sources is presented.

Further, in [19], the authors have built an inverter to obtain 53 output voltage levels with fewer switches. In [20], a 53 level MLI with 13 switches is simulated. The numbers of levels at the output can be increased by extending the same topology, but a short circuit will occur due to the unnecessary turn-on of body diode available across the switches. Hence, the authors restricted the number of voltage levels to 53 and simulated the same.

In [21], to identify DC voltage sources’ amplitude, eight different methods were provided. Further, a 57 level inverter with a reduced number of power switches is designed using the fourth method. In [22], authors have modified the MLI output using packed U cells and achieved 147 levels in the output. In [23], a 9 level symmetric inverter structure, 13 and 17 level inverter structure using binary (2ⁿ) and trinary (3ⁿ) configuration is designed. In [24], the authors developed an H-bridge to generate a 5 level and 25 level inverter using symmetrical and asymmetrical voltage sources, respectively. In [25,26], working of asymmetric type MLI operations were presented.

The above shows that it is a challenge to reach a higher number of voltage levels beyond the 150 level with a minimal number of controlled switches. The development and working of a 485 level inverter using tri-state architecture are discussed in this paper. The tri-state architecture inverter developed in this paper supports the renewable energy system in converting direct current to the alternating current supply. Moreover, this architecture is designed in such a way to yield higher voltage levels with less harmonic content without the need for filters. In order to validate the proposed structure, simulation and experimentation are carried out. Further, the results are analyzed in comparison with theoretical results.

2. Development of 485 Level Inverter Using Tri-State Architecture

The proposed 485-level tri-state inverter can be used in photovoltaic and fuel cell power generation systems (Figure 1). A series of fuel cell or Photo Voltaic arrays can be connected to match the magnitude of voltage sources in the proposed inverter. The proposed tri-state inverter feeds the power to the load. The inverter was designed to operate at grid frequency.

2.1. Working of k-State Inverter

Consider the architecture shown in Figure 2, which can generate ‘k’ number of states from every structure. More voltage levels are built by cascading ‘j’ number of such units. The switching combination for the k-state architecture is mentioned in

Table 1. Switching combination for the k-state architecture.

Level Generation (Volts)	Switching Combination
0	TUj1	TUj2	TUj3	…	TUjk
$y^0\times (3^{j-1})$	TUj1	TUj2	TUj3		TUjk
$y^1\times (3^{j-1})$	TUj1	TUj2	TUj3		TUjk
…
$y^k\times (3^{j-1})$	TUj1	TUj2	TUj3		TUjk

. Only a single switch will be turned on in each k-state architecture at a particular time to generate a voltage level. Therefore, to generate a maximum voltage between the nodes ‘X’ and ‘Y’ (Figure 2), the number of switches to be turned on will be equal to ‘j.’ The input voltage source connected to generate a maximum voltage between the nodes ‘X’ and ‘Y’ is also equal to ‘j’. The shaded portion in Table 1 indicates the ‘ON’ status of the switch in the j^th structure. For example, zero voltage state is realized by turning on ‘TU_j2’, voltage $y^0\times (3^{j-1})$ is realized by turning on ‘TU_j1,’ and voltage $y^k\times (3^{j-1})$ is realized by turning on ‘TU_jk’. Magnitudes of DC sources in each unit are selected as: 0, $y^0\times (3^{j-1})$, …, $y^{k-2}\times (3^{j-1})$ (‘j’ = number of k-state units and y = 1, 2,…). With these values, the voltage obtained between the nodes ‘X’ and ‘Y’ is given in Equation (1).

$$V_{xy}={\displaystyle \sum }_{i=1}^j(x_{i1}\overline{x_{i2}}V{T}_{i1}+x_{i2}\overline{x_{i3}} V{T}_{i2}+x_{i3}\overline{x_{i4}} V{T}_{i3}+ \dots \dots ..+ x_{ik}\overline{x_{i\left(k+1\right)}} V{T}_{ik})$$

(1)

with $\overline{x_{i\left(k+1\right)}}=1$, VT_i2 = 0 and $x_{ik}$—switch state (0 or 1)

The same switching combination is used in realizing alternating waveform by suitably adding an H-bridge to the cascaded structures.

The number of switches required for constructing a k-state inverter with ‘j’ number of structures is given as,

$$N_{devices,kj}=\left(k\times j\right)+4$$

(2)

The number of sources required to construct ‘k’ state inverter and the peak value of the voltage obtained is written as,

$$N_{sources}=j\times \left(k-1\right)$$

(3)

A single ‘k’—state architecture consists of switches ‘TU₁₁’, ‘TU12’, …., ‘TU1k’. For the j^th k-state architecture, the switches present in the design is given as ‘TU_j1’, ‘TU_j2’, …., ‘TU_jk’. Turning on a single switch in each ‘k’—state architecture is enough to generate an output level between nodes ‘X’ and ‘Y.’ The same is explained in Table 1. Aforementioned, to generate a maximum level between nodes ‘X’ and ‘Y,’ the number of switches to be turned on will be equal to ‘j.’

2.2. Development and Design of Tri-State Architecture Based Inverter

The increase in the number of states in each architecture beyond 3 (i.e., k = 3) results in redundancy in voltage levels. Thus, the requirement of voltage sources is increased with the cost. Hence tri-state architecture is preferred to avoid redundancy and to minimize the usage of voltage sources. This tri-state architecture is developed using three switches and two variable DC sources [20].

The number of voltage levels (N_level) generated by the proposed tri-state architecture as stated in Equation (4).

$$N_{\mathrm{level}}=\left(2\times k^j\right)-1$$

(4)

The number of switches (N_switch) needed to design a tri-state architecture based inverter are shown in Equation (5).

$$N_{switch}=3j+4$$

(5)

Suitable switching is done in each tri-state architecture to generate voltage levels. In the j^th tri-state architecture (k = 3), to generate zero voltage, switch ‘TU_j2’ is turned on, to generate $y^0\times (3^{j-1})$ V at the output, switch ‘TU_j1’ is turned on and to get $y^1\times (3^{j-1})$ V at the output, switch ‘TU_j3’ is turned on (Figure 2).

The magnitude of DC voltage sources is designed by considering $V{T}_{i3}=y\times V{T}_{i1}$. In general, the amplitude of the ‘VT_i1’ and ‘VT_i3’ is given in Equations (6) and (7).

$$V{T}_{i1}=3^{j-1}$$

(6)

$$V{T}_{i3}=y\times (3^{j-1})$$

(7)

The value of ‘y’ is selected among 1, 2, 3, and 4 in such a way that the following constraints are satisfied, and they are:

i.

Smooth step variation in the output so that waveform is sinusoidal.

ii.

Capable of generating more voltage levels.

iii.

Redundancy is avoided in the levels of voltages.

With the values mentioned above of ‘y’, Figure 3 is drawn, and

Table 2. Design procedure to find the value of ‘y’ in a Tri-State Inverter.

Details	y = 1			y = 2			y = 3			y = 4
Redundancy	Yes			No			Yes			Yes
j	VTi1	VTi2	VTi3	VTi1	VTi2	VTi3	VTi1	VTi2	VTi3	VTi1	VTi2	VTi3
1	1	0	1	1	0	2	1	0	3	1	0	4
2	3	0	3	3	0	6	3	0	9	3	0	12
3	9	0	9	9	0	18	9	0	27	9	0	36
4	27	0	27	27	0	54	27	0	81	27	0	108
5	81	0	81	81	0	162	81	0	243	81	0	324
Waveform smoothness	Not smooth			Smooth			Not smooth			Not smooth

is created with the values of j = 1, 2, 3, 4, and 5. These constraints are satisfied when the value of ‘y’ becomes 2. Though the peak value of y = 3 and y = 4 are higher than the peak value of y = 2, the waveforms obtained are not smooth. Thus, there is an increase in harmonics content for y = 3 and y = 4. From Figure 3 and Table 2, it is understood that the tri-state inverter has the capability of generating the highest level, i.e., 243 levels of voltage, without any redundancy for the value of y = 2. Further, an H bridge is added to get 485 levels of output voltage, including 242 levels of positive voltages, 242 levels of negative voltages, and one zero level (Figure 3), and thus, the waveform becomes smooth.

Additionally, it was realized that an increase in the number of structures increases the number of output voltage levels. In the proposed work, five structures were considered to design a 485 level tri-state inverter.

2.3. Development of 485 Level Tri-State Inverter

Figure 3 shows the plot between the number of tri-state architectures and the number of voltage levels obtained before and after the H-bridge inverter. Tri-state architecture with five cascaded structures generates 242 levels of positive voltages without an H bridge. These voltage levels are achieved by following

Table 3. Level generation pattern of a Tri-State Inverter.

Vo	Level-0			Level-1				Level-169				Level-242
	0 Volts			1 Volt				169 Volts				242 Volts
Tri state units/Bit	$3^{j-1}$	Zero	$2\times (3^{j-1})$	$3^{j-1}$	Zero	$2\times (3^{j-1})$		$3^{j-1}$	Zero	$2\times (3^{j-1})$		$3^{j-1}$	Zero	$2\times (3^{j-1})$
j = 1 1st bit	1	0	2	1	0	2	…	1	0	2	…	1	0	2
j = 2 2nd bit	1	0	2	1	0	2		1	0	2		1	0	2
j = 3 3rd bit	1	0	2	1	0	2		1	0	2		1	0	2
j = 4 4th bit	1	0	2	1	0	2		1	0	2		1	0	2
j = 5 5th bit	1	0	2	1	0	2		1	0	2		1	0	2

.

Figure 4 shows the development of a 485 level tri-state inverter by cascading five tri-state architectures. Using Equations (2) and (3), 19 controlled switches and 10 DC sources were required to construct 485 voltage levels. DC source values were obtained from Equations (7) and (8). VT₁₁, VT₂₁, VT₃₁, VT_41, and VT₅₁ are taken as 1 V, 3 V, 9 V, 27 V, and 81 V. The voltage values of VT₁₂, VT₂₂, VT₃₂, VT_42, and VT₅₂ are considered as zero. The voltage values of VT₁₃, VT₂₃, VT₃₃, VT_43, and VT₅₃ are considered as 2 V, 6 V, 18 V, 54 V, and 162 V, respectively, to design a 485 level tri-state inverter.

As the proposed inverter is constructed using five tri-state architectures, each and every architecture has assigned a single bit and hence, the total number of bits required becomes five. Five bits are assigned sequentially to each tri-state architecture and it is shown in Table 3.

For the voltage levels, corresponding bits are shaded, and it is shown in Table 3. From the identified voltage sources, corresponding switches connected with the sources, i.e., TU₅₃, TU₄₂, TU₃₂, TU_23, and TU_11, are turned on to build 169 volts.

Voltage level 169 is considered an example to understand how to construct any voltage level and generate pulses for the switches in the tri-state inverter. The following steps were used to realize 169 volts.

Step 1:

Calculate (169)₃, and it is obtained as 20021.

Step 2:

From the value 20021, suitable voltage sources and switches are identified, shown in

Table 4. Selection of voltage sources and switches.

Bit	5	4	3	2	1
Voltage source value	162	0	0	6	1
Switch identified	TU53	TU42	TU32	TU23	TU11

.

From Table 4, the device connected with a 162 voltage source is switched on for the MSB, the device connected with zero voltage source is turned on for the fourth bit as well as for the third bit, the device connected with six voltage source is turned on for the second bit, and the device connected to one voltage source is turned on for the first bit.

The operation modes to obtain 0 V, 1 V, 169 V, 242 V, −1 V, −169 V, and −242 V output voltage at the load are explained as follows;

• Stage 1 to generate ‘0’ Volt:

The switches TU_12, TU_22, TU_32, TU_42, TU_52, T_1, and T_2, are to be turned on to achieve the ‘0’ voltage level at the output. The ‘ON’ state and ‘OFF’ state of the switches are demonstrated in Figure 5a. From the Figure, no voltage sources are connected, and thus, 0 V is achieved at the output.

• Stage 2 to generate ‘+1’ Volt/‘−1’ Volt:

The switches TU_11, TU_22, TU_32, TU_42, TU_52, T_1, and T_2, are to be turned on to achieve the 1st positive level at the output, shown in Figure 5b. From the Figure, the voltage source VT₁₁ is connected by turning on the switch TU_11, and the output voltage obtained is +1 V. To construct corresponding negative voltage, TU_11, TU_22, TU_32, TU_42, TU_52, T_3, and T₄ are to be turned on, which is shown in Figure 5c.

• Stage 170 to generate ‘+169’ Volt/‘−169’ Volt:

The switches TU_11, TU_23, TU_32, TU_42, TU_53, T_1, and T_2, are to be turned on to achieve the 169th positive level at the output, shown in Figure 5d. From the Figure, the voltage source VT_11, VT_23, and VT₅₃ are connected to the load, and the output voltage obtained is +169 V. To construct corresponding negative voltage, TU_11, TU_23, TU_32, TU_42, TU_53, T_3, and T₄ are to be turned on which is shown in Figure 5e.

• Stage 243 to generate ‘+242’ Volt/‘−242’ Volt:

The switches TU_13, TU_23, TU_33, TU_43, TU_53, T_1, and T_2, are to be turned on to achieve the 242th positive level at the output, shown in Figure 5f. From the Figure, the voltage source VT_13, VT_23, VT_33, VT_43, and VT₅₃ are connected to the load, and the output voltage obtained is +242 V. To construct corresponding negative voltage, TU_13, TU_23, TU_33, TU_43, TU_53, T₃ and T₄ are to be turned on which is shown in Figure 5g.

Thus, the tri-state inverter can generate 242 positive levels, 242 negative levels, and 0 levels at the output. The peak voltage obtained across the load is ±242 V.

2.4. Comparative Study of Existing MLI Designs with the Proposed Inverter Structure

Table 5. Comparison between the number of state architectures and generated output levels.

Generalized Form	Number of Levels
Single state [8]	j2 + j + 1
Two state [8]	$(2^{j+1})-1$
Tri-state inverter proposed	$(2\times 3^j)-1$

indicates the comparison among the single state, two-state and tri-state inverters in a generalized way. From Table 5, in comparison with the single state and two-state, the tri-state logic proposed in this paper can produce more voltage levels at the output.

The variety of inverters designed in References [9,10,11,12,16,22] are named as RE [1], RE [2], RE [3], RE [4], RE [5], RE [6].

Table 6. Circuit parameter count comparison of MLI in terms of the number of structures.

Reference	Named as	Switches	Sources	Output Levels
[9]	RE [1]	4j + 1	j	$3^j$
[10]	RE [2]	2j + 4	j	$2j+1$
[11]	RE [3]	2j + 4	j	$2\times (2^j)-1$
[12]	RE [4]	4j + 6	4j + 2	$8j+7$
[16]	RE [5]	6j	2j	$5^j$
[22]	RE [6]	2j + 2	j	$(2^{j+1})-1$
Tri-state inverter	TS	3j + 4	2j	$(2\times 3^j)-1$

compares the existing MLI with the proposed inverter (TS) in terms of the number of structures. In RE [1], two variable DC supplies are utilized to develop a nine-level at the output, and in RE [3], three sources are used to generate the fifteen level in the output voltage. RE [2] and RE [6] utilize the five sources and generate 11 and 147 voltage levels, respectively. RE [4] proposes a fifteen level MLI with six sources. Further, RE [5] fabricates 25 levels MLI using four voltage sources.

The tri-state inverter produces the highest level of four hundred and eighty-five voltage levels at the output by utilizing ten variable DC voltage sources than the existing MLI in [1,2,3,4,5,6], which is shown in Figure 6.

The plot for the utilization of switches with respect to the number of output voltage level generation is shown in Figure 7. The plot shows that RE [1] constructs nine-level output using nine switches. RE [3] and RE [4] utilize ten switches to produce fifteen levels at the output. RE [2], [5], and [6] use fourteen, twelve, and sixteen switches to produce eleven, twenty-five, and one hundred and forty-seven output levels, respectively. Whereas, in the proposed work, nineteen controlled switches were required for producing four hundred and eighty-five voltage levels at the load.

Figure 8 shows the number of voltage levels achieved by the earlier authors and the proposed 485 level tri-state inverter. From the above, it is clear that the proposed tri-state inverter could produce the highest voltage level in the output with fewer controlled switches and sources. Moreover, the overall space used by the proposed design was less than the existing structures.

3. Simulation and Experimentation of Tri-State Inverter

The design work of five tri-state architectures connected in series with a half-bridge was carried out using the MATLAB/Simulink R2013a, and the design was capable of producing 485 output voltage levels.

The amplitude of the variable voltage sources was achieved from Equations (7) and (8). The simulation design was tested for resistive load and impedance load with 400 ohms and (400 + j23.55) ohm, respectively. Pulses were generated using the logic explained in Section 2.2. The blocking diode was connected in a series with each device to avoid unnecessary turn-on of the anti-parallel diodes across the switches, as shown in Figure 9.

3.1. A Systematic Approach in Designing the Experimentation of Tri-State Inverter

The five tri-state architectures connected in series produces 242 positive output voltage levels. Further, it can be extended to 485 levels of alternating voltage levels using an H-bridge configuration along with the tri-state inverter.

The amplitude of the voltage sources in the five tri-state architectures is arrived at using the relation explained in

Table 7. Design procedure for the DC sources.

Structure No	First Leg			Second Leg		Third Leg
	Symbol	Value (V)	Relation	Symbol	Value (V)	Symbol	Value (V)	Relation
1	VT11	1	30	VT12	0	VT13	2	$2\times 3^0$
2	VT21	3	31	VT22	0	VT23	6	$2\times 3^1$
3	VT31	9	32	VT32	0	VT33	18	$2\times 3^2$
4	VT41	27	33	VT42	0	VT43	54	$2\times 3^3$
5	VT51	81	34	VT52	0	VT53	162	$2\times 3^4$

.

In tri-state architecture, sources in the first leg are obtained in multiples of three, sources in the second leg are considered zero, and the sources in the third leg are obtained by doubling the value of the voltage source used in the first leg. Voltage variation for the first leg, second leg and third leg of each structure are obtained as [3⁰, 3¹, …, 3^k], [0,0,…, 0] and 2 × [3⁰, 3¹, …, 3^k]. Thus, the values of sources are tabulated in Table 7. This procedure is adopted to construct a sinusoidal waveform in the load.

In order to generate a multilevel in the output voltage, it needs the control pulse generation for the switches. Figure 10 shows the block diagram of the generation of pulses, which is achieved by comparing the sinusoidal wave with the constant voltage steps at regular intervals. The switching state will become one when sinusoidal is in between the i^th level and i + 1^th level. For 242 level generation, the value of ‘i’ will be varying from 0 to 242 (i.e., from i^th level to n + 1 level) to construct positive 242 levels, and the same will be repeated for negative. Adder will combine all the switching states created, and it will act as an input to activate the corresponding switching pattern via a multiport switch. De-multiplexer is used for distributing the pulses for the switches in the tri-state inverter.

The laboratory development is carried out for the tri-state inverter and presented in Figure 11. Using the Xilinx Spartan-6 XC6SCX9 controller pulses are generated and given to the Insulated Gate Bipolar Transistor FGA15N120. Triggering signals for the IGBT’s are produced using VHDL language.

The program is developed for a full cycle (0 to 2π), and it is simulated using Modelsim. The program is coded, organized, and transferred to the Spartan-6 XC6SCX9 controller kit using Xilinx. Once the coding is communicated to the controller, the switches will be triggered according to the switching patterns to generate output at load using the input voltage sources.

Both resistive and impendence load with the value of 400 ohms and (400 + j0.314) ohm are tested in experimental development, which is shown in Figure 11a,b.

The output voltages and the current waveforms are obtained satisfactorily from the simulation and experimental design for resistive loads, and they are shown in Figure 12a–d, respectively.

The output voltage and current waveform of the impedance load from the simulation design and experimental development are shown in Figure 13a–d. Both simulation and experimentation are aimed at generating a 50 Hz smooth waveform.

The simulation design and experimental development were tested with resistive and impedance load, which produces a maximum output voltage of 242 V and the maximum current value of 0.605 A, respectively. The waveforms are shown in Figure 12 and Figure 13. The frequency spectrum of the output voltage for the resistive load and impedance load was analyzed using the Fast Fourier Transform, and the harmonic contents for both the loads are obtained as 0.34% and 0.21%, which are shown in Figure 14 and Figure 15, respectively.

Figure 16 shows the maximized view of the output voltage for resistive load measured for a period of 50 microseconds, and the amplitude of the voltage level obtained is at approximately 3 V (i.e., the 2.42 level). This shows that, for a one-quarter cycle (5 milliseconds), the output level generated was equal to 242.

Further, the simulation work was carried out for various resistive loads. For the load 50 ohm and 100 ohms, the output current built at the load terminal was measured as 4.84 A and 2.42 A, respectively. The inverter output current waveforms obtained for the 50 ohm and 100 ohm load resistance are presented in Figure 17 and Figure 18.

Simulation for various impedance loads (50 + j31.4) ohm and (100 + j31.4) ohm are performed. The output voltage and current waveform for (50 + j31.4) ohm load are shown in Figure 19 and Figure 20. By comparing the output voltage and current waveform, it has been inferred that the current waveform is having a phase shift of 32.12° (lag), maintaining a power factor of 0.8468 at the output. The presence of harmonic content at the load voltage is measured as 0.30%, and it is shown in Figure 21.

The output voltage and current waveform for (100 + j31.4) ohm load are shown in Figure 22 and Figure 23. By comparing the output voltage and current waveform, it has been inferred that the current waveform has a phase shift of 17.43° (lag), maintaining a power factor of 0.9541 at the output. The presence of harmonic content at the load voltage is measured as 0.23%, and it is shown in Figure 24.

The proposed inverter was tested for an output frequency of 60 Hz. The simulation work is carried out for 60 Hz, and it is clearly observed from the waveform shown in Figure 25.

3.2. Safe Operation of Proposed Tri-State Inverter

The voltage rating and current rating of the Insulated Gate Bipolar Transistor (FGA15N120) was 1200 V and 15 A, respectively, as per the manufacturer’s specifications. The output voltage and current produced by the 485-level tri-state inverter were ±242 V and 0.605 A, respectively. By comparing the IGBT’s voltage rating and current rating, the output voltage and current produced by the proposed tri-state inverter is less. Thus, the 485-level tri-state inverter’s experimentation works under a safe operating area for the given load conditions.

3.3. Validation of Tri-State Inverter Results with Other MLI’s

The result of the tri-state architecture inverter was compared with other MLI’s in terms of harmonic content present in voltage waveform. The values in

Table 8. Presence of harmonic content in load waveform of various MLI designs.

Reference Number	Load Voltage THD in % (RL Load)
[10]	5.2
[11]	4.63
[16]	3.35
[17]	3.25
[22]	1.63
Tri-state architecture inverter	0.21

are presented from various MLI designs tested with impedance load. From Table 8 and Figure 26, it can be concluded that the presence of harmonic contents in output load voltage is less than the other MLI designs.

4. Conclusions

A new MLI structure was designed using five tri-state architectures to reach 485 voltage levels with 19 controllable switches and ten variable DC sources. This Tri-state architecture is derived from the k-state structure. The proposed tri-state architecture eliminates the repeated usage of voltage sources, thereby facilitating minimum voltage sources to generate maximum voltage levels at the load.

Further, a design procedure is followed to obtain the values of dc sources in the inverter. Design procedure confirms that the values obtained for the voltage sources of j^th tri-state architecture are 0, $3^{j-1}$, $2\times (3^{j-1})$.

A comparative study was carried out with the already existing MLI’s in terms of the number of structures, number of switches, number of sources, and number of voltage levels. From the comparative study, it was found that the proposed structure was capable of generating the highest output voltage level with fewer components.

The proposed inverter’s working was studied and simulated using MATLAB/Simulink R2013a for both resistive load and impedance load. A laboratory setup was developed to study the tri-state inverter’s performance with resistive load and impedance load. Diodes are added in series with controlled switches to gain the blocking capability, and therefore, the results are obtained satisfactorily. The harmonic distortion of the output waveform is obtained from Fast Fourier Transform, and it is given as 0.34% for resistive load and 0.21% for impedance load. The experimental result discussed in this paper proves that the presence of harmonic content is less in the output voltage without filters; thus, this inverter can be implemented in renewable energy systems like solar, fuel cells, etc., with optimal cost. From the above, it is concluded that the proposed tri-state inverter performs better with a simple structure than the other related topologies.