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Article

Low Power QC-LDPC Decoder Based on Token Ring Architecture

Faculty of Automatic Control, Electronics and Computer Science, Silesian University of Technology, ul. Akademicka 16, 44-100 Gliwice, Poland
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Energies 2020, 13(23), 6310; https://doi.org/10.3390/en13236310
Received: 5 November 2020 / Revised: 24 November 2020 / Accepted: 26 November 2020 / Published: 30 November 2020
The article presents an implementation of a low power Quasi-Cyclic Low-Density Parity-Check (QC-LDPC) decoder in a Field Programmable Gate Array (FPGA) device. The proposed solution is oriented to a reduction in dynamic energy consumption. The key research concepts present an effective technology mapping of a QC-LDPC decoder to an LUT-based FPGA with many limitations. The proposed decoder architecture uses a distributed control system and a Token Ring processing scheme. This idea helps limit the clock skew problem and is oriented to clock gating, a well-established concept for power optimization. Then the clock gating of the decoder building blocks allows for a significant reduction in energy consumption without deterioration in other parameters of the decoder, particularly its error correction performance. We also provide experimental results for decoder implementations with different QC-LDPC codes, indicating important characteristics of the code parity check matrix, for which an energy-saving QC-LDPC decoder with the proposed architecture can be designed. The experiments are based on implementations in the Intel Cyclone V FPGA device. Finally, the presented architecture is compared with the other solutions from the literature. View Full-Text
Keywords: LDPC; QC-LDPC; FPGA; Min-Sum; distributed control system; token ring; partially-parallel decoder LDPC; QC-LDPC; FPGA; Min-Sum; distributed control system; token ring; partially-parallel decoder
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MDPI and ACS Style

Kuc, M.; Sułek, W.; Kania, D. Low Power QC-LDPC Decoder Based on Token Ring Architecture. Energies 2020, 13, 6310. https://doi.org/10.3390/en13236310

AMA Style

Kuc M, Sułek W, Kania D. Low Power QC-LDPC Decoder Based on Token Ring Architecture. Energies. 2020; 13(23):6310. https://doi.org/10.3390/en13236310

Chicago/Turabian Style

Kuc, Mateusz, Wojciech Sułek, and Dariusz Kania. 2020. "Low Power QC-LDPC Decoder Based on Token Ring Architecture" Energies 13, no. 23: 6310. https://doi.org/10.3390/en13236310

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