# Quasi-3D Thermal Simulation of Integrated Circuit Systems in Packages

^{1}

^{2}

^{*}

## Abstract

**:**

_{MAX}determination for different types of packages was not more than 10–20%.

## 1. Introduction

## 2. State of the Art

#### 2.1. BGA Packages

#### 2.2. 3D-IC-TSV Packages

_{2}. A numerical solution for the simplified model was used to analyze the role of TSVs in heat dissipation.

#### 2.3. Embedded Die Packages

## 3. Quasi-3D Numerical Model of IC Packages

_{X}, L

_{Y}≫ L

_{Z}. Due to this, the 3D problem can be reduced to a system of 2D equations on the horizontal surfaces of the layers [10].

_{1}(x,y), on the surfaces of the package inner layers T

_{ξ}(x,y), ξ = 2, …, N, and on the surface of the PCB T

_{N}

_{+1}(x,y). These equations have the following form:

- convective heat transfer occurs on the top surface of the package$$\frac{\partial}{\partial x}\left[{\lambda}_{1}(x,y)\frac{\partial {T}_{1}}{\partial x}\right]+\frac{\partial}{\partial y}\left[{\lambda}_{1}(x,y)\frac{\partial {T}_{1}}{\partial y}\right]+\alpha \left({T}_{AMB}-{T}_{1}\right)+{\lambda}_{1}(x,y)\frac{{T}_{2}-{T}_{1}}{{Z}_{1}}=0,$$
- for inner layers$$\begin{array}{c}\frac{\partial}{\partial x}\left[{\lambda}_{\xi}(x,y)\frac{\partial {T}_{\xi}}{\partial x}\right]+\frac{\partial}{\partial y}\left[{\lambda}_{\xi}(x,y)\frac{\partial {T}_{\xi}}{\partial y}\right]+{\lambda}_{\xi -1}(x,y)\frac{{T}_{\xi -1}-{T}_{\xi}}{{Z}_{\xi -1}}+{\lambda}_{\xi}(x,y)\frac{{T}_{\xi +1}-{T}_{\xi}}{{Z}_{\xi}}=\\ \begin{array}{cc}=\{\begin{array}{ccccccc}-P(x,y),& for& active& layers& with& power& source\\ 0,& for& passive& layers& & & \end{array},& \xi =2,\dots ,N.\end{array}\end{array}$$
_{ξ}(x,y) is the layer temperature; T_{AMB}is the ambient temperature; P is the power density on die surface; α is the convective heat transfer coefficient; λ_{ξ}and z_{ξ}are the thermal conductivity coefficient and thickness of the package structural layer ξ = 1,2, …, N; N is the quantity of package layers X_{S}Y_{S}package horizontal sizes.

_{N}

_{+1}(x,y) ≡ T

_{AMB}, or other heat exchange conditions are established, for example, a coefficient of convective heat exchange can be set.

- Package structural parameters, i.e., the number of layers, type of layer, sizes, and physical parameters of the layer;
- The powers or power densities of the active dies;
- Computational parameters, i.e., difference network sizes M
_{X}× M_{Y}and accuracy of computations.

- Temperature arrays in network nodes for each layer T
_{ξ}(i,j), ξ = 1,2, …, N; - The temperature distribution plots T
_{ξ}(i,j) in the x,y plane; - Average T
_{AV}and maximal T_{MAX}values of layer temperatures.

## 4. Simulation Results

#### 4.1. Stacked IC-TSV-BGA Module

_{PCB}= T

_{AMB}, neglecting the heat flow caused by a free convection.

_{MAX}= 145 °C observed at the surface of the middle die in Figure 6b is critical because it is very close to that established for the semiconductor ICs’ upper limit of 150 °C. The thermal regime of the middle die must be improved to decrease T

_{MAX}.

_{MAX}of interposer is about 106 °C, which means that stress and degradation of TSVs cannot appear.

#### 4.2. Multi-Chip Stack Embedding Package

^{2}total area is shown. The analogous pictures are shown in Figure 9 for the two-layer package with 38 × 20 mm

^{2}area, and in Figure 10 for the three-layer package with 20 × 20 mm

^{2}area. The power of each die is 10 W.

_{MAX}increase of the active dies, i.e., 44, 55, and 72 °C for the constructions, presented in Figure 8, Figure 9 and Figure 10 accordingly. The largest value of 72 °C for the structure, shown in Figure 10, correlates well with the experimental value of 85 °C taken for the embedded die module reliability testing in [11,27].

## 5. Validation of the Q3D Model

_{JC}) and junction to board (Θ

_{JB}), for different types of packages.

#### 5.1. Comparison with Results Obtained Using Standard Fully-3D FEM Simulators

_{AMB}= 85 °C [11]. The maximal difference in internal module temperature distributions obtained by two different tools in the range + 85–130 °C was not more than 5–6 °C.

#### 5.2. Comparison with Measured Thermal Resistances for Different Types of Packages

#### 5.2.1. The Standard BGA Package

^{2}BGA package was used with 8.2 × 8.2 mm

^{2}die, three-row peripheral ball array, 156 perimeter balls, 16 central thermal balls; the chip power dissipation was 1 W [26]. The comparison of the measured and simulated results for thermal resistance junction to ambient Θ

_{JA}is shown in Table 3, showing that good agreement was achieved.

#### 5.2.2. UltraScale FPBGA Package

_{JB}and Θ

_{JC}of the package FSGD2104, which is used for field-programmable gate arrays (FPGA) [26] are presented in Table 4.

#### 5.3. High-Performance Flip-Chip BGA (HP-fcBGA)

_{JA}with this resistance simulated using our software Overheat-3D-IC. It is seen in Figure 14 that our simulation results are in good agreement with this experiment.

## 6. Conclusions

- (a)
- 3D integration of ICs and board;
- (b)
- Large number of thinned layers of different materials;
- (c)
- Vertical z-axes interconnections.

_{MAX}determination was not more than 10%.

_{JA}, Θ

_{JB}, Θ

_{JC}, and maximal temperature T

_{MAX}were compared for different types of packages. The simulation error was 10–20%.

## Author Contributions

## Funding

## Conflicts of Interest

## References

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**Figure 1.**Extra performance ball grid array (XP-BGA) package. 1, active die; 2, die attach 1; 3, die attach 2; 4 dummy spacer die, stacked gap; 5, heat spreader attach; and 6, heat spreader.

**Figure 2.**Package-on-package (PoP) structure. 1, solder balls; 2, laminate; 3, dies; 4, stacked gap; 5, laminate; and 6, mold cap.

**Figure 4.**Embedded die package. 1, Embedded die; 2 BGA die; 3, passive components, 4, polyimide; 5, adhesive; 6, copper; and 7, conductive paste.

**Figure 5.**Geometrical model of the 3D structure of stacked silicon interconnection module. Planes: 1, package top; 2, bottom of package lid; 3, top of dies; 4, bottom of dies; 5, top of passive silicon interposer; 6, bottom of passive silicon interposer; 7, top of substrate; 8, bottom of substrate; 9, surface of PCB; 10, BGA balls; 11, package substrate; 12, C4 bumps; 13, passive silicon interposer; 14, microbumps; 15,16, and 17, active dies; and 18, lid of package.

**Figure 6.**Distribution of temperature in the structure of stacked IC-TSV-BGA module [16]. (

**a**) Cross-section of the structure. L, the line of the vertical temperature distribution diagram, see Figure 7; (

**b**) Temperature on the active surface of dies, isotherms, °C; (

**c**) Temperature on the top surface of interposer, isotherms, °C. 1, active die with power 4 W; 2, active die with power 8 W; and 3, active die with power 8 W.

**Figure 8.**Thermal mode of chips located in a single-layer package. (

**a**) Cross-section of the structure; (

**b**) Vertical temperature distribution along the line L; (

**c**) Temperature distribution on the active surface of the dies. 1, dies flip-chip; 2, solder balls; 3, substrate-polyimide; 4, vias; and 5, PCB.

**Figure 9.**Thermal mode of chips located in a two-layer package. (

**a**) Cross-section of the structure; (

**b**) Vertical temperature distribution along the line L; (

**c**) Temperature distribution on the active surface of the die lying on the package. 1, upper die flip-chip; 2, lower dies flip-ship; 3, polyimide; 4, adhesive; 5, vias; 6, balls; and 7, PCB.

**Figure 10.**Thermal mode of chips located in a three-layer package. (

**a**) Cross-section of the structure; (

**b**) Vertical temperature distribution along the line L; (

**c**) Temperature distribution on the active surface of the die lying on the package. 1, upper die flip-chip; 2, middle die flip-chip; 3, lower die flip-chip; 4, solder balls; 5, vias; 6, polyimide; 7, adhesive; and 8, PCB.

**Figure 11.**(

**a**) Three-layer TSV stack model built using COMSOL 4.1 software; 1, TSVs; 2, solder balls; 3, heat sink; and 4, substrate. (

**b**) Die surface; 5, 2 × 2 matrices of power grids.

**Figure 12.**The 3D view of steady-state temperature distribution for three-layer chip with TSVs; 1, upper silicon layer; 2, central silicon layer; 3, bottom silicon layer.

**Figure 13.**The temperature distributions simulated using Overheat-3D-IC. (

**a**) On the upper silicon layer; (

**b**) On the bottom silicon layer.

**Figure 14.**(

**a**) High-performance flip-chip BGA (HP-fcBGA) structure; (

**b**) Thermal resistance junction to ambient Θ

_{JA}. 1, measured; 2, simulated by FloTHERM; and 3, simulated by Overheat-3D-IC.

Material | Constructive Element | Thermal Conductivity, K/W |
---|---|---|

Silicon | die, interposer | 150 |

Solder | balls | 50 |

Ceramic | substrate | 0.377 |

Polyimide | constructive layers | 100 |

Copper | via | 385 |

Molding | constructive layers | 0.6 |

Covar | lid | 17 |

Temperature, °C | COMSOL [14] | Overheat-3D-IC (This Work) | Difference | |
---|---|---|---|---|

In °C | In % | |||

T_{MAX} for bottom layer in Figure 8a | 82 | 78.2 | 3.8 | 4.4 |

T_{MAX} for upper layer in Figure 8a | 76 | 73.4 | 2.6 | 3.4 |

Θ_{JA}, K/W | Average Temperature of Die, °C | |
---|---|---|

Measurement [26] | 23.3 | 41.6 |

Q3D model | 23.9 | 40.8 |

Thermal Resistance, K/W | Value from the Reference [29] | Calculated by Q3D Model |
---|---|---|

Θ_{JB} | 0.004 | 0.005 |

Θ_{JC} | 0.219 … 0.292 | 0.246 |

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## Share and Cite

**MDPI and ACS Style**

Petrosyants, K.O.; Ryabov, N.I.
Quasi-3D Thermal Simulation of Integrated Circuit Systems in Packages. *Energies* **2020**, *13*, 3054.
https://doi.org/10.3390/en13123054

**AMA Style**

Petrosyants KO, Ryabov NI.
Quasi-3D Thermal Simulation of Integrated Circuit Systems in Packages. *Energies*. 2020; 13(12):3054.
https://doi.org/10.3390/en13123054

**Chicago/Turabian Style**

Petrosyants, Konstantin O., and Nikita I. Ryabov.
2020. "Quasi-3D Thermal Simulation of Integrated Circuit Systems in Packages" *Energies* 13, no. 12: 3054.
https://doi.org/10.3390/en13123054