Seven-Level Active Power Filter Based on a Novel H-Bridge Power Topology Structure

Abstract

This paper proposes a novel seven-level power topology, that increases the number of output levels by using fewer power switches and capacitors compared to the traditional seven-level topology. Moreover, the working mechanism of the proposed topology and its implementation method are given. Furthermore, a two-stage capacitor-voltage equalization control strategy with overall control and independent control is proposed. Finally, the proposed topology is applied to the active power filter system, and simulations and experimental research of two types of working conditions are performed. The results verify the effectiveness and feasibility of the new topology and control strategy.

1. Introduction

Active power filters (APFs) are considered the best way to improve the power quality of the power supply systems because of their rapid compensation capacity and high precision [1,2,3,4]. It is difficult to apply the traditional two-level APF to high-voltage and high-power situations due to the voltage and power limitations of power switches [5]. The multilevel converter has attracted wide attention due to its low harmonic content (THD) and low electromagnetic interference (EMI) [6,7,8,9]. At present, the research on multilevel converters mainly focuses on optimizing topology and control algorithms [10,11,12,13,14].

There are three types of mature multilevel topologies; namely neutral point clamped (NPC), flying capacitor (FC), and cascade H-bridge (CHB) multilevel converters [15,16]. NPC and FC can significantly increase the number of power switches and DC capacitors if the number of output levels increases [17]. CHB topology can be divided into symmetric and asymmetric structures. The advantage of the symmetric topology is that the withstand voltage of the power switches can be reduced, while the disadvantage is that there are many power switches and capacitors [18]. Compared to the symmetric structure, the asymmetric structure can reduce the number of power switches to achieve the same multilevel output [19], but the key point to this topology is how to generate uniform output levels, reduce the harmonic content of the output voltage, and simplify the voltage-equalization control strategy [20,21,22,23].

For the control algorithm optimization, the main problem is the capacitor-voltage equalization; the current solution is to use the carrier phase shifted sinusoidal pulse width modulation (CPS-SPWM) to adjust the transmission power of each unit by fine-tuning the amplitude and phase of the modulated wave of each H-bridge unit [24,25]. The disadvantage of this method is that when the modulated wave of each unit is adjusted, the lower harmonics in the phase voltage cannot be eliminated, which results in the distortion of the output voltage waveform [26]. In contrast to the power distribution technology based on the CPS-SPWM, in the literature [27,28], the modulation technology of the carrier disposition and carrier rotation is proposed to realize multilevel output, and the power balancing distribution of each element is also realized. However, the power-balance control strategy is not given. In addition, methods based on step-wave modulation technology, multi-frequency power allocation, etc. have been proposed, but there are some limitations in terms of harmonic performance, implementation difficulty, and power balance distribution, etc. [29,30].

This paper proposes a novel seven-level power topology. Compared to other traditional seven-level topologies, it can reduce the number of power switches and capacitors, increase the number of output levels, and reduce the harmonic content of the output voltage and the complexity of the system. This paper deeply analyzes the working mechanism of the novel power topology and gives the engineering realization of the proposed topology. At the same time, an equalization control strategy with overall control and independent control of two-stage capacitor voltage is proposed to solve the problem of the capacitor-voltage imbalance in applications. Finally, the novel topology is applied to the three-phase APF system, and the harmonic suppression control strategy and cell capacitor-voltage regulation are proposed. The simulation and experimental work are carried out under different working modes, and the results verify the correctness and feasibility of the proposed novel topology and control strategy.

2. Analysis of the Novel Seven-Level Topology

2.1. The Structure and Working Mechanism of the Novel Seven-Level H-Bridge Topology

Figure 1 shows the main circuit of a novel seven-level APF. The three-phase units have the same structure; A phase contains six power switches S_a1–S_a6 and two capacitors C_a1 and C_a2 which are called the seven-level H-bridge topology. As can be seen from the dotted box in Figure 1, when S_a1, S_a2 (or S_a3, S_a4) are simultaneously turned on, C_a1 (or C_a2) is short-circuited, so S_a1, S_a2 (or S_a3, S_a4) must work in a complementary state. In addition, when S_a5 and S_a6 are simultaneously turned on, C_a1 and C_a2 are also short-circuited, so S_a5 and S_a6 also work in a complementary state. As can be seen from

Table 1. Switching states of the seven-level topology.

Switch Status			Output Level
Sa1,Sa2	Sa3,Sa4	Sa5,Sa6
1,0	1,0	0,1	+(V1 + V2)
1,0	0,1	0,1	+V1
0,1	1,0	0,1	+V2
1,0 or 0,1	1,0 or 0,1	1,0 or 0,1	0
1,0	0,1	1,0	−V2
0,1	1,0	1,0	−V1
0,1	0,1	1,0	−(V1 + V2)

, the novel topology has seven working states. Among them, S_a5 and S_a6 work at low frequency, which is consistent with the modulation wave frequency. The switching frequency of S_a1 and S_a2 is half of S_a3 and S_a4. V₁ and V₂ are the voltages of C_a1 and C_a2, respectively, V₁ = 2V₂. Inductors L_A, L_B, and L_C connect the converter to the power grid, balance the voltage difference between the grid and the converter output, and perform reactive compensation or harmonic suppression.

2.2. Comparison with Other Seven-Level Structures

Table 2. Seven-level topology comparison.

	Structure	Diode Clamp	Cascading H-Bridge	New Topology
Category
Topology
Number of single-phase power switches		12	12	6
Number of single-phase capacitors		6	3	2

shows the comparison of the novel topology with the traditional diode-clamped and cascaded seven-level converters, in which the number of power switches per phase is 6, 12, and 12, and the number of capacitors is 2, 6, and 3, respectively. It can be seen that the structure of the novel topology is simple, and reduces the system volume. At the same time, considering the withstand voltage limit, the novel topology is suitable for medium-voltage and low-voltage situations.

3. APF Control Method Based on Novel Topology Structure

3.1. Overall Control Strategy of the System

Figure 2 shows the diagram of the overall control structure of the novel APF system, including the harmonic current control unit and the capacitor-voltage stage control unit. In the harmonic current control unit, the output u_f could be obtained based on the ip–iq current detection method and quasi-proportional resonance (PR), repetitive control strategy. Considering that the imbalance of the capacitor voltage is caused by switch loss and drive pulse delay, the inverter output voltage is distorted, so the capacitor voltage must be regulated. Figure 2 shows the capacitor-voltage stage control unit, which uses a two-stage capacitor-voltage control strategy with overall control and independent control to obtain two-stage outputs u_1f and u_2f. Finally, the harmonic current control and the capacitor-voltage stage control are combined to obtain u_a, u_b, and u_c. The carrier disposition is modulated to generate a pulse-width-modulated (PWM) signal, and the power amplifier drives the power switches to achieve harmonic suppression and capacitor-voltage regulation. The following cases, without loss of generality, are illustrated with the A phase as an example.

3.2. First-Stage Control Strategy of the Capacitor Voltage

The first stage is the overall control of capacitor C_a1 and C_a2, as shown in Figure 3a. Proportional integral regulator (PI) adjustment is performed for the sum of the given capacitor-voltage (V_ref1 + V_ref2) and the sum of the actual capacitor-voltage (V_a1 + V_a2). Its output is multiplied by the unit sine of the A-phase grid voltage to obtain the modulated wave u_1af to realize the overall voltage control of the A-phase units C_a1 and C_a2, and obtain V_ref1 + V_ref2 = V_a1 + V_a2.

3.3. Second-Stage Control Strategy of the Capacitor Voltage

The second stage is the independent control of capacitors C_a1 and C_a2, as shown in Figure 3b, which consists of the determination of charge and discharge status and the control strategy of charge and discharge; sgn (i_A) is the symbol function of i_A.

3.3.1. Determination of Charge and Discharge Status

Figure 4 shows the operating state of the unit circuit when C_a1 and C_a2 in the A-phase are charged and discharged, where i_A is the output current.

Table 3. State determination of C_a1, C_a2 charge and discharge.

	Current	iA > 0	iA < 0
Output Level
7: V1 + V2		-	-
6: V1		Ca1 discharge, Ca2 suspend	Ca1 charge, Ca2 suspend
5: V2		Ca1 suspend, Ca2 discharge	Ca1 suspend, Ca2 charge
4: 0		-	-
3: −V2		Ca1 suspend, Ca2 charge	Ca1 suspend, Ca2 discharge
2: −V1		Ca1 charge, Ca2 suspend	Ca1 discharge, Ca2 suspend
1: −(V1 + V2)		-	-

gives the charge and discharge status of C_a1 and C_a2. First, the charge and discharge status of C_a1 and C_a2 are judged by the unit output status and the direction of i_A. When the status is 1 or 7 (Table 3), if the charge and discharge of C_a1 and C_a2 are carried out, the output of the unit will change. At the same time, considering that C_a1 and C_a2 are suspended at state 4, the charge and discharge are not adjusted under these three conditions.

3.3.2. Control Strategy of Charge and Discharge

Figure 3b shows the charge and discharge control of C_a1 and C_a2. The actual voltage V_a1, V_a2 and the reference voltage V_ref1, V_ref2 are, respectively subjected to PI adjustment to obtain Δ1, Δ2, and U_2af could be obtained after synthesis. Figure 5 shows a schematic diagram of the seven-level phase capacitor-voltage adjustment. The six-layer carriers output seven level states, which are defined as levels 1–7 from low to high. According to the carrier-disposition modulation principle, when the modulated wave is located in area 1 or 2, it outputs six levels (corresponding to V₁ in Table 3). If the actual capacitor-voltage V_a1 is greater than the reference voltage V_ref1, reduction in the V_a1 output could be achieved by increasing the discharging time of C_a1 or shortening the charging time of C_a1. When C_a1 is in a discharged state, if the modulated wave is compared with carrier 6 at that moment, the output is level 6 or level 7, if the amplitude of the modulated wave is decreased, and the output time of level 6 could be increased accordingly, that is, the discharge time of C_a1 is increased. Similarly, when C_a1 is in the charge state, the charging time of C_a1 could be reduced by changing the amplitude of the modulated wave. The voltage adjustment of C_a2 is the same as that of C_a1. It can be seen that the capacitor-voltage stabilization can be achieved by changing the amplitude of the modulated wave.

3.4. Parameter Calculation of Passive Elements

The larger the connected inductance value of APF is, the smaller the current ripple, but the smaller the rate of change of the compensation currens, and the weaker the current tracking ability. Secondly, the compensation current should be able to track the maximum rate of change of the command current. The smaller the inductance value is, the higher the rate of change of the current, and the faster the dynamic response speed of APF. However, the more drastic the current change is, the larger the ripple of the current. The DC side capacitor provides a stable DC power supply for the APF. The larger the capacitance, the more stable the DC side voltage. As the capacitor capacity increases, the volume and cost of the capacitor also increases.

3.4.1. Parameter Calculation of Connected Inductor

a. Inductance parameter selection based on ripple constraint condition

The equivalent circuit of the APF device is shown in Figure 6, we can get:

$$u-e=L\frac{d{i}_c}{dt}$$

(1)

where u is the AC side voltage of the inverter, e is the grid side voltage, L is the connection inductance, and i_c is the compensation current.

In the process of the harmonic current compensation of APF, high-frequency harmonic components exist in the output of the AC side, which generates a ripple current under the action of inductance, and the ripple is the largest at the peak of the output current. Figure 7 shows, in a multilevel inverter, NU_dc and (N–1)U_dc levels are included at the peak output current of thr AC side. It is assumed that the high-level duration of NU_dc is t₁ and the low-level duration of (N–1)U_dc is t₂ in a switching period Ts, when the output current is at the peak, applying u = NU_dc, di_c/d_t = Δi_c/T_c into Equation (1), we can get:

$$\{\begin{array}{l}N{U}_{dc}-e=L\frac{\Delta i_1}{t_1}\\ e-(N-1)U_{dc}=L\frac{\Delta i_2}{t_2}\end{array}$$

(2)

When the output current is at the peak, it satisfies Δi₁ = Δi₂, t₁ + t₂ = T_s. Applying them into Equation (1):

$$t_1=\frac{e-(N-1)U_{dc}}{U_{dc}}{T}_s$$

(3)

$$\Delta i_1=\frac{(N{U}_{dc}-e)\left[e-(N-1)U_{dc}\right]}{L{U}_{dc}}{T}_s$$

(4)

$$L=\frac{(N{U}_{dc}-e)\left[e-(N-1)U_{dc}\right]}{\Delta i_1{U}_{dc}}{T}_s$$

(5)

It can be seen from Equation (4) that increasing the connected inductance L can reduce the ripple current Δi₁. In practical engineering, the ripple current usually takes 5% of the compensation current peak value. Thus, the lower limit of connection inductance could be obtained:

$$L\ge \frac{(N{U}_{dc}-e)\left[e-(N-1)U_{dc}\right]}{\Delta i_{\max }{U}_{dc}}{T}_s$$

(6)

In the Equation (6), f_s = 20 kHz, N = 3, U_dc = 130 V, e = 311 V, we can get:

$$L\ge 1.55\mathrm{mH}$$

(7)

b. Inductance parameter selection based on the tracking ability of the compensation current at zero crossing

During one cycle of the command current, it changes the fastest at zero-crossing point (wt = 0), and the upper limit of the connected inductance could be determined according to the rate of change of the command current at zero. The current tracking waveform is shown in Figure 8. Δi₁ and Δi₂ are the current increments across the connected inductor during t₁ and t₂, and T_S is a PWM switching cycle.

$$U_{dc}-e=L\frac{\Delta i_1}{t_1}$$

(8)

$$e-0=L\frac{\Delta i_2}{t_2}$$

(9)

It can be seen from Equations (8) and (9) that the current has a maximum rate of change at the current zero-crossing point. When t₁ = T_S, t₂ = 0, Δi₂ = 0, Δi₁ = Δi, e = 0, we can get:

$${\frac{d(I_m\sin \omega t)}{dt}|}_{t=0}={I_m\omega \cos \omega t|}_{t=0}=\omega I_m$$

(10)

$$\frac{U_{dc}}{L_{\max }}=\omega I_m$$

(11)

where I_m is the current peak, we can get:

$$L_{\max }\le \frac{U_{dc}}{\omega I_m}$$

(12)

where U_dc = 130 V, I_m = 28.28 A, f = 50 Hz, w = 2πf, we can get:

$$L\le 14.6\mathrm{mH}$$

(13)

According to Equations (7) and (13), the value of the connected inductor L_A, L_B, and L_C could be selected as 3 mH.

3.4.2. Parameter Calculation of Capacitor

The main considerations for the DC-side capacitors are: switching frequency f_s, average value of DC bus voltage U_dcavg, DC bus voltage ripple rate γ_v, and current peak I_m.

The DC bus voltage ripple rate γ_v could be expressed as:

$${\gamma }_v=\frac{U_{dc\max }-U_{dcavg}}{U_{dcavg}}=\frac{U_{dcavg}-U_{dc\min }}{U_{dcavg}}$$

(14)

where U_dcmax and U_dcmin are the maximum value and the minimum value of the DC bus voltage, respectively.

From Equation (14), we can get:

$$U_{dc\max }=(1+{\gamma }_v)U_{dcavg}$$

(15)

$$U_{dc\min }=(1-{\gamma }_v)U_{dcavg}$$

(16)

Since Q = it, Q = CU, there is:

$$\Delta U_{dc\max }=U_{dc\max }-U_{dcavg}={\gamma }_v{U}_{dcavg}=\frac{\Delta Q}{C}=\frac{1}{C}{T}_s{I}_m$$

(17)

According to Equation (17), it could be inferred that the DC side capacitor C is:

$$C=\frac{1}{{\gamma }_v{U}_{dcavg}}{T}_s{I}_m=\frac{1}{{\gamma }_v{U}_{dcavg}{f}_s}{I}_m$$

(18)

where γ_v is 0.9%, f_s is 20 kHz, U_dcavg is 390 V, I_m is 28.28 A, then C = 403 uF, the value of the capacitor C_a1 and C_a2 could be selected as 1000 uF.

4. System Simulation and Result Analysis

In order to verify the correctness and feasibility of the proposed topology, voltage-balance control strategy, and its application in the APF system, the following simulation is conducted. The parameters of the simulation are as follows: the voltage of the capacitor C_a1 U_d1 is 260 V, the voltage of the capacitor C_a2 U_d2 is 130 V, the grid frequency f is 50 Hz, he switching frequency f_s is 20 kHz, and the inductance L is 3 mH.

4.1. Under the Conditions of Balanced Grid and Load

The grid voltages U_A, U_B, and U_C, are all 220 V, and the rectifier bridge is followed by the resistance of 40 Ω. Figure 9 and Figure 10 show the gird current in the A-phase and its THD before and after compensation, where the THD decreases from 24.03% to 1.10%. As shown in Figure 10a, before 0.3 s, the system load is a three-phase rectifier bridge with a resistance of 40 Ω, at 0.3 s, a resistance of 40 Ω is connected in parallel, and after 0.35 s, the load is changed to 40 Ω. It can be seen that in the case of a sudden change of load, the grid current fluctuates slightly, and tracks the reference input quickly, the voltage fluctuation is small, and there is no mutation substantially. Figure 11 shows the voltage of each capacitor, the fluctuation does not exceed 1 V, and it also shows the unit output, which is seven levels.

4.2. Under the Conditions of Unbalanced Grid and Load

The grid phase voltages U_A, U_B, and U_C, are 220 V, 180 V, and 180 V, respectively. A single-phase rectifier load with a resistance of 10 Ω is connected between the A-phase and the B-phase, and the three-phase rectifier bridge is followed by a resistance of 40 Ω. Figure 12 and Figure 13 show the grid current and its current THD before and after compensation. It can be seen that the THD decreases from 20.98% to 1.89%, and the compensation effect is obvious. As shown in Figure 13a, before 0.3 s, the system load is a three-phase rectifier bridge with a resistance of 40 Ω, at 0.3 s, a resistance of 40 Ω is connected in parallel, and after 0.35 s, the load is changed to 40 Ω. It can be seen that in the case of a sudden change in system load, the grid current fluctuates slightly, and track the reference input quickly, the voltage fluctuation is small, and there is no substantial mutation. Figure 14 shows the voltage waveforms of each capacitor, which enter the steady-state at 0.05 s, and the fluctuation does not exceed 1 V, and it also shows the unit output of the novel power topology, which is seven levels.

5. Experiment and Result Analysis

In order to verify the correctness and feasibility of the proposed topology, the voltage-balance control strategy, and its application in the APF system, the following experiment is conducted.

Table 4. Main parameters of the system.

System Parameters	Values
The voltage of capacitor Ca1	260 V
The voltage of capacitor Ca2	130 V
The capacitor Ca1	1000 uF
The capacitor Ca2	1000 uF
The switching frequency fs	20 kHz
The grid frequency f	50 Hz
The inductor LA, LB, LC	3 mH
The balanced grid phase voltages UA, UB, UC	220 V
The balanced resistance load R	40 Ω
The unbalanced grid phase voltages UA, UB, UC	220 V, 180 V, 180 V
A single-phase rectifier load RAB	10 Ω

shows the parameters of the experiment, and the experiment system platform is shown in Figure 15.

5.1. Under the Conditions of Balanced Grid and Load

The grid phase voltages U_A, U_B, and U_C, are all 220 V, and the rectifier bridge is followed by the resistance of 40 Ω. Figure 16 and Figure 17 show the grid current waveforms of the A-phase and its THD before and after compensation, where the phase current THD is reduced from 29.49% to 2.79%, and the compensation effect is obvious. At the same time, the dynamic compensation performance of the system was studied. The rectifier was connected with a 40 Ω resistance load, then a 40 Ω load resistance was connected in parallel, and finally removed. It can be seen from Figure 17a that U_a1 and U_a2 are stable at a reference value, and the system has good dynamic compensation performance if the power grid and load are all balanced, and it also shows the unit output of the novel power topology, which is seven levels.

5.2. Under the Conditions of Unbalanced Grid and Load

The grid phase voltages U_A, U_B, and U_C are 220 V, 180 V, and 180 V, respectively. A single-phase rectifier load with a resistance of 10 Ω is connected between A phase and B phase, and the three-phase rectifier bridge is followed by a resistance of 40 Ω. Figure 18 and Figure 19 show the grid current and its current THD before and after compensation. It can be seen that the THD decreases from 30.24% to 3.13%, and the compensation effect is obvious. At the same time, the dynamic compensation performance of the system was studied. The rectifier was connected with a 40 Ω resistance load; then a 40 Ω load resistance is connected in parallel, and finally removed. It can be seen from Figure 19a that U_a1 and U_a2 are stable at a reference value, and the system has a good dynamic compensation performance if the power grid and load are all balanced, and it also shows the unit output of the novel power topology, which is seven levels.

6. Conclusions

This paper proposes a novel seven-level power topology. Compared to the novel seven-level topology, each power switch in a traditional two-level topology withstands the total DC bus voltage, while some power switches in the novel seven-level topology only withstand one-third of the total DC bus voltage; therefore, the novel seven-level topology has large power capacity, and reduces the withstand voltage of the power switches. The novel seven-level topology makes the output waveform closer to a sine wave by increasing the number of output levels and thereby improves the quality of the output waveform. According to the simulation and experimental results in this paper, the compensated grid current THD with the seven-level APF is only 1%–3%, much lower than the traditional two-level and three-level APF whose compensated grid current THD is usually greater than 5%, and the harmonic suppression effect is obvious. Compared to other seven-level topologies, the novel seven-level topology reduces the number of power switches and capacitors; thus reducing the size and cost of the device. Through the in-depth analysis of the working mechanism of the proposed topology, the engineering realization of the seven-level output is given. Besides, for the problem of capacitor-voltage imbalance in the application, an equalization control strategy with overall control and independent control of the two-stage capacitor voltage is proposed. In addition, the passive elements have been selected based on detailed mathematical analysis. Finally, from the above simulation and experimental work, we can see that the voltage control strategy described in this paper can achieve better cell capacitor-voltage regulation and the three-phase APF can achieve better compensation effect.