Digital Control of a Buck Converter Based on Input-Output Linearization. An Interpretation Using Discrete-Time Sliding Control Theory

Abstract

This paper presents the analysis and design of a PWM nonlinear digital control of a buck converter based on input-output linearization. The control employs a discrete-time bilinear model of the power converter for continuous conduction mode operation (CCM) to create an internal current control loop wherein the inductor current error with respect to its reference decreases to zero in geometric progression. This internal loop is as a constant frequency discrete-time sliding mode control loop with a parameter that allows adjusting how fast the error is driven to zero. Subsequently, an outer voltage loop designed by linear techniques provides the reference of the inner current loop to regulate the converter output voltage. The two-loop control offers a fast transient response and a high regulation degree of the output voltage in front of reference changes and disturbances in the input voltage and output load. The experimental results are in good agreement with both theoretical predictions and PSIM simulations.

1. Introduction

Since breaking into the regulation of dc-dc switching converters at the end of the 1990s, the digital control has undergone successive phases of expansion and stagnation. Destined to be a new standard for the switching converters at the moment of its appearance, the reality, however, has shown that its adoption by the industry has been so far practically inexistent. Despite the inherent advantages of the digital control such as insensitivity to noise, design reuse and reprogram capability, the user’s mistrust, on the one hand, and the difficulty of design, on the other hand, have contributed to this absence of industrial penetration [1].

From the user’s perspective, adopting a new technology more expensive than the present one and not working so well in terms of accuracy in steady-state and dynamic performance was a risk that the manufacturers did not want to take. Time-delay and numerical limit cycles are intrinsic drawbacks associated with the digital design that eventually degrade the controller’s response. The time-delay problem is introduced mainly by the analog-to-digital converter in the cycle by cycle realization of the sampling/conversion process [2,3], which provokes a controller’s delayed reaction of one switching cycle. To mitigate this problem, the sampling/conversion process is performed at large sampling rates up to 32 times the switching frequency [4,5] and small quantization steps are often employed, which results in an increasing of cost, hardware complexity and consumption of the controller. The limit cycle issue is caused by the digital pulse width modulator and the quantization error of the analog-to-digital converter, this yielding an oscillation in the converter output voltage [6].

From the designer’s point of view, the realization of the digital controller is less intuitive than the corresponding analog implementation. In addition to this fact, it has to be pointed out that the first designs required silicon areas considerably bigger than those needed presently and their power consumption was significantly larger than that of their corresponding analog counterparts. However, the exponential decrease of cost and size of digital circuits, which in the period elapsed since 1998 has dramatically incremented the capacity of integrating electronic functions, has revived the idea of digital control as the definitive substitute of the analog equivalent in dc-dc switching converters. This idea is being supported by the fact that recent digital research has been focused on non-realizable aspects in the analog domain such as integrating communications, controller’s self-tuning, converter’s efficiency monitoring and complex nonlinear control techniques implementation. An example of this are the works reported in [5,7], where the dynamic response to perturbations in the power converter is improved by a specific nonlinear control with self-tuning and the overall performance is ameliorated by the action of an active efficiency monitoring system. Other contributions have dealt with new modulation schemes [8] to optimize the converter’s efficiency and extend its input range. Some recent reports are also found when testing new complex control strategies either deterministic [9] or random modulation-based [10], and in introducing new on-line self-tuning protocols [11].

Most digital control realizations are of hybrid type, which means that they combine the action of a nonlinear controller to facilitate a fast transient response with the performance of a linear controller to obtain a precise regulation in steady-state. This is the case of [12], wherein a fuzzy logic-based controller implements a PI algorithm to eliminate the output voltage error in steady-state. However, when that error or its time derivative are relatively high, the duty cycle changes rapidly by means of a nonlinear action. A similar situation is described in [5], where a PID algorithm for steady-state regulation is combined with a sliding mode control for minimum time transient operation. A posterior attempt to solve the problem of minimum time transient recovery is reported in [13] together with a concise description of different strategies dealing with this problem. Nevertheless, the controller does not operate on-line because it only uses memory accesses and comparisons of previously stored data. Another approach on minimization concerns the output deviation as reported in [14], where a specific integrated circuit for a digital control of a single and a two-phase buck converters is introduced showing that the deviation of the output is four times smaller than that of a fast PID compensator. Other cases exhibiting this hybrid nature are found in the optimal-time control whose goal is to lead the converter’s dynamics to the steady-state in minimum time [15], in the near-optimal voltage deviation and recovery time [16,17], and finally in the use of a hysteretic analog modulator together with a digital linear control loop and a digital frequency regulation loop [18].

On the other hand, most linear digital controllers have been designed from linear analog controllers by mapping the s-plane into the z-plane and employing either frequency domain methods or pole-zero assignments in the z-plane. The first exception is the work reported in [19], where the controller design is based on a discrete-time linear model of the plant, which is obtained with the method presented in [20] for switching converters operating in continuous conduction mode with constant switching frequency. A second exception is found in [21], where a time-domain design method is used to fit a digital PID template to the desired response. In [22], after a review of previous contributions, a methodology to design non-linear digital controllers based on discrete-time sliding mode control is presented where a dead-beat response is achieved [23]. Also, in [24] this methodology is applied to regulate the output voltage of a boost converter with constant power load, providing a comparison with one of the most referenced works in digital control of power converters [25].

The aim of this work is to develop a digital control that combines a good transient response and a good steady-state regulation in only one algorithm. This has the advantage of simplifying the control implementation with respect to the hybrid control realizations found extensively in the literature. The starting point of the controller proposed in this article is the bilinear recurrence developed in [26] for PWM converters in CCM, which is reviewed in Section 2. The proposed nonlinear controller is obtained by input-output linearization and presented in Section 3, in which a discrete-time sliding mode interpretation is also provided. Output voltage regulation and experimental results are reported in Section 4 and Section 5 respectively. Conclusions are presented in Section 6.

2. Nonlinear Recurrence

The dynamic behaviour of a dc-to-dc switching converter operating in CCM with constant switching frequency can be described by the following pair of state equations

$$\begin{array}{cc}\hfill \dot{X}=A_{1}X+b_1{V}_g& nT\le t<(n+d_n)T\end{array}$$

(1)

$$\begin{array}{cc}\hfill \dot{X}=A_{2}X+b_2{V}_g& (n+d_n)T\le t<(n+1)T\end{array}$$

(2)

where X is the converter state vector, $A_1$, $A_2$, $b_1$, and $b_2$ are constant-coefficient matrices, T is the switching period, $nT$ is the instant at the beginning of the conduction state (“ON” state) in $n^{th}$ cycle, and $d_{n}T$ is the duration of “ON” state. Let $d_n$ the duty cycle during the switching cycle $(nT,(n+1\left)T\right)$ and ${\overline{d}}_n=1-d_n$.

The solution of the first equation with initial condition $X\left(nT\right)$ is given by

$$X\left((n+d_n)T\right)=e^{A_1{d}_{n}T}X\left(nT\right)+\underset{nT}{\overset{(n+d_n)T}{\int }}{e}^{A_1((n+d_n)T-\zeta )}{b}_1{V}_g\mathrm{d}\zeta .$$

(3)

Taking into account that the pair [$A_i$, $e^{A_{i}t}$] commutes, i.e., $A_i^{-1}{e}^{A_{i}t}=e^{A_{i}t}{A}_i^{-1}$, Equation (3) becomes as follows

$$X\left((n+d_n)T\right)=e^{A_1{d}_{n}T}X\left(nT\right)+\left(e^{A_1{d}_{n}T}-I\right)A_1^{-1}{b}_1{V}_g$$

(4)

where I is a unitary matrix with appropriate dimensions. Similarly, the solution of Equation (2) with initial condition $X\left((n+d_n)T\right)$ will be given by Equation (5),

$$X\left((n+1)T\right)=e^{A_2{\overline{d}}_{n}T}X\left((n+d_n)T\right)+\underset{(n+d_n)T}{\overset{(n+1)T}{\int }}{e}^{A_2((n+1)T-\zeta )}{b}_2{V}_g\mathrm{d}\zeta .$$

(5)

By inserting Equation (4) in (5) we obtain

$$X\left((n+1)T\right)=e^{A_2{\overline{d}}_{n}T}[e^{A_1{d}_{n}T}X\left(nT\right)+(e^{A_1{d}_{n}T}-I)A_1^{-1}{b}_1{V}_g]+(e^{A_2{\overline{d}}_{n}T}-I)A_2^{-1}{b}_2{V}_g.$$

(6)

Please note that terms in the form $(e^{AT}-I)A^{-1}$ have a matrix series expansion even if A is singular

$$(e^{AT}-I)A^{-1}=T\sum _{n=0}^{\infty }\frac{{\left(AT\right)}^n}{(n+1)!}.$$

(7)

In practice, the switching frequency is much larger than the natural frequencies of the power converters and therefore the exponential matrices containing T can be approximated by their respective first terms of a Taylor’s series at $T=0$, so that Equation (6) can be written as follows in (8),

$$\begin{array}{ccc}\hfill X\left(\right(n+1\left)T\right)& \approx & [I+(A_1{d}_n+A_2{\overline{d}}_n)T]X\left(nT\right)+(b_1{V}_g{d}_n+b_2{V}_g{\overline{d}}_n)T].\hfill \end{array}$$

(8)

The recurrence equation defined in Equation (8) can be expressed as

$$X\left((n+1)T\right)=HX\left(nT\right)+FX\left(nT\right)d_{n}T+E{d}_{n}T+G$$

(9)

where

$$\begin{array}{cccc}E=\left(b_1-b_2\right)V_g,\hfill & F=\left(A_1-A_2\right),\hfill & G=b_2{V}_{g}T,\hfill & H=I+A_{2}T.\hfill \end{array}$$

(10)

The nonlinear nature of recurrence Equation (9) is observed in the second and forth terms by showing the respective multiplication of the duty cycle (control) by the state vector and by an additive term depending on the input voltage (energy). In the particular case of the buck converter $A_1=A_2$, which implies $F=0$ and reveals that the nonlinear behaviour is an afine characteristic. In the case of a boost converter $b_1=b_2$, which results in $E=0$ and shows that the nonlinear characteristic is produced by the product of the control and state vector.

Although a constant value has been considered for $V_g$, the analysis developed could be applied also to slowly varying input voltages. In this case there will be also a nonlinearity produced by the product of the control and the input voltage.

3. Current Control Loop Based on Input-Output Linearization

In the particular case of a buck converter (Figure 1), the state vector is $X={\left[v_C{i}_L\right]}^T$ and therefore the nonlinear recurrence can be simplified as follows

$$X\left((n+1)T\right)=HX\left(nT\right)+E{d}_{n}T$$

(11)

since F and G are zero because $A_1=A_2$ and $b_2=0$ in such converter.

Matrix H can be expressed as

$$\begin{array}{c}H={\left(h_{ij}\right)}_{2\times 2}\hfill \end{array}$$

(12)

where

$$\begin{array}{cccc}{h}_{11}=1-\frac{{\displaystyle R_{a}T}}{{\displaystyle L}},\hfill & h_{12}=-\frac{{\displaystyle (1-\epsilon )T}}{{\displaystyle L}},\hfill & h_{21}=\frac{{\displaystyle (1-\epsilon )T}}{{\displaystyle C}},\hfill & h_{22}=1-\frac{{\displaystyle T}}{{\displaystyle C{R}_b}}\hfill \end{array}$$

(13)

and

$$\begin{array}{ccc}{R}_a=R_1+\frac{{\displaystyle R_o{R}_2}}{{\displaystyle R_o+R_2}},\hfill & \epsilon =\frac{{\displaystyle R_2}}{{\displaystyle R_o+R_2}},\hfill & \mathrm{and}{R}_b=R_o+R_2.\hfill \end{array}$$

(14)

Hence, recurrence Equation (11) can be expressed as

$$\begin{array}{ccc}\hfill i_L\left((n+1)T\right)& =& h_{11}{i}_L\left(nT\right)+h_{12}{v}_C\left(nT\right)+\frac{V_g}{L}{d}_{n}T\hfill \end{array}$$

(15)

$$\begin{array}{ccc}\hfill v_C\left((n+1)T\right)& =& h_{21}{i}_L\left(nT\right)+h_{22}{v}_C\left(nT\right).\hfill \end{array}$$

(16)

Now, let’s impose that the current sample at instant $(n+1)T$ reaches a reference $i_{REF}\left(nT\right)$ with an approximation error dynamics that decreases in geometric progression. The error dynamics can be expressed as follows

$$i_L\left((n+1)T\right)-i_{REF}\left(nT\right)=w\left(i_L\left(nT\right)-i_{REF}\left(nT\right)\right)$$

(17)

where

$$-1<w<1$$

(18)

and w is the ratio of the decreasing geometric progression. Taking into account Equation (15), imposing the current error dynamics given by Equation (17) requires a control law given by

$$\begin{array}{ccc}\hfill d_n& =& \frac{L}{V_{g}T}((1-w)i_{REF}\left(nT\right)-h_{12}{v}_C\left(nT\right)-(h_{11}-w)i_L\left(nT\right)).\hfill \end{array}$$

(19)

Assuming that the current has tracked its digitally generated reference of constant value $i_{REF}\left(nT\right)=I_{REF}u\left(nT\right)=i_{REF}\left[n\right]$ for the sake of simplicity, the remaining dynamics corresponding to the capacitor voltage will be described by

$$v_C\left((n+1)T\right)=h_{21}{i}_{REF}\left[n\right]+h_{22}{v}_C\left(nT\right).$$

(20)

Besides, the converter parameters have the following bounds

$$\begin{array}{cccc}0<h_{11}<1,\hfill & 0<h_{22}<1,\hfill & h_{12}<0,\mathrm{and}\hfill & h_{21}>0.\hfill \end{array}$$

(21)

Therefore the coefficient of $v_C\left(nT\right)$ in recurrence Equation (20) is positive and smaller than one. Hence, the recurrence will always exhibit a stable behaviour around the converter steady-state operating point given by

$$\begin{array}{ccc}\hfill I_L& =& I_{REF}\hfill \end{array}$$

(22)

$$\begin{array}{ccc}\hfill V_C& =& \frac{I_{REF}{h}_{21}}{1-h_{22}}\hfill \end{array}$$

(23)

$$\begin{array}{ccc}\hfill D& =& \frac{I_{REF}L}{V_{g}T}\frac{(1-h_{22})(1-h_{11})-h_{12}{h}_{21}}{(1-h_{22})}.\hfill \end{array}$$

(24)

It has to be pointed out that the recurrence based on the current valley is accurate to describe the inductor current dynamics but it is less exact to explain the capacitor voltage behaviour. This discrepancy is due to the ripple existence in both inductor current and capacitor voltage. Thus, if no losses are assumed, the steady-state mean value of the capacitor voltage will be given by the product of the corresponding mean value of the inductor current and the load resistance. This is not the case in Equation (23), which predicts a capacitor voltage given by the product of the current valley and the load resistance $V_C=R_o{I}_{REF}$. Hence, there is a prediction error in each recurrence period given by

$$〈V_C〉-V_C=\frac{I_{MAX}-I_{REF}}{2}{R}_o$$

(25)

where $〈V_C〉$ and $I_{MAX}$ are the mean and maximum values of capacitor voltage and inductor current in steady-state respectively.

For this reason, the recurrence expressing the voltage behaviour is now modified with the introduction of some additional terms corresponding to a trapezoidal approximation in the calculation of the inductor current mean value. For the sake of simplicity, no losses are considered ($R_1=0$, $R_2=0$) so that the new recurrence for the capacitor voltage can be expressed as follows:

$$v_C\left((n+1)T\right)=h_{21}^{\prime }{i}_{REF}\left[n\right]+h_{22}^{\prime }{v}_C\left(nT\right)+(-d_n^2+2d_n)\frac{T^2}{2LC}{V}_g$$

(26)

where $d_n$ was given in Equation (19), $h_{21}^{\prime }=\frac{T}{C}$, and $h_{22}^{\prime }=1-\frac{T}{R_{o}C}-\frac{T^2}{2LC}$.

The new equilibrium point is

$$\begin{array}{ccc}\hfill I_L& =& I_{REF}\hfill \end{array}$$

(27)

$$\begin{array}{ccc}\hfill V_C& =& \frac{V_g}{2}\left[(1-\frac{2L}{R_{o}T})+\sqrt{{\left(1-\frac{2L}{R_{o}T}\right)}^2+\frac{8L{I}_{REF}}{T{V}_g}}\right]\hfill \end{array}$$

(28)

$$\begin{array}{ccc}\hfill D& =& \frac{V_C}{V_g},\hfill \end{array}$$

(29)

which is coincident with the reported in [22] using an equivalent discrete-time sliding approach to obtain the recurrence for the output capacitor voltage. In fact, both approaches are completely equivalent if $w=0$. It is possible to provide a sliding mode interpretation of our approach Equation (17) considering that it proposes a more general switching surface $s_e$ than the one in [22], which was the current error with negative sign. The new surface Equation (31) includes a dynamical term of the current error with the same decreasing geometric progression of the input-output linearization and becomes Equation (30) for $w=0$.

$$\begin{array}{ccc}\hfill s\left(nT\right)& =& i_L\left(nT\right)-I_{REF}\left(nT\right)\hfill \end{array}$$

(30)

$$\begin{array}{ccc}\hfill s_e\left(nT\right)& =& s\left(nT\right)-ws\left(\right(n-1\left)T\right)\hfill \end{array}$$

(31)

$$\begin{array}{ccc}\hfill s_e\left((n+1)T\right)& =& 0.\hfill \end{array}$$

(32)

Adding a dynamical term in the discrete recurrence increases the order of the closed loop reference-to-current transfer function in the z domain Equation (34) that, since it exhibits the order reduction associated with sliding mode ideal dynamics, is of first order and can be directly determined from the recurrence equation of the current.

$$\begin{array}{ccc}\hfill i_L\left((n+1)T\right)& =& w{i}_L\left(nT\right)+(1-w)I_{REF}\left(nT\right)\hfill \end{array}$$

(33)

$$\begin{array}{ccc}\hfill G_I\left(z\right)& =& \frac{I_L\left(z\right)}{I_{REF}\left(z\right)}=\frac{1-w}{z-w}.\hfill \end{array}$$

(34)

Please note that with $w=0$ the pole of the $I_{REF}$-to-$I_L$ current loop transfer function is located at the origin like in a dead-beat control of a first order discrete-time system [23].

4. Voltage Regulation

An outer loop establishing the reference of the inner current loop is added now in order to regulate the output voltage to a desired level $V_{REF}$, the reference being the sum of two terms which are respectively proportional to the output voltage error and to the integral of the error.

In the descriptive equations of the system, Equations (17), (19), and (26), the discrete current reference, and proportional and integral errors can be expressed as follows

$$\begin{array}{ccc}\hfill i_{REF}\left[n\right]& =& k_{1}e\left[n\right]+k_{2}inte\left[n\right]\hfill \\ \hfill e\left[n\right]& =& V_{REF}u\left(nT\right)-v_C\left(nT\right)\hfill \\ \hfill inte\left[n\right]& =& inte[n-1]+e\left[n\right]\hfill \end{array}$$

(35)

where $V_{REF}$ is the desired output voltage and $k_1$, $k_2$ are respectively the proportional and integral coefficients of the voltage regulation loop. Equivalently, Equation (35) can be written in compact form as

$$i_{REF}\left[n\right]=i_{REF}[n-1]+\frac{k_n}{k_{VI}}(e\left[n\right]-\beta z_{P}e[n-1])$$

(36)

where the control parameters have been normalized with respect to Equation (13) as $k_n=(k_1+k_2)k_{VI}$ and $\beta =\frac{k_1}{(k_1+k_2)z_P}$.

It can be observed that, although the equation corresponding with the voltage regulator is linear, Equations (17), (19), (26) should be linearized around the equilibrium point so that the choice of coefficients $k_1$, $k_2$ or $k_n$, $\beta$ can be carried out by means of linear control techniques. The analysis of the linearized equations together with Equation (35) in the z domain results in the following transfer equations

$$G_P\left(z\right)=\frac{V_C\left(z\right)}{I_{REF}\left(z\right)}=\frac{k_{VI}(1-w)(z-z_D)}{(z-w)(z-z_P)}=G_I\left(z\right)\frac{k_{VI}(z-z_D)}{(z-z_P)}$$

(37)

$$G_C\left(z\right)=\frac{I_{REF}\left(z\right)}{E\left(z\right)}=\frac{k_n}{h_{VI}}\frac{(z-\beta z_P)}{(z-1)}$$

(38)

where coefficients $k_{VI}$, $z_N$ and $z_P$ are

$$\begin{array}{ccc}\hfill k_{VI}& =& \frac{T(V_g-V_C)}{CVg}\ge 0\hfill \\ \hfill z_D& =& -\frac{V_C}{V_g-V_C}<0\hfill \\ \hfill z_P& =& 1-\frac{2LT+R_o{T}^2(2V_C/V_g-1)}{2L{R}_{o}C}.\hfill \end{array}$$

(39)

It should be noted that the transfer function in Equation (37) presents a zero depending on the operating point associated with the delay inherent to the digitally PWM controlled converter [22].

The closed loop gain will be

$$\mathcal{T}\left(z\right)=\frac{k_n(1-w)(z-z_D)(z-\beta z_P)}{(z-w)(z-z_P)(z-1)}$$

(40)

where $\beta =1$ will fix a closed loop pole in its open loop position. A sensible design of the control parameters will usually consider the ranges $0<\beta <1$ and $0<k_n$.

Let us consider the converter coefficients and operation point described in [22]. It can be shown that $z_D=-1$ for $D=0.5(V_C=V_g/2)$ and the pole $z_P$ in the plant Equation (37) corresponds to the converter coefficient $h_{22}$. For the given voltage operation point, while the previous zero and pole of the plant are already determined from the point of view of the controller design, the pole at w corresponding to the input-output linearization in the current loop can be adjusted to improve the performance of the voltage controller. Applying the Jury criterion to the characteristic equation $1+\mathcal{T}\left(z\right)=0$ the following expression can be obtained.

$$-\frac{1+w}{(1-w)h_{22}}<k_n\beta <\frac{1}{h_{22}}.$$

(41)

In the most restrictive case $(w\to -1)$ Equation (41) becomes

$$0<k_n<\frac{1}{\beta h_{22}}.$$

(42)

Other necessary conditions provided by the Jury criterion have been omitted because they are more complex and not so useful for the control design.

5. Experimental Results and Numerical Simulations

To verify the performance of the proposed digital control and, in particular, the effects of the inner current loop parameter w, a buck converter power stage with synchronous rectification was built and its control implemented on a Texas Instruments TMS320F28335 Digital Signal Controller (DSC) as shown in Figure 2.

As mentioned previously, the power stage, whose components are described in

Table 1. Components and parameters of the synchronous buck converter

Component/Parameter	Description	Type/Value
$Q_1$, $Q_2$	Power MOSFET	IRF3798
C	Ceramic Capacitor	C5750X7R1C476M230KB
	X7R dielectric	$11\times 47\mathsf{\mu }$F
		5-V estimated C $\approx 350\mathsf{\mu }$F
L	Power Inductor	WE-HCC 7443320330
	Ferrite core	L at $100$ kHz: $3.3\mathsf{\mu }$H
$R_1+R_s$	Series Resistor	Total Resistance: $\approx 6.6$ $\mathrm{m}\mathsf{\Omega }$
	Current Sensing	SMD $2.2$ $\mathrm{m}\mathsf{\Omega }$
	+ Inductor DCR	$4.4$ $\mathrm{m}\mathsf{\Omega }$
$R_o$	Load	Aluminium Housed
	Power Resistor	$1\mathsf{\Omega }$
T	Switching period	$10\mathsf{\mu }$s
$f=1/T$	Switching frequency	$100$ kHz
$\Delta i_L$	Inductor peak-to-peak current ripple	$7.6$ A
	($V_g=10$ V, $v_o=5$ V and $R_o=1$ $\mathsf{\Omega }$)
$I_L$	Inductor dc current	$5$ A
	($V_g=10$ V, $v_o=5$ V and $R_o=1$ $\mathsf{\Omega }$)
$\Delta v_o$	Output peak-to-peak voltage ripple	$27$ mV
	($V_g=10$ V, $v_o=5$ V and $R_o=1$ $\mathsf{\Omega }$)	(0.54%)
MOSFET Driver	High-speed synchronous MOSFET driver	LM27222
	Texas Instruments
Current monitor	Bidirectional current shunt monitor	AD8210
	Analog Devices

, is the same used in [22]. Since the parameters of the X7R dielectric vary with the frequency, temperature, current ripple and dc applied voltage, an approximated value of 350 $\mathsf{\mu }$F for the output capacitor bank was experimentally determined from the ac voltage ripple at the operating point. It has been assumed that $R_2$ is negligible.

On the other hand, the variables required by the control ($V_g$, $v_o$, and $i_L$) are sensed by means of resistive voltage dividers for input and output voltages and by means of an AD8210 difference amplifier for the inductor current. For simplicity reasons, instead of providing an external analog signal, the references are variables within the DSC code. All the analog signals are converted into digital values by means of a 12-bit Analog-to-Digital Converter (ADC) and processed to calculate the control law according to Equation (19) as illustrated in Figure 2. The core of the control law (19) is the same for both the current control (only internal loop) and the voltage control (two loops), the current reference variable $i_{REF}$ being an independent variable in the case of the current control implementation, while in the case of output voltage regulation, the value of $i_{REF}$ is given by the PI compensator output.

The control coefficients $k_n$ and $\beta$ are only required for voltage control and their selection will be discussed later, whereas three different values have been considered for the ratio of the decreasing geometric progression $w\in \left[-0.5,0.0,0.5\right]$ of the current loop.

In addition, the PWM signal of $Q_2$ with duty cycle $d_n$ corresponding to the control law is obtained by using a Digital Pulse Width Modulator (DPWM) of the DSC and sent to the LM27222 integrated circuit to drive the switch formed by the complementary action of $Q_1$ and $Q_2$ (IRF3708 MOSFETs).

Figure 3 shows a picture of the experimental setup with the buck power stage and the digital signal controller in front and the main dc power source, an electronic load, the oscilloscope, and an auxiliary power supply that provides 5 V to the digital board at the rear.

5.1. Inner Current Loop

A sequential sampling of the input and output voltages and the current signal has been synchronized with the PWM sawtooth signal and adjusted so that all variables are available to start performing the duty cycle calculations at the beginning of each cycle. It has been verified that a typical duty cycle calculation requires about $1.5\mathsf{\mu }$s, well below the nominal ON time of $5\mathsf{\mu }$s of the trailing-edge modulation considered. Despite configuring the current to be the last sampled variable, the analog-to-digital sampling, conversion, and latency times, makes impossible to mimic exactly the theoretical procedure. Therefore, instead of sampling the inductor current at its minimum value, it is sampled at about $200$ ns before the end of a switching cycle, still at the OFF subinterval where the current slope is negative.

Figure 4 show simulations (left) and experimental results (right) of the inductor current response to a step increase from 3 A to 5 A of the valley current reference, where the three different values of the geometric convergence factor $w\in \{-0.5,0.0,0.5\}$ have been considered. These values have been selected so that three different qualitative responses to the same step reference change can be discussed.

The ADC $200$ ns-delay, together with the effects of the 350-kHz bandwidth of the implemented current sensor, and the first order RC antialiasing filter of the control card are the main causes for the differences between the minimum current values and their references observed in the PSIM simulations. As it can be seen, since all these factors have been considered, the simulated currents are in a remarkable good agreement with the corresponding experimental waveforms. Being digitally generated, the reference waveform is not shown at the oscilloscope captures.

In Figure 4a,b the convergence factor is $w=0.5$. The error between the current minimum values and its final steady-state value is reduced in half every switching cycle and an exponential envelope linking the minimums can be easily visualized. In Figure 4c,d the convergence factor has been reduced to $w=0.0$ so that, disregarding the delay associated with the modulation, the steady-state zero-error is reached in one cycle. As delay associated with the modulation we mean that, assuming ideally no delays and instantaneous calculation times, all reference changes at any point between two consecutive sampling points are seen by the control as a change at the beginning of the cycle, and result in the same response. The $w=0$ response seems optimal from the point of view of transients in the current loop but, since our objective is to regulate the output voltage, we have decided to analyze also the possibility of using a negative convergence factor. The effects of $w=-0.5$ can be seen in Figure 4e,f, where the transient duration is the same as in the opposite sign case, $w=0.5$, but the alternation in the error sign makes it difficult to imagine the two exponential envelopes, one increasing and one decreasing, linking every other minimum point of the current. The negative convergence factor effect is similar than in analog peak and valley current-mode control which also could result in a negative discrete-time pole. The difference being that, in our case, the pole is imposed by the value of w while in analog control it is a consequence of many parameters.

5.2. Voltage Regulation Loop

The current reference-to-output voltage discrete transfer in Equation (44) corresponding to $w=0.0$ has been used to design the parameters of a PI compensator in MATLAB’s Control System Designer Toolbox. The PI parameters have been slightly rounded to final values of $k_n=0.275$ and $\beta =0.85$ that provide a crossover frequency (CF) of about 8 kHz and a phase margin (PM) of about ${45}^{\circ }$. The exact CF and PM figures are provided in

Table 2. Crossover frequency (CF) and phase margin (PM) for different values of w (with $\beta =0.85$ and $k_n=0.55$).

	Theoretical		Simulated		Experimental
w	CF	PM	CF	PM	CF	PM
$\left(-\right)$	(kHz)	(deg)	(kHz)	(deg)	(kHz)	(deg)
0.5	7.3	23.3	6.1	34.0	5.2	36.9
0.0	8.4	43.4	7.3	44.2	6.2	46.4
−0.5	8.6	53.2	7.6	48.7	7.3	47.4

where the theoretical values are compared with the results obtained from PSIM closed loop ac-sweep simulations and the experimental measurements obtained using a Venable 3120 frequency response analyzer (FRA). The table provides also data obtained with $w=0.5$ and $w=-0.5$ using the same PI parameters. To help readers to reproduce the theoretical results, all three numerical current reference-to-output voltage discrete transfer functions are provided next.

$$\begin{array}{ccc}\hfill G_P{\left(z\right)|}_{w=0.5}& =& \frac{z+1}{140z^2-206z+68}\hfill \end{array}$$

(43)

$$\begin{array}{ccc}\hfill G_P{\left(z\right)|}_{w=0.0}& =& \frac{z+1}{70z^2-68z}\hfill \end{array}$$

(44)

$$\begin{array}{ccc}\hfill G_P{\left(z\right)|}_{w=-0.5}& =& \frac{3(z+1)}{140z^2-66z-68}.\hfill \end{array}$$

(45)

The common PI discrete controller is

$$G_C\left(z\right)=19.3\frac{z-0.8257}{z-1}.$$

(46)

Simulation and experimental results are in good agreement despite a relatively ideal simulation circuit, which has no switching losses and a very simple model of the switching delays. As expected, since the theoretical transfer functions have been obtained after linearizing the approximate model (9), theoretical predictions differ more than simulations from the experimental results. The differences are more significant in the cases of $w=0.5$ and $w=-0.5$ than for $w=0.0$. The maximum error is between the theoretical and the experimental values of PM for $w=0.5$. For the three kinds of data origins (theoretical predictions, simulations, and experimental measurements), selecting $w=-0.5$ provides wider loop bandwidths (CFs) and higher PMs with the same computational efforts in the experimental setup.

Figure 5 depicts the three theoretical discrete root locus plots corresponding to the previous transfer Equations (43), (44), and (45). All the root locus have been obtained for the same PI compensator in Equation (46) (with $\beta =0.85$ and $k_n=0.275$), and only the inner current loop convergence factor w is different among them. Root locus in Figure 5b with $w=0.0$ is the reference diagram predicting a closed loop positive discrete pole and a pair of complex conjugated poles with a damping factor of 0.741, close to $1/\sqrt{2}$. Root locus (a) corresponding to $w=0.5$ depicts a similar real pole but has a pair of less damped complex poles (damping factor 0.26). Finally, the effect of $w=-0.5$ is depicted in plot (c) where the damping factor of the dominant complex pole pair is 0.94 and the real pole is negative ($-0.305{\mathrm{s}}^{-1}$).

Closed voltage loop simulated and experimental responses to $\pm 2$-A step changes in the nominal load are provided in Figure 6. Left plots correspond to PSIM simulations and right plots to experimental oscillograms. Again, the PI compensator is the same in Equation (46) for all cases shown, being w the only parameter that is different among the lines of subplots. The less damped voltage responses in top Figure 6a,b that correspond to $w=0.5$ are qualitatively in good agreement between them and also with the theoretical underdamped closed loop poles of Figure 5a root locus. The amplitudes of the over- and undershoots and frequency of the ringings are similar although the experimental plot seems slightly more damped, which is to be expected because the simulation considers only conduction losses. Middle Figure 6c,d depict the simulated and experimental load regulation responses when $w=0.0$. Both voltage responses are a bit more damped than the one expected from a system with a theoretical damping factor slightly larger than $1/\sqrt{2}$. Finally, the dynamics of the voltage responses in bottom Figure 6e,f are coincident with those of an almost critically damped system (dominant complex poles with a theoretically damping factor of 0.94) with settling times of about $120\mathsf{\mu }$s – $140\mathsf{\mu }$s. As expected from the similar PMs in Table 2 there are no large differences between the dynamics with $w=0.0$ and $w=-0.5$. The main difference is in the over and under shoot absolute amplitudes that are 20 mV smaller for $w=-0.5$ than for $w=0.0$.

Since experimental load regulation results with $w=-0.5$ are slightly better, the following simulations and experiments are focused on this case. Figure 7 depicts the system responses to relatively large amplitude $\pm 1$-V reference changes. In both simulated and experimental cases the valley current reference has been limited between $-5$ A and 8 A. It is important to limit the maximum current, although indirectly, to avoid saturating the power stage inductor and the oscilloscope current probe. Establishing saturation limits to the current reference is also useful to avoid exceeding the current sensor linear operation range. In both simulation and experiments reference changes from 5 V to 6 V and back from 6 V to 5 V have been considered. In the positive changes, the output voltage reaches the 6-V steady state in about $140\mathsf{\mu }$s. It is worth noting that the 8-A valley current reference limitation acts for about 5 switching periods. The response to the negative reference change is slightly faster, about $120\mathsf{\mu }$s, because in the experiment there is no saturation of the negative current reference and in the simulation it is of less than one switching period, and it is required more duration of the saturation to have a significant effect on the voltage dynamics.

Figure 8 shows the inductor current and output voltage at the system start-up from zero initial conditions. In this large-signal voltage situation, in addition to the current reference limit of 8 A, a limitation of the minimum duty cycle to 15% ensures that duty cycles smaller than the calculation time do not cause problems with the DPWM. The DSC DPWM comparator generates an interrupt when the duty cycle registry is equal to that of the digital ramp. Therefore, the interrupt is not generated if the duty cycle registry is written with a value smaller than the digital ramp of the DPWM, which causes the control signal to be at high state for the full period and, usually in start-up, severe current spikes. As it can be seen, although the mentioned saturations, the output voltage reaches its desired steady state in about $400\mathsf{\mu }$s in the simulation and in about $600\mathsf{\mu }$s in the experiment without noticeable overvoltages. The difference in start-up times is due to the fact that the X7R dielectric of the 11 small-footprint ceramic capacitors connected in parallel in the experimental power stage is highly nonlinear with respect to the operating voltages and temperatures. From a theoretical value of $517\mathsf{\mu }$F around 0 V the capacitance at 5 V, estimated from current and voltage ripple measurements, derated to about $350\mathsf{\mu }$F.

To avoid having a discontinuous input current, the buck power stage has a 1-mF capacitive input filter that makes difficult to apply high slew-rate perturbations in the input voltage. The experimental results in Figure 9b shows the input voltage obtained when programming at the dc power supply an ideal 25-Hz square voltage between 10 V and 14 V. As it can be seen, after a voltage change the real input voltage converges exponentially to the new steady-state value. The simulation in Figure 9a has been adjusted so that is shows the same input voltage pattern as in the experiment. As expected, the line regulation is excellent, with just small changes in the ripple amplitudes of the output voltage that are caused by the peak-to-peak amplitude modulations in the inductor current.

6. Conclusions

This work develops a nonlinear digital control in a PWM buck converter with steady-state voltage regulation and fast transient response. Uses a discrete-time bilinear model of the converter in CCM and applies input-output linearization of the inductor current dynamics to obtain the control law. The current control algorithm employs the samples of capacitor voltage and inductor current at the beginning of the ON interval to determine the duty cycle in the same switching cycle. The main limitation occurs at low voltage values because the calculation time of the particular experimental implementation imposes a minimum duty cycle of about 15%. The internal current loop is stable for all the permitted range of duty cycle values when it operates either alone as an inductor current regulator or in cooperation with an outer loop for output voltage regulation. It has been determined that selecting a negative value for the convergence factor w in the current loop instead of zero, as in the case of a sliding control, can provide a slightly better load regulation performance. The start-up large-signal transient is fast and together with line regulation simulations and experiments verify the excellent regulation of the output voltage.