Series-Series/Series Compensated Inductive Power Transmission System with Symmetrical Half-Bridge Resonant Converter: Design, Analysis, and Experimental Assessment

Abstract

In order to compensate the large leakage inductance and improve the power transmission capacity, capacitors are widely used in inductive power transfer (IPT) systems, which results in high voltage or current stresses in the resonant tanks and limits higher volt-ampere (VA) rating of the transfer power, especially in medium and low frequency applications. This paper presents a symmetrical half-bridge resonant converter (SHRC) for series-series/series compensated IPT systems with detailed analysis and design. It operates at a relatively low frequency of 12.5 kHz, suitable for IGBT applications. The theoretical analysis shows that, compared with full-bridge resonant converter (FRC) for IPT, the symmetrical half-bridge resonant converter achieves a higher efficiency. Simulation and a prototype of 1500 W power output were built to verify the theoretical analysis. The experimental results show that the power loss of SHRC is 39.7 W while that of FRC is 79.4 W, which is consistent with the theoretical analysis. The global efficiency of the IPT based on the proposed converter is 91.6%.

1. Introduction

Inductive power transfer (IPT) systems transfer electric power across an air gap by magnetic coupling and produces comparative advantages over transfer with physical contact. It has been widely used in commercial and industrial applications where convenience and safety are imperative, such as household apparatuses [1], biomedical applications [2], and electric vehicle (EV) charging [3,4,5,6,7,8,9]. Different from strongly coupled systems, the mutual coupling of IPT systems is generally weak. The leakage inductance is relatively high, and the coupling coefficient k is usually less than 0.2, resulting in a large reactive power which can be up to 50 times the transmitted power [10]. Moreover, system losses increase due to high reactive current [11]. To deliver the required power, improve the transfer efficiency, and minimize the VA rating of the power supply, it is necessary to compensate the leakage inductance [11,12]. Four basic compensation topologies, which are series/series (S/S), series/parallel (S/P), parallel/series (P/S), and parallel/parallel (P/P), were widely used in a number of studies [10,11]. The primary parallel compensation topologies (P/S and P/P) are fed by current source or with a bulky inductor [4,13,14,15], while the primary series topologies (S/S and S/P) are fed by voltage source [16]. Compared with P/S and P/P topologies, S/S and S/P topologies which require less space are more commonly used in IPT [4,17]. Compared with S/P topology, S/S compensation can achieve better overall efficiency [18], requires less copper mass [3], and is independent of the load [19]. Our research in this paper based on the S/S topology.

Derived from the four basic compensation topologies, more compensation topologies were proposed to improve the IPT systems. An SP/S compensation method, which can be regarded as a combination of S/S and P/S, was used to achieve a high misalignment tolerance without adjusting the primary power supply [20]. S/SP compensation topology was proposed to achieve high efficiency and good output controllability [12]. LCL compensation topology with two large inductors was presented to avoid instantaneous changes in the voltages of the inverter and was proved to be suitable under variations of load and coupling coefficient [21]. In order to reduce the size of the inductors in LCL, LCC was proposed in [22], which had high misalignment tolerance and load independence characteristics [15]. LCC was further optimized to suitable for EVs charging in [7]. An efficient double-sided LCC for IPT system was proposed in [23], and the dead time optimization of this double-sided LCC topology for power and efficiency enhancement were further studied in [24]. However, the compensation networks became more complex with additional capacitors and/or inductors. The orders and interdependency of the IPT system increased. The combination of inductor and/or capacitor of the four basic compensation topologies is rarely studied.

In a strongly coupled transformer system, the full-bridge topology is widely used rather than half-bridge topology. The reasons are probably related to the following issues of the half-bridge topology: Poor controllability, low power density, and voltage imbalance of the two capacitors. However, in the IPT systems the shortages of half-bridge topology become less important. The main factor limiting the power capacity of the IPT system is the high voltage stresses of the compensated capacitors due to the large leakage inductance, especially when the operating frequency is relatively low. On the other hand, the half-bridge topology has advantages such as less power devices and lower cost. In this paper, a series-series/series (SS/S) compensated symmetrical half bridge resonant converter (SHRC) with double capacitors in primary is presented as shown in Figure 1a. Without increasing the order of the system, the system characteristics and efficiency of the proposed topology will be discussed by comparing with the full-bridge resonant converter (FRC)-based IPT system as shown in Figure 1b. In order to make the converter smaller with smaller filter capacitor, three-phase AC power sources with rectifier and filter are adopted in both Figure 1a,b.

The main contents of this paper are organized as follows: The detailed design process is analyzed in Section 2. The efficiency analysis of the proposed system and an efficiency comparison between SHRC and FRC are shown in Section 3. Simulations and experimental results are given in Section 4 to verify the analysis. Finally, Section 5 contains the conclusions and discussions.

2. Proposed Topology and Operation Analysis

The topology of the SS/S SHRC is shown in Figure 1a. Different from the traditional half-bridge converter, the voltage value of point B is varying instead of U_in/2. C₁₁ and C₁₂ are the primary compensation capacitors, which are in series with the inductor and connected to the DC power U_in. The capacitance of the two capacitors are not necessarily the same, and one can be zero. The secondary is series compensated. To achieve optimal efficiency, the IPT system operates in resonance [13]. Interestingly, converter fed by voltage source for IPT generally operates in near resonance frequency with slightly inductive in practical applications.

2.1. Mode Analysis

In Figure 1a, S₁ and S₂ alternatively turn on converting DC source U_in into high-frequency AC power to drive the resonant circuit. The primary resonant circuit consists of capacitor C₁₁, C₁₂, and coil L₁. Coils of primary L₁ and secondary L₂ have the same structure. There are four operational modes of the proposed topology as shown in Figure 2. The main waveforms of these modes are illustrated in Figure 3 where i₁ is the current of the primary inductor, i_a is the input current, u_A is the voltage of point A, and u_C12 is the voltage of capacitor C₁₂.

Mode 1 [t₀, t₁]: Before t₀, switch S₁ is off. The input current i_a flows through antiparallel diode D₁. Therefore, at t₀, S₁ turns on under zero-current-switching (ZCS) and zero-voltage-switching (ZVS) conditions. During this mode, S₁ turns on, input voltage U_in is connected to the primary resonant circuit as Figure 2a. Taking into account of conduction loss of switch, system dynamics is given by

$$\{\begin{array}{l}(r_L+r_C+r_{on})i_1+j\omega L_1{i}_1+\frac{i_{11}}{j\omega C_{11}}+j\omega M{i}_2=0\mathrm{loop}1\\ (r_L+r_C+r_{on})i_1+j\omega L_1{i}_1+\frac{i_{12}}{j\omega C_{12}}+j\omega M{i}_2=U_{\mathrm{in}}\mathrm{loop}2\end{array}$$

(1)

where

$$i_{11}+i_{12}=i_1$$

(2)

r_on, r_L, and r_C are the equivalent on-resistance of the switch, lumped resistance of primary coil, and equivalent series resistance of resonant capacitor, respectively. i₁₁ and i₁₂ are the current of C₁₁ and C₁₂, respectively. When

$$C_{12}=\alpha C_{11}$$

(3)

$$C_1=C_{11}+C_{12}=(1+\alpha )C_{11}$$

(4)

and based on Equation (2), Equation (1) is simplified as Equation (5) by adding the left side of loop 1 to the left side of loop 2 and adding the right side of loop 1 to the right side of loop 2.

$$(r_L+r_C+r_{on})i_1+j\omega L_1{i}_1+\frac{i_1}{j\omega C_1}+j\omega M{i}_2=\frac{\alpha }{\alpha +1}{U}_{\mathrm{in}}$$

(5)

Mode 2 [t₁, t₂]: At t₁, S₁ turns off and the primary coil current i₁ is low, but positive, and almost equal to 0. i₁ keeps flowing into antiparallel diode D₂, which insures ZCS and ZVS of S₂ in mode 3. This mode also plays the role of dead zone for the converter. Simplified as mode 1, mode 2 system dynamics can be expressed as

$$U_D+(r_L+r_C)i_1+j\omega L_1{i}_1+\frac{i_1}{j\omega C_1}+j\omega M{i}_2=-\frac{1}{\alpha +1}{U}_{\mathrm{in}}$$

(6)

where U_D is the turn-on voltage of antiparallel diode.

Mode 3 [t₂, t₃] and mode 4 [t₃, t₄] are similar to mode 1 and mode 2, respectively. The corresponding system dynamics are given by

$$(r_L+r_C+r_{on})i_1+j\omega L_1{i}_1+\frac{i_1}{j\omega C_1}+j\omega M{i}_2=-\frac{1}{\alpha +1}{U}_{\mathrm{in}}$$

(7)

$$U_D+(r_L+r_C)i_1+j\omega L_1{i}_1+\frac{i_1}{j\omega C_1}+j\omega M{i}_2=\frac{\alpha }{\alpha +1}{U}_{\mathrm{in}}$$

(8)

To simplify the calculation, mode 2 and mode 4 can be represented by mode 3 and mode 1 since they are so short compared with mode 1 or mode 2. From the four mode system dynamics Equations (5)–(8), SHRC system dynamics are further simplified as

$$\{\begin{array}{l}(r_L+r_C+r_{on})i_1+j\omega L_1{i}_1+\frac{i_1}{j\omega C_1}+j\omega M{i}_2=\frac{\alpha -1}{2\alpha +2}{U}_{in}+\frac{1}{2}{U}_{\mathrm{in}}0\le t<\frac{T}{2}\\ (r_L+r_C+r_{on})i_1+j\omega L_1{i}_1+\frac{i_1}{j\omega C_1}+j\omega M{i}_2=\frac{\alpha -1}{2\alpha +2}{U}_{in}-\frac{1}{2}{U}_{\mathrm{in}}\frac{T}{2}\le t<T\end{array}$$

(9)

where T is switching period of the converter. Equation (9) can be expressed as

$$(r_L+r_C+r_{on})i_1+j\omega L_1{i}_1+\frac{i_1}{j\omega C_1}+j\omega M{i}_2=\frac{\alpha -1}{2\alpha +2}{U}_{\mathrm{in}}+u_{half}$$

(10)

where u_half is a square wave with amplitude of U_in/2 and mean of 0. According to Equation (10), the SHRC systems can be presented as Figure 4.

Where

$$\{\begin{array}{l}{R}_1=r_L+r_C+r_{on}\\ R_2=r_L+r_C\end{array}$$

(11)

If α = 1, DC component of Equation (10) $\frac{\alpha -1}{2\alpha +2}{U}_{\mathrm{in}}=0$, the SHRC and FRC will share the same equivalent circuit as shown in the dotted rectangle in Figure 4. If α ≠ 1, based on first harmonic approximation method, Equation (10) can be simplified as Equation (12), Figure 4 can be presented as Figure 5, which is the same as α = 1 condition.

$$R_1{i}_1+j\omega L_1{i}_1+\frac{i_1}{j\omega C_1}+j\omega M{i}_2=\frac{2}{\pi }{U}_{\mathrm{in}}\sin \omega t$$

(12)

$$R_{ac}=\frac{8}{{\pi }^2}{R}_L$$

(13)

According to Kirchhoff’s voltage law (KVL), the system dynamics of secondary is given by

$$R_2{i}_2+R_{ac}{i}_2+j\omega L_2{i}_2+\frac{i_2}{j\omega C_2}+j\omega M{i}_1=0$$

(14)

By grouping Equations (12) and (14), the system dynamics of SS/S SHRC are present as

$$\{\begin{array}{l}{R}_1{i}_1+j\omega L_1{i}_1+\frac{i_1}{j\omega C_1}+j\omega M{i}_2=\frac{2}{\pi }{U}_{\mathrm{in}}\sin \omega t\\ R_2{i}_2+R_{ac}{i}_2+j\omega L_2{i}_2+\frac{i_2}{j\omega C_2}+j\omega M{i}_1=0\end{array}$$

(15)

The input impedance of the primary impedance Z₁, the secondary impedance Z₂ and the reflected impedance Z_r are given by

$$\{\begin{array}{l}{Z}_1=R_1+Z_r+j\omega L_1+\frac{1}{j\omega C_1}\\ Z_2=R_2+j\omega L_2+\frac{1}{j\omega C_2}+R_{ac}\\ Z_r=\frac{{\omega }^2{M}^2}{Z_2}\end{array}$$

(16)

Equation (16) can be solved as

$$\{\begin{array}{l}{Z}_1=R_1+\frac{{\omega }^4{M}^2{C}_2^2(R_2+R_{ac})}{{\omega }^2{C}_2^2{(R_2+R_{ac})}^2+{({\omega }^2{L}_2{C}_2-1)}^2}-j(\frac{({\omega }^2{L}_2{C}_2-1){\omega }^3{M}^2{C}_2}{{\omega }^2{C}_2^2{(R_2+R_{ac})}^2+{({\omega }^2{L}_2{C}_2-1)}^2}+\omega L_1-\frac{1}{\omega C_1})\\ Z_2=R_2+R_{ac}+j(\omega L_2-\frac{1}{\omega C_2})\\ Z_r=\frac{{\omega }^4{M}^2{C}_2^2(R_2+R_{ac})}{{\omega }^2{C}_2^2{(R_2+R_{ac})}^2+{({\omega }^2{L}_2{C}_2-1)}^2}-j\frac{({\omega }^2{L}_2{C}_2-1){\omega }^3{M}^2{C}_2}{{\omega }^2{C}_2^2{(r_2+R_{ac})}^2+{({\omega }^2{L}_2{C}_2-1)}^2}\end{array}$$

(17)

Z₁, Z₂, and Z_r in Equation (17) are normalized as Z_1n (Z_1n = Z₁/Z₀), Z_2n (Z_2n = Z₂/Z₀), and Z_rn (Z_rn = Z_r/Z₀), respectively. The normalized impedance Z_1n, Z_2n, and Z_2n as a function of the normalized angular frequency ω_n (ω_n = ω/ω₀) and the normalized load resistance R_n (R_n = R_ac/Z₀) at k = 0.29 are further illustrated in Figure 6a–c, respectively. Where

$$Z_0=\sqrt{\frac{L_1}{C_{11}+C_{12}}}$$

(18)

$${\omega }_0=\frac{1}{\sqrt{L_1(C_{11}+C_{12})}}=\frac{1}{\sqrt{L_2{C}_2}}$$

(19)

From Figure 6b,c, Z_2n has a minimum value at the resonance frequency ω = ω₀, while Z_rn is the largest. In order to analyze Z_1n, Figure 6d describes the trend of Z_1n as a function of ω_n using a two-dimensional graph. It is shown in Figure 6a,d that the maximum transfer power, when Z_1n is the smallest, does not necessarily occur at the resonant frequency. When R_n > 0.5, maximum transfer power point is at the resonant frequency, while that of R_n = 0.2 or 0.25 is not. The frequency of the maximum transfer power bifurcates.

In order to make the IPT system operate at slightly inductive region which can be considered as resonance, it is necessary to analyze impedance angle of Z₁. The impedance angle curve of the system is constructed by Equation (17), as shown in Figure 7. The resonant frequency bifurcation, which means there is more than one frequency where the angle of Z₁ is zero, may occur when, for example, R_n < 0.3. Furthermore, when ω is in the near region of ω₀, the impedance of the converter is capacitive when ω > ω₀ and it is inductive when ω < ω₀, which are contrary to a typical transformer system. This paper will use R_n = 0.25 as one of the design parameters to further prove the frequency bifurcation phenomenon, a frequency slightly lower than ω₀ was chosen as ω to make it operate at slightly inductive region.

2.2. Resonance Analysis

When system operates in resonance, the imaginary part of Z₁ is equal to zero. From Equation (17), the resonant frequency can be solved as

$$f_0=\frac{{\omega }_0}{2\pi }=\frac{1}{2\pi \sqrt{L_1(C_{11}+C_{12})}}=\frac{1}{2\pi \sqrt{L_2{C}_2}}$$

(20)

Equation (20) presents the relationship between L₁, C₁₁, C₁₂, L₂, and C₂. When the designed resonant frequency is determined and coil structure is fixed, L₁, L₂ and f₀ are determined. In order to ensure the resonance state of the system, the values of C₁₁, C₁₂, and C₂ can be determined. The equivalent impedance of the secondary reflected to the primary is purely resistive. It can be seen from the Figure 7 and Equation (17) that, for different loads, the imaginary part of reflection impedance Z_r is zero. Thus the resonance state of IPT system is load-independent.

$$\mathrm{Re}(Z_r)=\frac{{\omega }_0{}^2{M}^2}{R_2+R_{ac}}$$

(21)

$$\mathrm{Im}(Z_r)=0$$

(22)

The primary input impedance is simplified as

$$Z_1=R_1+\frac{{\omega }_0^2{M}^2}{R_2+R_{ac}}$$

(23)

$$i_1=\frac{\frac{2}{\pi }{U}_{\mathrm{in}}\sin \omega t}{R_1+\frac{{\omega }_0^2{M}^2}{R_2+R_{ac}}}$$

(24)

The output power P_out can be calculated as

$$P_{out}=(\frac{\frac{2}{\pi }{\omega }_{0}M{U}_{\mathrm{in}}\sin \omega t}{R_1(R_2+R_{ac})+{\omega }_0^2{M}^2}{)}^2{R}_{ac}$$

(25)

From Equations (15)–(25) and the equivalent circuit as shown in Figure 5 and analysis in references [6,7,8,23], the proposed SS/S SHRC has the same characteristics as the FRC based on SS compensation topology. Capacitors C₁₁ and C₁₂, in series with the primary inductor L₁, play the same role as the primary compensation capacitor in full-bridge topology. Capacitance of the dual capacitors is equal to C₁₁ + C₁₂ as shown in Equation (4). Therefore, it is defined as SS/S (C₁₁C₁₂/C₂) compensation topology in this paper.

In the analysis above, C₁₁ and C₁₂ are considered as C₁, which are the same as in a FRC topology. But when they are analyzed independently, their operational characteristics are different. According to mode analysis in Figure 2, the bus current i_a is also different from that in the full-bridge topology. For capacitors C₁₁ and C₂₂, we can obtain

$$\frac{1}{C_{11}}{\displaystyle \int -i_{11}dt}+\frac{1}{C_{12}}{\displaystyle \int i_{12}dt}=U_{\mathrm{in}}$$

(26)

Substituting Equations (2)–(4) into (26), the voltage and the current of C₁₁ and C₁₂ are given by

$$\{\begin{array}{l}{u}_{C_{11}}=\frac{1}{2}{U}_{\mathrm{in}}-u_{C_1}\\ u_{C_{12}}=\frac{1}{2}{U}_{\mathrm{in}}+u_{C_1}\end{array}$$

(27)

$$\{\begin{array}{l}{i}_{11}=\frac{C_{11}}{C_1}{i}_1=\frac{1}{1+\alpha }{i}_1\\ i_{12}=\frac{\alpha }{1+\alpha }{i}_1\end{array}$$

(28)

The voltage of the capacitor C₁₁ is the DC component superimposed on the voltage of the equivalent capacitor C₁. The peak-to-peak values and voltage stresses of u_C11 and u_C12 are the same as u_C1. The operating characteristics of capacitor C₁₂ are almost the same. From the mode analysis, the bus current can be expressed as

$$\{\begin{array}{l}{i}_{\mathrm{a}}=i_{12}=\frac{\alpha }{1+\alpha }{i}_{1}0\le t<\frac{T}{2}\\ i_{\mathrm{a}}=i_{11}=\frac{1}{1+\alpha }{i}_1\frac{T}{2}\le t<T\end{array}$$

(29)

3. Efficiency Analysis

The losses of IPT system include device loss of the inverter, high-frequency impedance loss of primary and secondary coils, core heating loss, loss of radio frequency and magnetic field, and the other miscellaneous parameters in the circuit. The efficiency of IPT system can be expressed as

$$\eta =\frac{P_o}{P_i}={\eta }_c\cdot {\eta }_r\cdot {\eta }_m\cdot {\eta }_d$$

(30)

where η_c is the converter efficiency which is related to the switch conduction loss and diode conduction loss. η_r denotes the resonator efficiency mainly related to the high-frequency impedance of the coils. η_m is the core and magnetic field conversion efficiency, η_d is secondary rectification efficiency. The efficiency analysis of magnetic field, which has been explored extensively by previous studies [9,25], will not be analyzed in this paper. As shown in [5,6], the converter loss is one of the most important losses in the IPT system. This paper will focus on the converter efficiency η_c and coil conduction efficiency η_r.

3.1. Losses of SS/S SHRC and the Coils

The equivalent circuit model of the SHRC system for efficiency analysis is shown as Figure 5. When the system resonates, the converter operates in soft-switching mode. Thus, the switching loss can be regarded as zero. The loss of SHRC P_hbloss is mainly caused by the conduction loss of the switches. For each operation mode of SHRC shown in Figure 2 only one switch is on. Therefore, loss of the converter can be expressed as

$$P_{hbloss}=i_1{U}_q$$

(31)

Thus,

$${\eta }_c=1-\frac{P_{hbloss}}{P_i}.$$

(32)

where U_q is the forward conductive voltage of switch for IGBT. P_i is the input power of the system. The losses of the primary and secondary coils P_rloss can be presented as

$$P_{rloss}=i_1^2{r}_L+i_2^2{r}_L$$

(33)

Thus,

$${\eta }_r=1-\frac{P_{rloss}}{P_i}$$

(34)

3.2. Comparison of SS/S SHRC and FRC

In this section, the efficiency comparison of SHRC and FRC is presented. For fairness, the load and output power in both topologies are set as the same using the same devices. As shown in Figure 1a,b, the same capacitors, switches, coils, and diodes are used for the SHRC and the FRC. As described in Section 2.1 and shown in Figure 5, the equivalent circuits of the two topologies are the same. The output power P₂ can be calculated as

$$P_2=\frac{j^2{\omega }^2{M}^2{i}_1{}^2{R}_{ac}}{{(Z_2+R_{ac})}^2}$$

(35)

Equation (35) shows that the output power is related to the primary current i₁, M, and R_ac. If the transfer distance and the coil structure, which affect the value of M, are the same, output power of SHRC and FRC are only related to primary current i₁ powering the same load R_ac. If the input voltage of SHRC is twice of the input voltage of FRC, the primary currents of both are the same based on Equation (24) and analysis in [6,7,8,23]. By regarding the circuit parts inside the dotted rectangle in both Figure 1a,b as two-port network and if the input currents of both topologies are the same, the efficiency of these two networks are equal to each other. Besides the losses of the two-port networks, the remained losses are the converter losses including switch conduction loss, diode conduction loss and capacitor conduction loss. Similar as the analysis in Section 2.1, for every operational process of FRC two switches are on. The loss of FRC P_fbloss can be expressed as

$$P_{fbloss}=2i_1{U}_q$$

(36)

According to Equations (31) and (36),

$$P_{fbloss}=2P_{hbloss}$$

(37)

The loss of the full-bridge converter P_fbloss is twice that of the half-bridge converter P_hbloss.

However, to supply a same power to a same load with same voltage and current stresses of the resonant tank, the SHRC system requires a higher input voltage than the FRC system. This results in a double switch voltage stress than that of the FRC system. Nevertheless, this article focuses on the loss and efficiency comparison of the two systems, regardless of that the switches in FRC can stand a twice higher voltage stress than they actually faced, which is not economical. To seek the balance between simpler circuit structure, higher efficiency, lower input voltages, and economical efficiency need to be further explored.

In summary, if the input voltage of SHRC is twice of FRC, which results in twice voltage stresses for switches in SHRC, the primary current i₁ of SHRC and FRC are the same. The same i₁ guarantees the same output power, the same coils, and the same secondary efficiency of both IPT systems. In addition, the loss of SHRC is half of the FRC losses at the same i₁. It is shown that the SHRC IPT system is more efficient than FRC IPT system under these conditions.

4. Simulations and Experiments

To verify the theoretical analysis proposed in this paper, a Saber simulation was established according to Figure 1a. A 1.5 kW prototype of SHRC with 170 mm air gap was built as shown in Figure 8. The parameters in the simulation and the prototype are shown in

Table 1. Parameters for SHRC and FRC 1.5 kW IPT systems.

Symbol	Circuit Component	Value
Uin1	SHRC input voltage	0–200 V
Uin2	FRC input voltage	0–100 V
L1	primary inductance	175 μH
L2	secondary inductance	175 μH
C11 + C12	primary capacitance	880 nF
C2	secondary capacitance	880 nF
rL1	primary coil resistance	165 mΩ
rL2	secondary coil resistance	165 mΩ
M	mutual inductance	50.5 μH
RL	load resistance	3.33 Ω

. IGBT switch model 2MBI75N-060 was used as the switches, which have a collector-emitter saturation voltage of 2.8 V at 75 A. The primary and secondary inductors were wound with Litz wires in a same manner as shown in Figure 9. Three 100 Ω resistors which were parallel with each other were used as the resistive load of the IPT system. Power analyzer WT500 was used to measure input voltages/currents, output voltages/currents, losses of SHRC, and FRC.

4.1. Operation of the Proposed SS/S SHRC

Based on the parameters of Table 1, the coupling coefficient k is 0.29, the normalized load resistance R_n is 0.25, and the resonant frequency f₀ is 12.8 kHz. Frequency bifurcation would occur according to the analysis in Section 2 and Figure 7. In order to verify the frequency bifurcation, the operational frequency 12.5 kHz, which is close to and less than the resonant frequency 12.8 kHz was chosen in the simulations and experiments. At the input voltage of 200 V, the performance of SHRC was shown by simulation in Figure 10 and validated by experiments as shown in Figure 11. In Figure 10a, as shown in the circled moment, the primary current i₁ is still positive at the switching moment. The phase of the current lags behind the phase of the driving voltage V_GE, which means the converter operated at the inductive region with lower frequency as the frequency bifurcation indicates. Simulation waveforms of i_a for five different α were presented in Figure 10b in five different colored curves. The first peak of i_a is α times of the second peak coinciding with Equation (29). When C₁₁ is equal to C₁₂ (α = 1), the peak value of the bus current i_a achieves a minimum at 13.6 A.

The operational waveforms of different α by experiments were presented as Figure 11. The driving voltage of S₂ is shown in the yellow line, the bus current i_a is in blue, primary current i₁ is in green, and voltage waveform of C₁₂, u_C12, is in red. As shown in Figure 11, each switch operates at nearly 50% duty cycle, including a 2 μs dead-time. The system works in resonance state. The peak of the primary resonant current i₁ is 26.2 A. The peak-to-peak voltage of the C₁₂ is 744 V, and the average is 100 V, which is half of U_in1. According to the waveforms of i_a in Figure 11, the value of the first peak of i_a is α times of the second peak, verifying both the theoretical analysis and the simulation results. From Figure 10a and Figure 11b, by comparing the operational waveforms, and the experimental results were consistent with the simulations. Since the influences of parasitic parameters are ignored in the simulation, waveforms of simulation are larger than the experiment. Meanwhile, the deviation is within the allowable range. In general, the simulation results and the experimental waveforms of i_a, i₁, u_C12 verify the analysis in Section 2, as shown in Equations (20)–(29).

4.2. Soft-Switching

Since the working procedures of the two switches of SS/S SHRC are complementary with dead-time, only the soft switching state of S₁ was analyzed. As shown in Figure 12, the yellow curve is the driving voltage of S₁, the green curve is the primary current i₁, and the red curve is V_CE of S₁. At t₀, D₁ is in conducting state, V_CE is 0, S₁ is turned on, and i₁ is zero. Thus, S₁ is turned on in ZVS and ZCS state. At t₁, S₁ is turned off. The i₁ is approximately zero. Because of the effect of parasitic capacitor, which is parallel to S₁, V_CE rises from zero to U_in. So, S₁ turns off in ZVS and quasi-ZCS state.

4.3. Comparison between SHRC and FRC

For a fair comparison, FRC IPT system was built with the same device as SHRC IPT system. C₁₁, in parallel with C₁₂, are the primary compensate capacitors which are shown in Figure 13. The experimental waveforms of FRC IPT system were presented in Figure 14. The bus current i_a, peak to peak capacitor voltage u_C12, primary current i₁, and the resonant frequency are exactly the same as SHRC shown in Figure 10 and Figure 11. To analyze the difference between the SHRC and FRC IPT system, comparing Figure 11 with Figure 14, only the bus current i_a and the average of u_C12 are different. The results validate Section 2 analysis that the proposed SS/S SHRC has the same operational characteristics as the FRC.

For the converter efficiency comparison, in order to ensure the universality, a SHRC system with α = 3 was compared with the FRC. Based on the parameters in Table 1, the losses of SHRC and FRC at different output power from 400 W to 1500 W were measured by experiments and illustrated in Figure 15. The input voltage of SHRC changed from 0 V to 200 V and that of FRC from 0 V to 100 V. When the output power was 1500 W, the input voltage of SHRC was 200 V and that of FRC was 100 V verifying the analysis in Section 3.2. For a system efficiency comparison, the total efficiency is 91.6% of the SHRC IPT system, while it was 89.3% of FRC IPT system at 1500 W. Both were measured from the two experimental prototypes. At the output power of 1500 W, the coil loss and converter loss of the two systems were presented in Figure 16 for comparison.

In Figure 15, the left coordinate is the loss percentage of SHRC and FRC, whereas the right coordinate is the ratio of FRC loss to SHRC loss. It is shown that the SHRC loss (curve in green) and FRC loss (curve in blue) decrease with the increasing of transferring power in low power range, then the decreasing speed gradually slows down. According to Equation (37), the ratio of FRC loss to SHRC loss is 2. In Figure 15, it is slightly smaller than 2. The reason may because the loss of the contact resistance and other parameters of the device, which can be considered as a fixed proportion is ignored in the efficiency in Section 3. From Figure 16, the coil losses of both converters are almost the same, validating the two-port network efficiency analysis in Section 3. From the experimental results, it is verified that the SHRC IPT system is more efficient than the FRC IPT system by comparing the losses.

5. Conclusions and Discussion

In this paper, an SS/S compensated symmetrical half-bridge resonant converter for the inductive power transfer is presented. The main contributions of this paper are as followed:

1. Based on the mutual inductance model and the first harmonic approximation method, the working procedure and system parameters of the proposed converter are analyzed in detail and compared with an FRC system. In the proposed system, the pair of resonant capacitors with different capacitance ratios were applied and theoretically compared.

2. The frequency bifurcation of proposed IPT system is theoretically analyzed by impedance analysis method. In order to verify the frequency bifurcation phenomenon, an operating frequency of 12.5 kHz close to and lower than the resonant frequency of 12.8 kHz was applied to the system.

3. Simulations and experiments are done to verify the theoretical analysis. The losses and efficiencies of the proposed system with the FRC system. To supply a same power to a same load with same voltage and current stresses of the resonant tank, the SHRC system achieves a higher efficiency than the FRC system, although the SHRC system requires a higher input voltage than the FRC system. Experimental results show that the loss of SHRC was 39.7 W while that of FRC was 79.4 W, and the total efficiency is 91.6% of the SHRC IPT system compared with 89.3% of the FRC IPT system at 1500 W.

On the other hand, the proposed system will suffer twice the voltage stress of the switches in the primary compared to those of the FRC system. To seek a balance between simpler circuit structure, higher efficiency, lower input voltages, and economical efficiency need to be further explored. Comparison of the proposed topology with other converter topologies will also be explored in the future work.