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Energies 2019, 12(11), 2139; https://doi.org/10.3390/en12112139

Article
A Modified Partial Power structure for Quasi Z-Source Converter to Improve Voltage Gain and Power Rating
1
Department of Electrical and Electronics Engineering, Shiraz University of Technology, Shiraz 71557-13876, Iran
2
Department of Electrical Engineering, Technical University of Catalonia, 08222 Barcelona, Spain
3
Department of Electrical Engineering and Automation, Aalto University, 02150 Oslo, Finland
*
Authors to whom correspondence should be addressed.
Received: 18 April 2019 / Accepted: 31 May 2019 / Published: 4 June 2019

Abstract

:
Employing partial power processing (PPP) technique for quasi Z-source converter (QZSC) a new structure of the converter is presented. Using PPP technique although eliminates electrical insolation, but permits reducing voltage and current stress at the semiconductors, if compared with full power proposals. In this work, two PPP structures are discussed: A first one, similar to the basic topology, where the output voltage of the power converter is in series with the input voltage; and a second one, where the output is in series with the capacitor of the QZSC. This minor modification, which requires no extra elements, improves the power rating, voltage gain, and requires a lower transformation ratio. An experimental prototype of the proposed converter has been tested and the results are compared with other implementations, permitting to validate the theoretical analysis as well as the advantages that this proposal provides.
Keywords:
partial power processing; quasi Z-source converters; high step up converters

1. Introduction

As one of the main backbones of the power electronics industry an uncountable number of research works have been devoted to the study and design of high efficiency, low power rating, and low cost DC/DC converters for different applications such as: PV, electrical equipment, electrical vehicles, energy storage, and communication systems. Furthermore, many researches have been made to improve the performance of conventional converters. One recent technique that is giving rise to good results is based on partial power processing (PPP) [1,2]. The basic principle of this technique is based on providing part of the input power directly to the output, meanwhile the rest is processed by the converter [1,2,3,4,5,6,7,8,9,10,11,12,13]. The main advantage of this technique is to level down the power rating of the elements as less power is handled by the converter. This is achieved without requiring to add or remove any element.
The main feature of the PPP technique is found in the connection between the source and the load [1]. The layout available in Figure 1 shows the two main topologies. The first type (Figure 1a), which is appropriate for boosting, has an output voltage equals to the sum of the source voltage and the output voltage of the converter [1,3,4,5,6,7]. The second one, shown in Figure 1b, is appropriate for buck application, and builds the output voltage taking the difference between system and converter input voltages [8,9].
Isolation is a big challenge in PPP applications [1,2,10]. However non-isolated converters can be considered in some cases [3,4,5]. For instance, in [11] a simple and commercially available non-isolated partial power (PP) boost converter for PV systems was integrated. Based on [12], the performance of this converter does not follow the PP method and acts like a full power converter (FPC). As described in [1,3,4], if the average current passing through the direct power path is zero, the system’s performance is similar to a full power processing converter. A dual input non-isolated partial power converter (PPC) was introduced in [13,14,15], which employs two similar PPC.
On the other hand, impedance network converters are widely investigated for low voltage renewable energy source applications. The main advantage of these converters lays on the fact that they can provide a high voltage step up; and the other merit is short circuit immunity [16,17,18,19,20,21,22,23,24,25]. The PPP technique can be applied to these types of converters in order to improve their performance. Z-source converter (ZSC) which is the first proposed structure of impedance network converters, includes an inductor and a capacitor that handle the charge and discharge cycles to provide the maximum power conversion ability during the shoot through time interval [19]. However, quasi ZSC (QZSC) which has been chosen in this paper, provides some advantages compared to ZSC, including continuous input current and wider boosting range [20,25].
After defining the topology different types of switching methods can be implemented such as: Using only one switch to shoot through switching, using two or three leg H-Bridge switching topology, and push-pull switching topology [21] (Figure 2). In this case reducing the number of switches and implementing a simple control using push-pull switching, have been prioritized in the selection of the proposed converter [22].
In this paper the isolated QZSC has been used with push pull switching method in the middle, as shown in Figure 2a. Two structures of PPC for this converter are presented: PP-QZSC (Figure 2b) and modified PP-QZSC (Figure 2c). The first type is based on the basic structure of PPP technique (as depicted in Figure 1a), while the structure is revised in the second one and this provides reduced voltage stress and higher voltage gain.
One of the main contributions of this paper is the use of the PPP technique for improving the voltage gain of the full power QZSC (FP-QZSC). The proposed method permits achieving a voltage gain 20% higher than basic PPP system.
In order to evaluate the performance of the modified PP-QZSC, its performance will be compared to traditional FP-QZSC and basic PP-QZSC in terms of efficiency, voltage and current stress, and voltage gain in continuous conduction mode (CCM) of operation.

2. Operation Principles and Topology Analysis of the Proposed Converter

The modified PP-QZSC in Figure 2c follows the switching sequence shown in Figure 3.
It should point out that in order to guarantee a good operation of the proposed converter, the duty cycle D t should be within 50 % < D t < 75 % and hence the shoot-through duty cycle D s is D s = 2 D t 1 . As by short circuiting the transformer magnetically the shoot through situation happens, the transformer design should be very accurate [22]. In this study the transformer magnetizing inductance LM, is neglected.
Considering the sequence described in the figure, three modes of operation can be defined for modified PP-QZSC (Figure 2c). The equivalent circuits corresponding to these modes are shown in Figure 4. In the proposed converter the output voltage is the sum of the voltages at C 1 and C 4 . Therefore, the output voltage can be determined as follows:
V o u t = V C 1 + V C 4
V C 1 = 1 D s 1 2 D s V i n
V C 4 = 2 n 1 2 D s V i n
where, Vout and Vin is the output and input voltages and Ds stands for shoot through duty cycle. Substituting (1) and (2) into (3) and based on D t or D s , the converter voltage gain can be expressed as:
V o u t V i n = 2 n + 1 D s 1 2 D s = 2 ( n + 1 D t ) 3 4 D t
where, n is the transformer turns ratio and Dt is the duty cycle of switches. The same analysis can be considered for basic PP-QZSC and FP- QZSC which is given by (5) and (6) respectively.
V o u t V i n = 2 n + 3 4 D t 3 4 D t
V o u t V i n = 2 n 3 4 D t
Figure 5 shows the voltage gain versus duty cycle for similar transformer turn ratio, n = 1. As it can be realized, the proposed converter with a slight difference, provides a higher voltage gain. This is translated into a lower voltage stress for all the elements, specifically for the voltage stress in the semiconductors. Moreover, the proposed converter is compared to other PP topologies such as: Boost, Full Bridge, and Flyback PPC. This figure shows the merit of PPP technique for impedance network converters.
The QZS network part of the circuit only processes two modes of operation: Shoot-through mode and non-Shoot-through mode. So, the inductor currents in steady state can be derived based on the following two modes of operation:
Shoot-through mode: In this stage the diode D 1 is turned off and the DC link terminals are magnetically short circuited, therefore the following equations referring to Figure 4a can be written:
i C 1 = i L 2 i o u t i C 2 = i L 1 = i i n
where iin, iout, iC, and iL are input, output, capacitor, and inductor currents respectively.
Non-shoot-through mode: Based on Figure 4b or Figure 4c, the diode D 1 is turned on and inductors currents are induced to DC link terminals, so;
{ i C 1 = i D 1 i L 2 i o u t i C 2 = i D 1 i i n
where iD1 is the D1 current. According to the capacitor Amp-second balance law and shoot through duty cycle, the inductor’s steady state current can be calculated as:
{ I L 1 = I i n = 2 n + 1 D s 1 2 D s V o u t R o u t = 2 ( n + 1 D t ) 3 4 D t V o u t R o u t I L 2 = I i n I o u t = 2 n + D s 1 2 D s V o u t R o u t = 2 n + 2 D t 1 3 4 D t V o u t R o u t

3. Comparison and Evaluation of Topologies

In the following, three discussed converters are compared regarding several criteria in steady state operation. The averaged model of QZSC and PP-QZSC is discussed in [26].

3.1. Voltage and Current Stress Analysis

The voltage and current stress of the semiconductor devices are shown in Table 1. Current stress equations of the converters are identically except for D1 current stress, so overall the modified PP-QZSC has lower current stress compared to others. Also the voltage stress of the modified PP-QZSC is reduced compared to FP-QZSC and basic PP-QZSC. Both the basic and the modified PP-QZSC have less current and voltage stresses compared to FP-QZSC. Figure 6 illustrates a comparison of the switch’s voltage stress as a ratio of input voltage based on the converter voltage gain. From this figure it can be concluded that having less voltage stress in the switches results in lower switch built in conducting resistance. Also, the voltage stress of other elements such as diodes are reduced. Lower voltage stress results in lower power rating of the elements, for instance low power rated passive element like capacitor. Generally, reduced voltage and current stress of the elements, specifically active elements, can be effective for enhancing the converter’s cost.

3.2. Element Design

The full bridge, half bridge, and push-pull switching topologies help the voltage and current stress to be reduced compared to single switching topologies [21]. The steady state analysis of inductors current ripples and capacitors voltage ripples indicates the size of passive elements of the converters, therefore;
{ L 1 = 2 ( 2 D t 1 ) ( 1 D t ) 4 n f s V o u t Δ I L 1 L 2 = 2 ( 2 D t 1 ) ( 1 D t ) 4 n f s V o u t Δ I L 2
{ C 1 = ( n + 1 D t ) ( 2 D t 1 ) ( 3 4 D t ) f s R o u t V o u t Δ V C 1 C 2 = ( n + 1 D t ) ( 2 D t 1 ) ( 3 4 D t ) f s R o u t V o u t Δ V C 2 C 3 = 4 n + 1 2 n f s R o u t V o u t Δ V C 3 C 4 = D t 2 f s R o u t V o u t Δ V C 4
where, Δ i L is the inductor current ripple, Δ V C is the capacitor voltage ripple and fs is the switching frequency. The output voltage ripple for FP-QZSC and basic PP-QZSC are Δ V C 4 but for the modified PP-QZSC is the summation of ΔVC1 and ΔVC4.

3.3. Comparison

In terms of comparison, some parameters have been considered such as voltage gain, voltage and current stress, voltage ripple of capacitors, current ripple of inductors, power losses, transformer turn ratio, number of used elements, and efficiency. Therefore, some non-idealities of elements such as: Inductor resistance, transformer resistance, switch built in conducting resistance, and diode conducting voltage drop are considered. Also, converter no-load power loss which is caused by transformer or inductor core loss has been considered as a constant factor of output power. Other non-idealities such as capacitor equivalent series resistance (ESR) or diode resistance are neglected. Table 2 shows the converters specifications and the amount of non-ideal elements which has been considered in terms of simulation comparison.

3.4. Voltage Gain Comparison

The effect of non-idealities is translated into power losses increase and reduction of the output voltage that results in higher duty cycle for a determined value of input and output voltage. Figure 7 illustrates the output voltage comparison versus duty cycle while the input voltage is the same. As it can be seen, the required duty cycle for the proposed PPP converter at a specific output voltage is lower than in other converters.

3.5. Losses Comparison

Figure 8 shows the conducting dissipation power comparison between FP-QZSC, basic PP-QZSC, and the modified PP-QZSC. Both presented PPCs have lower power losses compared to FP-QZSC.
The efficiency difference between the basic and the proposed PP structures is related to current difference passing through L1. The power losses difference between the basic PP-QZSC and the modified PP-QZSC, where the basic converter dissipates less power, as this parameter is highly dependent on the value of L1 and D1. These two parameters are the structural difference between the presented converters. In the QZSC network of the modified PP-QZSC, L1 and D1 currents are equal to Iin but in the basic PP-QZSC this value is lower, being Iin-Iout the overall current that go through the circuit. Other elements performances are almost similar in the basic PP-QZSC and the modified PP-QZSC, because they handle Iin-Iout which give rise to similar power losses. Therefore, in proposed model these elements process the whole input power which in this case causes higher losses than in the basic converter. In terms of power losses, the switching losses are also considered. Based on parasitic elements, which are mentioned before and referring to Table 1 and Table 2, the power losses of the inductors, diodes, switches, and transformer are given by (12), (13), (14), and(15) respectively. These equations are calculated based on switching duty cycle, Dt. In order to compute the losses, RMS values of each current are calculated. With a small approximation, diodes, switches, and transformer current ripples are considered to be inductor current ripple. The inductors power losses value is based on their RMS current, which is calculated as follows,
P L = R L 1 I L 1 , r m s 2 + R L 2 I L 2 , r m s 2 { I L 1 , r m s = I L 1 , a v g 1 + 1 3 ( Δ i 2 I L 1 , a v g ) I L 2 , r m s = I L 2 , a v g 1 + 1 3 ( Δ i 2 I L 2 , a v g )
where PL, IL1,rms, IL2,rms, and Δi are the overall inductor’s losses, L1 and L2 the average current and current ripple which can be obtained in (14), respectively. Also, diodes and switches power losses are calculated based their current RMS values, so
P D = ( I D 1 , a v g + I D 2 , a v g + I D 3 , a v g ) V d
PD is the sum of diodes conduction loss and is calculated based on the average current. Also, ID1,rms, ID2,rms, and ID3,rms are:
{ I D 1 , a v g = 2 n + 1 D s 1 2 D s . V o u t R o u t I D 2 , a v g = I D 3 , a v g ( 1 D s ) ( 2 n + D s ) 2 n ( 1 2 D s ) . V o u t R o u t
PS(cond) are the conduction losses in the switches (S1 and S2). IS,rms(Cond) is the RMS value of the current at the switch and is calculated as:
{ P S 1 ( C o n d ) = P S 2 ( C o n d ) = 1 2 P S ( c o n d ) P S ( c o n d ) = 2 R o n I S , r m s ( C o n d ) 2
PS(cond) are the conduction losses of the switches (S1 and S2). Likewise, IS,rms is the RMS value of the current at the switch and it can be calculated as:
I s , r m s = 11 2 D t 24 Δ i 2 + ( 2 D t 1 ) I 1 2 + ( 1 D t ) I 2 2 ,
where I1 and I2 are the DsTs and (DtDs)Ts time intervals average currents, as it can be concluded from Figure 3. The transformer’s primary and secondary windings losses are determined according to the switches and diode D2 and D3 currents, respectively. According to Figure 4a,b the transformer primary windings conduction is based on switches turn on time interval, DtTs and the secondary winding is calculated in (1 − Ds)Ts. Therefore;
P w i n d i n g = P w i n d , p r i 1 + P w i n d , p r i 2 + P w i n d , sec { P w i n d , p r i 1 = P w i n d , p r i 2 = R w I S , r m s , ( C o n d ) 2 P w i n d , sec = R w I D 2 , r m s 2
Pwinding is the sum of the transformer primary and secondary power losses. The switching power loss (PS(switching)) due to non-ideal turn-on and turn-off is illustrated by (18).
{ P S ( s w i t c h i n g ) = 2 ( α o n + α o f f ) ( V s w I s w ) f s w α o n = α o f f = 0.5 ( τ r i s e + τ f a l l )
α o n and α o f f are turn on and turn off switching times respectively which can be found in the datasheet. Also V s w and I s w are the average voltage and current stress of the switches, which can be obtained from Table 1. Figure 9 shows the MOSFET switches power loss comparison based on (17) and (18), which the proposed converter has less switch power dissipation.

3.6. Efficiency Comparison

Integrating PPP technique into any converter does not necessarily mean an improvement in the efficiency [1]. In this case integrating PPP technique improved both basic proposed models compared to full power converter. However, the proposed converter efficiency is lower than basic structure. The structural difference between basic and proposed converters has been mentioned which results in efficiency difference as well. Efficiency of the proposed model highly depends on operating points and transformer turn ratio, which in some cases the modified PP-QZSC efficiency can be improved compared to the basic model. The relationship between these three converters efficiencies which have been listed in Table 3. Since the QZSC efficiency ηQ1 is always smaller than one, the overall efficiencies of the basic PP-QZSC and the modified PP-QZSC are higher than the FP-QZSC. If the individual converter efficiencies are similar, the relation of converters efficiencies are ηS3 > ηS2 > ηS1 which is shown in Figure 10. Moreover, the full power converter duty cycle is higher than the other two converters. Also, Vout/VC4 ratio in the modified PP-QZSC is limited to a range between 1.25 and 1.5 because of switching duty cycle which is a range between 50% to 75%. Individual system efficiency of the proposed PPP system, ηQ3 is dependent on this ratio. If Vout/VC4 gets larger, ηQ3 gets lower, therefore ηS3 is always lower than one. Figure 11 shows the efficiency comparison based on the output power.
It should be noticed that, the experimental efficiency curve in 22, shows that maximum efficiency of FP-QZSC can go beyond 97% which is different from our measurement. The efficiency curve of two converters may be compared only if all the conditions are the same. The parameters which affect the converter efficiency are: MOSFET conduction resistance and switching loss, diode forward voltage, winding resistance, and converter operation points. In two prototypes of the converter, these values may differ and therefore different efficiency values can be calculated.

4. Simulation and Experimental Results and Discussion

The laboratory low power 200 W prototype of the proposed converter, shown in Figure 12, has been built to validate the theoretical analysis and simulation results. The prototype component values are shown in Table 2. In this section the simulation results and experimental results are shown and compared.
The switching gate signals for two switches are shown in Figure 13. In order to generate the desired output voltage, the switching and shoot though duty cycles are adjusted to Dt = 0.6 and Ds = 0.2 (according to (4)). The switching frequency is 40 kHz. All the experimental tests were conducted under CCM operation of the converter, as DCM does not represent a representative operating point. Comparing simulation and experimental results it can be seen that both match quite well. On the other hand, considering two separate shoot through time intervals (equals to 0.1Ts) during a switching cycle, the voltage ripple of C1, and C2 have a frequency equals to 2fs (Figure 14c,d). The frequency voltage ripple of C3 and C4 are the same as fs (Figure 14e,f). The experimental output voltage waveform is also shown in Figure 14a. As mentioned before, the output voltage ripple is the sum of C1 and C4 voltage ripples, which can be seen in Figure 14b.
The waveforms of IL1 and IL2 are shown in Figure 15. The small current ripples insure the CCM operation of the converter. The only difference between the two current waveforms is that the IL2 is less than inductor IL1 as IL2 = IL1Iout. The experimental and simulation results for transformer primary and secondary voltages are shown in Figure 16. The primary and secondary voltage during shoot through mode is zero which shows the magnetically short circuit of the transformer. In order to compare the performance of the three discussed converters, three converters are made and several tests are done in different operating modes.
In Figure 17, the efficiency of the converters for different input voltages with constant switching duty cycle of 0.6 are sketched also compared with simulation resulted efficiency. The result shows higher efficiency of the basic PP-QZSC as predicted in Section 3. As discussed before, the semiconductor loss is lower which result in a smaller cooling system and improves the reliability of the system.

5. Conclusions

This paper presents a modified QZSC using PPP technique. Compared to full power converter, partial power converter shows higher efficiency and lower voltage and current stress. Although the modified PP-QZSC had a rather lower efficiency by 1%, but the voltage stress of the switches decrease by 25%. High boost capability, lower voltage and current stress, improved efficiency and lower cost considering small duty cycle, and small turn ratio of the transformer are the proposed and basic PPP converters features. Higher boosting mode and reduced voltage stress are the proposed PPP QZSC advantages compared to basic PPP structure. The operating performance of the proposed converter was simulated and experimentally tested to validate the theoretical analysis. Due to lower power handled by the PPP converters, which is a remarkable feature, and considering the results and performance obtained, the proposed converter is promising to be used in PV systems, as a partial power inverter would give rise to a lower cost and size of the power processing stage.

Author Contributions

All persons who meet authorship criteria are listed as authors, and all authors certify that they have participated sufficiently in the work to take public responsibility for the content, including participation in the concept, design, analysis, writing, or revision of the manuscript. Furthermore, each author certifies that this material or similar material has not been and will not be submitted to or published in any other publication before its appearance in the Applied Sciences, MDPI. All in all, the contribution of all authors is almost equal.

Funding

This research received no external funding.

Conflicts of Interest

The authors declare no conflict of interest.

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Figure 1. Basic structure of partial power processing (PPP system): (a) Input parallel output series, (b) Input series output parallel.
Figure 1. Basic structure of partial power processing (PPP system): (a) Input parallel output series, (b) Input series output parallel.
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Figure 2. Equivalent circuits of the converters: (a) Full power quasi Z-source converter (QZSC), (b) Basic PPP QZSC, (c) Proposed PPP QZSC.
Figure 2. Equivalent circuits of the converters: (a) Full power quasi Z-source converter (QZSC), (b) Basic PPP QZSC, (c) Proposed PPP QZSC.
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Figure 3. Equivalent circuits of the converters: (a) Full power QZSC, (b) Basic PPP QZSC, (c) Proposed PPP QZSC.
Figure 3. Equivalent circuits of the converters: (a) Full power QZSC, (b) Basic PPP QZSC, (c) Proposed PPP QZSC.
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Figure 4. Operation modes of the proposed PPP QZSC: (a) Shoot-through mode, (b) Non-shoot-through and S 1 is ON, S 2 is off, (c) Non-shoot-through and S 2 is ON, S 1 is off.
Figure 4. Operation modes of the proposed PPP QZSC: (a) Shoot-through mode, (b) Non-shoot-through and S 1 is ON, S 2 is off, (c) Non-shoot-through and S 2 is ON, S 1 is off.
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Figure 5. Voltage gain versus duty cycle for three discussed converters and PPP structures of Flyback, H-bridge, and Boost converters (Flyback and Boost have similar waveform).
Figure 5. Voltage gain versus duty cycle for three discussed converters and PPP structures of Flyback, H-bridge, and Boost converters (Flyback and Boost have similar waveform).
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Figure 6. MOSFET voltage stress/input voltage versus voltage gain for FP-QZSC, basic PP-QZSC, and modified PP-QZSC (Transformer turn ratio = 1).
Figure 6. MOSFET voltage stress/input voltage versus voltage gain for FP-QZSC, basic PP-QZSC, and modified PP-QZSC (Transformer turn ratio = 1).
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Figure 7. The effect of non-idealities on output voltage waveform versus duty cycle for the three discussed converters.
Figure 7. The effect of non-idealities on output voltage waveform versus duty cycle for the three discussed converters.
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Figure 8. Power Loss Comparison: Left bar) Full power QZSC, Middle bar) Basic PPP QZSC, Right bar) Proposed PPP QZSC.
Figure 8. Power Loss Comparison: Left bar) Full power QZSC, Middle bar) Basic PPP QZSC, Right bar) Proposed PPP QZSC.
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Figure 9. Switch power loss versus output power for the three discussed converters.
Figure 9. Switch power loss versus output power for the three discussed converters.
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Figure 10. System efficiency versus individual converter efficiency.
Figure 10. System efficiency versus individual converter efficiency.
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Figure 11. Efficiency versus output power for the three discussed converters.
Figure 11. Efficiency versus output power for the three discussed converters.
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Figure 12. Laboratory prototype of the proposed converter.
Figure 12. Laboratory prototype of the proposed converter.
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Figure 13. Switch gate signals S 1 and S 2 (Volt/div = 5 V, Time/div = 10 µs). Dt = 0.6 and Ds = 0.2.
Figure 13. Switch gate signals S 1 and S 2 (Volt/div = 5 V, Time/div = 10 µs). Dt = 0.6 and Ds = 0.2.
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Figure 14. Experimental and simulation result waveforms: (a) Input and output voltage (Volt/div = 50 V, Time/div = 10 µs), (b) Input and output voltage (c) Capacitor C 1 voltage, (d) Capacitor C 2 voltage, (e) Capacitor C 3 voltage and (f) Capacitor C 4 voltage.
Figure 14. Experimental and simulation result waveforms: (a) Input and output voltage (Volt/div = 50 V, Time/div = 10 µs), (b) Input and output voltage (c) Capacitor C 1 voltage, (d) Capacitor C 2 voltage, (e) Capacitor C 3 voltage and (f) Capacitor C 4 voltage.
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Figure 15. Simulation and experimental results for inductor currents: (a) experimental results for IL1 (Amp/div = 1 A, Time/div = 10 µs), (b) simulation results for IL1, (c) experimental results for IL2 (Amp/div = 1 A, Time/div = 10 µs) and (d) simulation results for IL2.
Figure 15. Simulation and experimental results for inductor currents: (a) experimental results for IL1 (Amp/div = 1 A, Time/div = 10 µs), (b) simulation results for IL1, (c) experimental results for IL2 (Amp/div = 1 A, Time/div = 10 µs) and (d) simulation results for IL2.
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Figure 16. Simulation and experimental results for inductor currents: (a) experimental results for IL1 (Amp/div = 1 A, Time/div = 10 µs), (b) simulation results for IL1, (c) experimental results for IL2 (Amp/div = 1 A, Time/div = 10 µs) and (d) simulation results for IL2.
Figure 16. Simulation and experimental results for inductor currents: (a) experimental results for IL1 (Amp/div = 1 A, Time/div = 10 µs), (b) simulation results for IL1, (c) experimental results for IL2 (Amp/div = 1 A, Time/div = 10 µs) and (d) simulation results for IL2.
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Figure 17. Experimental result for efficiency comparison of the three discussed converters.
Figure 17. Experimental result for efficiency comparison of the three discussed converters.
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Table 1. Voltage and current stress comparison.
Table 1. Voltage and current stress comparison.
ConverterVoltage StressCurrent Stress
SwitchesFull Power QZSC [22] 1 n · V o u t 2 n 1 2 D s · V o u t R o u t
Basic PPP QZSC 2 2 n 1 2 D s 1 V o u t 2 n 1 2 D s 1 · V o u t R o u t
Proposed PPP QZSC 2 2 n + 1 D s 2 V o u t 4 n + 1 2 ( 1 D s 2 ) · V o u t R o u t
Diode D1Full Power QZSC 1 2 n · V o u t 2 n V o u t ( 1 2 D s ) ( 1 D s ) R o u t
Basic PPP QZSC 1 2 n + 1 2 D s 1 V o u t 2 n V o u t ( 1 2 D s 1 ) ( 1 D s 1 ) R o u t
Proposed PPP QZSC 1 2 n + 1 D s 1 V o u t ( 2 n + 1 D s 2 ) V o u t ( 1 2 D s 2 ) ( 1 D s 2 ) R o u t
Diode D2 & D3Full Power QZSC V o u t 2 1 2 D s · V o u t R o u t
Basic PPP QZSC 2 n 2 n + 2 2 D s 1 V o u t 2 1 2 D s 1 · V o u t R o u t
Proposed PPP QZSC 2 n 2 n + 1 D s 2 V o u t 2 n + D s 2 n ( 1 2 D s 2 ) · V o u t R o u t
ConverterInductor L1Inductor L2
Current StressFull Power QZSC 2 1 2 D s · V o u t R o u t 2 1 2 D s · V o u t R o u t
Basic PPP QZSC 2 1 2 D s 1 · V o u t R o u t 2 1 2 D s 1 · V o u t R o u t
Proposed PPP QZSC 2 n + 1 D s 2 1 2 D s 2 · V o u t R o u t 2 n + D s 2 1 2 D s 2 · V o u t R o u t
Table 2. Prototype and Simulation parameters.
Table 2. Prototype and Simulation parameters.
ParametersSymbolsValue/Part no.
Output VoltageVout90 V
Input VoltageVin20 V
Switching Frequencyfs40 kHz
Duty CycleDt0.6
Transformer turn ration1:1:1
Primary and secondary resistanceRwp, Rws0.01 Ω
InductanceL1, L2200 µH
Inductor resistanceRL1, RL20.01 Ω
Diode Forward VoltageVd0.98 V
capacitanceC1, C2, C3, C4100 µF
Switch on resistanceRon0.18 Ω
Switch S1, S2IRF640N
Table 3. Efficiency comparison of Full power, basic PPP, and proposed PPP QZSC.
Table 3. Efficiency comparison of Full power, basic PPP, and proposed PPP QZSC.
ConverterIndividual Converter Output VoltageIndividual Converter EfficiencySystem Efficiency
Full power QZSC V o u t η Q 1 η S 1 = η Q 1
Basic PPP QZSC V o u t V i n η Q 1 η S 2 = V o u t V C 4 + η Q 2 · V i n · η Q 2
Proposed PPP QZSC V o u t V C 1 η Q 3 η S 3 = V o u t V C 4 · η Q 3
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