1. Introduction
With the demand of transferring power without physical contact, wireless power transfer (WPT) technology is gaining global popularity [
1,
2,
3,
4,
5] especially for applications in harsh environments [
1,
2,
6,
7,
8]. In most cases, a WPT system is designed to provide a load with constant voltage. This can be realized by an open loop design to make the output voltage insensitive to load and coupling coefficient [
9] or by a closed loop method to regulate the output voltage [
10,
11,
12]. The closed loop regulation can be implemented at the primary or secondary side, and the primary side regulation is implemented by changing the input power while the secondary side regulation is implemented by varying the equivalent impedance. Due to the time-varying load characteristics of a practical WPT system, closed loop regulation is more suitable since it can maintain an accurate constant output voltage for variable load resistances.
In WPT applications such as electrical vehicles (EVs) and implant device charging, load status monitoring (e.g., battery status, load voltage, load current, etc.) on the primary side is usually required [
13]. Thus data transmission from the secondary side to the primary side is needed. Although there exist some wireless data transmission technologies such as WiFi, Bluetooth and ZigBee, the shortcomings such as complicated paring [
13,
14] between the transmitter and receiver sides push people keep trying to realize the data transmission by utilizing the inherent wireless power transfer circuit [
15,
16]. Generally, the major requirement for such a WPT system with data transmission and output voltage controllability is the decoupling so the transmission of power and data are not affected by each other.
As for wireless transmission of power and data in WPT systems, references [
13,
15,
16] describe data transmission through the existing power coils, while [
17] proposes data transmission by the use of extra data transfer coils. In references [
13,
15,
16], the volume of the coupling structure (coils) is relatively small, since power and data are transferred through the same coupling coils. Nevertheless, its data processing circuit is difficult to design to increase the signal to noise ratio (SNR). In reference [
17], the data processing circuit is relatively easy to design to increase SNR since the data transfer channel is separated from the power transfer channel, however, the added data inductive channel makes the volume of the coupling structure large. Reference [
18] shows an alternative method for parallel transmission of power and data, whereby power is transferred through the fundamental component while data is transferred through the third-order harmonic component. Power and data are transferred through the same coupling structure, but the frequency modulation (FM) would affect the resonance of the power transfer resonant circuits. Reference [
14] studied an inductive and capacitive combined parallel transmission of power and data, where data is transferred via the parasitic capacitances, but not all the applications have the required aluminum plates. Reference [
13] shows that transferring information of load voltage and current only needs a slow data transfer rate. References [
19,
20] illustrated that power and data can be transferred through a time division multiplexing (TDM) method, and the transmission of power and data would not be affected by each other.
In this paper, an alternative wireless power and data decoupled transmission method is proposed. Compared with traditional power and data parallel transfer methods, the proposed method can utilize a short power blocking interval to transfer data and keep the power output continuous and stable at the same time. This method is beneficial for SNR improvement and high speed transmission rates. To implement this method, an AC bi-directional switch is added to control the data transmission flow and a hysteresis controller is utilized to realize the output voltage control. These features are verified by both the Bode plot analysis and experimental results.
3. Interference of Extra Data Transfer Channel on Power Transfer
3.1. Interference of Extra Data Transfer Channel on Power Transfer
When considering the influence on power transfer due to the extra data transfer channel, two issues should be of concern. The first is the interference of data carrier transfer with power transfer; the second is the power transfer loss due to the data transfer circuit. However, since data is transferred when the switch
S is off, so the interference of data carrier transfer on power transfer can be ignored. As for the power transfer loss due to the data transfer circuit, it can be monitored by the attenuation of output voltage
UL whether the data transfer circuit is added or not. The simplified power transfer circuit without and with the data receiver circuit are shown in
Figure 6a,b respectively, where
ii is the equivalent input current source.
For the original system shown in
Figure 6a, the reflected resistance to the primary side is given by:
where
Zs is the secondary side loop impedance, given by
Zs = jωLs + 1/
jωCs +
Req.
M is the mutual inductance.
The primary inductance current
ip1 can be derived as:
where
Zp1 is the impedance given by
Zp1 =
jωLp + 1/
jωCp +
Zr.
The output voltage can be given by:
The transfer function from the input current
ii to the output voltage
ueq1 is:
As mentioned before, the data carrier is injected to the secondary side only when switch
S is off (i.e., power transmission is blocked), the data transmitter circuit does not affect the power transfer. As for the data receiver circuit added in the primary side shown in
Figure 6b, the influence can be monitored. The primary inductance current
ip2 can be rewritten as:
where
Zp2 is the impedance given by:
and
Zd is the impedance of the data receiver circuit, given by:
Z
p2 = jωL
p + 1/jωC
p + Z
r + Z
d, Z
d = 1/(jωC
d + 1/jωL
d + 1/R
d).
So the output voltage can be given by:
The transfer function from the current input
ii to the output voltage
ueq2 can be calculated as:
By comparing the Bode plots of Equations (6) and (11), the interference on power transfer due to the addition of the data transfer channel can be monitored, and this will be presented in the following section.
3.2. Interference of Power Transfer on Data Transfer
As for the data transfer channel, the SNR should be designed to be pretty high [
12]. There are two factors affecting the SNR performance: (1) the interference of the power transfer with the data transfer; (2) the output capacity of the data transfer. These two effects could significantly influence the SNR performance. For a well-designed data transfer channel, these two factors should be optimized. The interference of power transfer on data transfer should be minimized while the output capacity of data transfer should be maximized.
As for the interference of power transfer on data transfer, the circuit is shown in
Figure 6b. According to Equation (7), the interference voltage
Vop can be expressed as:
The transfer function from the input current
ii to the data output
Vop is:
If the parameters
Lp,
Cp,
Ls and
Cs satisfy the assumption shown in Equation (2), then Equation (13) can be simplified as:
Equation (14) shows that the interference transfer function relates to the parameters ωp, Cp, Req (RL), M and Zd. In order to reduce the interference, we can increase RL, Zd or reasonably decrease ωp, M and Cp.
3.3. Data Transfer Channel Analysis
In the above section, we have learnt that the reduction of power transfer interference on data transfer can be achieved by reasonably setting some parameters. In this section, the output capacity of data transfer will be studied. When there is only data transfer in the system, the circuit is shown in
Figure 7a, where the mutual inductance couplings on primary side coil and secondary side coil are represented by two controlled voltage sources
jωMis and −
jωMip, respectively.
According to
Figure 7a, the following equations can be derived:
The transfer function from the input data carrier
Vd to the output data carrier
Vod1 can be expressed as:
where Z
sd = jωL
s + 1/jωC
s + 1/jωC
sd.
As is mentioned before,
Ls,
Csd and
Ld,
Cd resonate at data transfer frequency, so Equation (16) can be simplified as:
Figure 7b is presented to compare the SNR of the proposed method (transferring data when power transfer is blocked) with the traditional method which transfers data when power is transferred. The following equations can be derived from
Figure 7b:
The transfer function from the input data carrier
Vd to the output data carrier
Vod2 can be expressed as:
where Z
rp = jωL
p + 1/jωC
p, Z
rs = jωL
s + 1/jωC
s.
By comparing the Bode plots of Equations (17) and (19), the data transfer capacity of the proposed method and the traditional method can be compared, and this will be presented in the following section.
3.4. Consideration for the Data Transfer Rate
Since the proposed method transferring data when switch
S is off, the data transmission rate can be determined by:
where
dcr represents the conventional data transfer rate,
toff is the off-state time while
ton is the on-state time in one operation period of the switch
S.
So in order to increase the data transfer rate, we can either increase
dcr or
toff. Increasing
dcr can be achieved by increasing the data carrier frequency. As for
toff, it can be calculated by:
Equation (21) shows that the time interval of the off state can be increased when we reasonably increase the product of RL and CL.
5. Experimental Verification
To verify the proposed method, an experimental prototype is built according to
Figure 3 with the parameters shown in
Table 1. For the primary side push-pull inverter, an IRF3610 MOSFET is used as the switch device. For the secondary side rectifier, a SS36 Schottky diode is selected. The detailed power and data transfer circuit is shown in
Figure 11. For the secondary side power transfer circuit, LM311 chip is used as the voltage comparator, the comparison signal is fed to the field programmable gate array (FPGA) chip (Altera Cyclone II EP2C5T144C8). Afterward, the FPGA chip determines the on-off state of the switches
S and
Sd. For the data transfer circuit, the modulation is produced by a CD4051 chip; a ceramic filter chip is used as the bandpass filter while a LT1816 chip is used as the operational amplifier. The demodulation circuit consists of an envelope detector to get the envelop of the carrier and a comparator (LM311 chip) to discriminate the data.
5.1. Interference Analysis of the Data Transfer Channel to Power Transfer
As is indicated before, the interference from data transfer channel to power transfer can be monitored by the output voltage
UL.
Figure 12 shows the experiment results with and without data transfer, where channel 1 indicates the output voltage, channel 4 indicates the voltage of
Cp, and channel 2 indicates the output data.
Figure 12a shows that the mean value of
UL with data transfer is 16.4 V, while
Figure 12b shows that the mean value of
UL without data transfer is 16.2 V. Such a small difference indicates the interference of data transfer to power transfer can be ignored. This verifies the Bode plots shown in
Figure 8. Furthermore, the system efficiency of
Figure 12a is 71%, and the data transfer rate is 560 kbps.
5.2. Comparison between the Proposed and Traditional Data Transfer Method
Figure 13 shows the comparison results between the proposed and traditional data transfer as mentioned in
Figure 7.
Figure 7a shows the proposed data transfer circuit while
Figure 7b shows the traditional data transfer circuit. Channel 1 indicates the output voltage
UL, channel 4 indicates the output voltage of the amplifier, and channel 2 indicates the output data.
Figure 13a shows that data transfer with the proposed method is stable, while
Figure 13b shows that data transfer with a traditional circuit failed. The amplitude of channel 4 shows that the amplifier output of the proposed method is larger than that of the traditional circuit, thus the data transfer capacity of the proposed method is larger than that of the traditional circuit. These results verify the modeling of the transfer function in
Section 3 and the Bode plot analysis shown in
Figure 10.
5.3. Analysis of the Data Transfer Rate
Equation (20) shows that in order to increase the data transfer rate, we can either increase the conventional data transfer rate or the conduction duty cycle of
Sd.
Figure 14a shows the case by increasing the conventional data transfer rate, while
Figure 14b indicates the case by increasing the conduction duty cycle of
Sd.
Both
Figure 14a,b show the output voltage is controlled to be around 16 V. In addition, the data transfer rate can be increased through these two methods, i.e. by increasing the conventional data transfer rate or increasing the conduction duty cycle of
Sd.
5.4. Comparasion Results with the Published Literatures
Table 2 shows the comparison results between the proposed method and the traditional ways studied in [
13,
14,
15,
16,
17,
18]. Since the power transfer and data transfer functions of the proposed method are decoupled, the SNR is very high, so as the data transfer rate can reach 560 kbps. It should be noted that a 25 W prototype was set up for demonstration. This method could be used in high power systems due to its high SNR characteristics. Moreover, the data transfer method is especially suitable to monitor the load status in WPT applications such as biomedical implants and robot charging.