A Power and Data Decoupled Transmission Method for Wireless Power Transfer Systems via a Shared Inductive Link

: Wireless Power Transfer (WPT) technology is gaining global popularity. However, in some applications, data transmission is also required to monitor the load states. This paper presents an alternative wireless power and data transmission method via the shared inductive link. With the method, the system presents three characteristics: (1) controllability and stability of the output voltage; (2) miniaturization in volume of the system; (3) decoupled transmission of power and data. The output voltage control is realized by a non-inductive hysteresis control method. In particular, data is transferred when the power transmission is blocked (i


Introduction
With the demand of transferring power without physical contact, wireless power transfer (WPT) technology is gaining global popularity [1][2][3][4][5] especially for applications in harsh environments [1,2,[6][7][8].In most cases, a WPT system is designed to provide a load with constant voltage.This can be realized by an open loop design to make the output voltage insensitive to load and coupling coefficient [9] or by a closed loop method to regulate the output voltage [10][11][12].The closed loop regulation can be implemented at the primary or secondary side, and the primary side regulation is implemented by changing the input power while the secondary side regulation is implemented by varying the equivalent impedance.Due to the time-varying load characteristics of a practical WPT system, closed loop regulation is more suitable since it can maintain an accurate constant output voltage for variable load resistances.
In WPT applications such as electrical vehicles (EVs) and implant device charging, load status monitoring (e.g., battery status, load voltage, load current, etc.) on the primary side is usually required [13].Thus data transmission from the secondary side to the primary side is needed.Although there exist some wireless data transmission technologies such as WiFi, Bluetooth and ZigBee, the shortcomings such as complicated paring [13,14] between the transmitter and receiver sides push people keep trying to realize the data transmission by utilizing the inherent wireless power transfer circuit [15,16].Generally, the major requirement for such a WPT system with data transmission Energies 2018, 11, 2161 2 of 14 and output voltage controllability is the decoupling so the transmission of power and data are not affected by each other.
As for wireless transmission of power and data in WPT systems, references [13,15,16] describe data transmission through the existing power coils, while [17] proposes data transmission by the use of extra data transfer coils.In references [13,15,16], the volume of the coupling structure (coils) is relatively small, since power and data are transferred through the same coupling coils.Nevertheless, its data processing circuit is difficult to design to increase the signal to noise ratio (SNR).In reference [17], the data processing circuit is relatively easy to design to increase SNR since the data transfer channel is separated from the power transfer channel, however, the added data inductive channel makes the volume of the coupling structure large.Reference [18] shows an alternative method for parallel transmission of power and data, whereby power is transferred through the fundamental component while data is transferred through the third-order harmonic component.Power and data are transferred through the same coupling structure, but the frequency modulation (FM) would affect the resonance of the power transfer resonant circuits.Reference [14] studied an inductive and capacitive combined parallel transmission of power and data, where data is transferred via the parasitic capacitances, but not all the applications have the required aluminum plates.Reference [13] shows that transferring information of load voltage and current only needs a slow data transfer rate.References [19,20] illustrated that power and data can be transferred through a time division multiplexing (TDM) method, and the transmission of power and data would not be affected by each other.
In this paper, an alternative wireless power and data decoupled transmission method is proposed.Compared with traditional power and data parallel transfer methods, the proposed method can utilize a short power blocking interval to transfer data and keep the power output continuous and stable at the same time.This method is beneficial for SNR improvement and high speed transmission rates.To implement this method, an AC bi-directional switch is added to control the data transmission flow and a hysteresis controller is utilized to realize the output voltage control.These features are verified by both the Bode plot analysis and experimental results.

Hysteresis Voltage Control
To simplify the output voltage control circuit, a hysteresis voltage control method is utilized.The corresponding circuit is shown in Figure 1, where S is a decoupling switch, power transmission is blocked (from primary side to secondary side) when S is turned off.A push-pull inverter is used to generate the high frequency AC source.L p , C p and L s , C s constitute the primary parallel and secondary series resonant circuits, respectively.D 1 ~D4 constitute the rectifier.R eq is the equivalent input resistance of the rectifier circuit and equals to 8R L /π 2 .C L is the output filter capacitor and R L is the load resistance.E and U L are the input and load DC voltages, respectively.
Energies 2018, 11, x 2 of 14 output voltage controllability is the decoupling so the transmission of power and data are not affected by each other.
As for wireless transmission of power and data in WPT systems, references [13,15,16] describe data transmission through the existing power coils, while [17] proposes data transmission by the use of extra data transfer coils.In references [13,15,16], the volume of the coupling structure (coils) is relatively small, since power and data are transferred through the same coupling coils.Nevertheless, its data processing circuit is difficult to design to increase the signal to noise ratio (SNR).In reference [17], the data processing circuit is relatively easy to design to increase SNR since the data transfer channel is separated from the power transfer channel, however, the added data inductive channel makes the volume of the coupling structure large.Reference [18] shows an alternative method for parallel transmission of power and data, whereby power is transferred through the fundamental component while data is transferred through the third-order harmonic component.Power and data are transferred through the same coupling structure, but the frequency modulation (FM) would affect the resonance of the power transfer resonant circuits.Reference [14] studied an inductive and capacitive combined parallel transmission of power and data, where data is transferred via the parasitic capacitances, but not all the applications have the required aluminum plates.Reference [13] shows that transferring information of load voltage and current only needs a slow data transfer rate.References [19,20] illustrated that power and data can be transferred through a time division multiplexing (TDM) method, and the transmission of power and data would not be affected by each other.
In this paper, an alternative wireless power and data decoupled transmission method is proposed.Compared with traditional power and data parallel transfer methods, the proposed method can utilize a short power blocking interval to transfer data and keep the power output continuous and stable at the same time.This method is beneficial for SNR improvement and high speed transmission rates.To implement this method, an AC bi-directional switch is added to control the data transmission flow and a hysteresis controller is utilized to realize the output voltage control.These features are verified by both the Bode plot analysis and experimental results.

Hysteresis Voltage Control
To simplify the output voltage control circuit, a hysteresis voltage control method is utilized.The corresponding circuit is shown in Figure 1, where S is a decoupling switch, power transmission is blocked (from primary side to secondary side) when S is turned off.A push-pull inverter is used to generate the high frequency AC source.Lp, Cp and Ls, Cs constitute the primary parallel and secondary series resonant circuits, respectively.D1 ~ D4 constitute the rectifier.Req is the equivalent input resistance of the rectifier circuit and equals to 8RL/π 2 .CL is the output filter capacitor and RL is the load resistance.E and UL are the input and load DC voltages, respectively.The hysteresis voltage control can be illustrated with the aid of Figure 2. Assuming the required constant output voltage is U L-req with a hysteresis tolerance band of ±u t .S will be switched to the on state when U L is smaller than U L-req − u t and switched to the off state when U L is larger than U L-req + u t .
Energies 2018, 11, x 3 of 14 The hysteresis voltage control can be illustrated with the aid of Figure 2. Assuming the required constant output voltage is UL-req with a hysteresis tolerance band of ±ut.S will be switched to the on state when UL is smaller than UL-req − ut and switched to the off state when UL is larger than UL-req + ut.

Power and Data Transfer Principle
In some WPT applications such as implanted biomedical devices or robot charging, the information such as battery status, output voltage and output current should be transmitted from the secondary side to the primary side.The proposed data transfer circuit is shown in Figure 3, where Sd is an AC switch composed of two semiconductor switches (e.g., IGBTs or MOSFETs).Csd is used to compensate Ls at the data carrier frequency.Vd is the injected data carrier while Vo is the received data carrier.Ld and Cd comprise an LC tuning circuit to maximize the output carrier Vo, satisfying , where ωd is the angular frequency of the data carrier.Rd is the input resistance of the data processing circuit.The data transfer topology is shown in Figure 4, where the data transmitter side consists of a modulation module, while the data receiver side consists of a bandpass filter, an operational amplifier and a demodulation module.An amplitude shift keying (ASK) modulation method is used to generate the data carrier.The generation function of the data carrier can be given as: ( ) ( ) cos 2 , "1" 0 , "0" where fd and Ac are the frequency and the amplitude of the data carrier, respectively.

Power and Data Transfer Principle
In some WPT applications such as implanted biomedical devices or robot charging, the information such as battery status, output voltage and output current should be transmitted from the secondary side to the primary side.The proposed data transfer circuit is shown in Figure 3, where S d is an AC switch composed of two semiconductor switches (e.g., IGBTs or MOSFETs).C sd is used to compensate L s at the data carrier frequency.V d is the injected data carrier while V o is the received data carrier.L d and C d comprise an LC tuning circuit to maximize the output carrier V o , satisfying , where ω d is the angular frequency of the data carrier.R d is the input resistance of the data processing circuit.The data transfer topology is shown in Figure 4, where the data transmitter side consists of a modulation module, while the data receiver side consists of a bandpass filter, an operational amplifier and a demodulation module.An amplitude shift keying (ASK) modulation method is used to generate the data carrier.The generation function of the data carrier can be given as: where f d and A c are the frequency and the amplitude of the data carrier, respectively.
Energies 2018, 11, x 3 of 14 The hysteresis voltage control can be illustrated with the aid of Figure 2. Assuming the required constant output voltage is UL-req with a hysteresis tolerance band of ±ut.S will be switched to the on state when UL is smaller than UL-req − ut and switched to the off state when UL is larger than UL-req + ut.

Power and Data Transfer Principle
In some WPT applications such as implanted biomedical devices or robot charging, the information such as battery status, output voltage and output current should be transmitted from the secondary side to the primary side.The proposed data transfer circuit is shown in Figure 3, where Sd is an AC switch composed of two semiconductor switches (e.g., IGBTs or MOSFETs).Csd is used to compensate Ls at the data carrier frequency.Vd is the injected data carrier while Vo is the received data carrier.Ld and Cd comprise an LC tuning circuit to maximize the output carrier Vo, satisfying , where ωd is the angular frequency of the data carrier.Rd is the input resistance of the data processing circuit.The data transfer topology is shown in Figure 4, where the data transmitter side consists of a modulation module, while the data receiver side consists of a bandpass filter, an operational amplifier and a demodulation module.An amplitude shift keying (ASK) modulation method is used to generate the data carrier.The generation function of the data carrier can be given as: where fd and Ac are the frequency and the amplitude of the data carrier, respectively.The hysteresis voltage control can be illustrated with the aid of Figure 2. Assuming the required constant output voltage is UL-req with a hysteresis tolerance band of ±ut.S will be switched to the on state when UL is smaller than UL-req − ut and switched to the off state when UL is larger than UL-req + ut.

Power and Data Transfer Principle
In some WPT applications such as implanted biomedical devices or robot charging, the information such as battery status, output voltage and output current should be transmitted from the secondary side to the primary side.The proposed data transfer circuit is shown in Figure 3, where Sd is an AC switch composed of two semiconductor switches (e.g., IGBTs or MOSFETs).Csd is used to compensate Ls at the data carrier frequency.Vd is the injected data carrier while Vo is the received data carrier.Ld and Cd comprise an LC tuning circuit to maximize the output carrier Vo, satisfying , where ωd is the angular frequency of the data carrier.Rd is the input resistance of the data processing circuit.The data transfer topology is shown in Figure 4, where the data transmitter side consists of a modulation module, while the data receiver side consists of a bandpass filter, an operational amplifier and a demodulation module.An amplitude shift keying (ASK) modulation method is used to generate the data carrier.The generation function of the data carrier can be given as: where fd and Ac are the frequency and the amplitude of the data carrier, respectively.Figure 3 shows that data is transferred during the off state of the decoupling switch S (S d is turned on when S is off).The proposed system has two working modes: (1) when S is on and S d is off, power is transferred to the load while data transmission is blocked; (2) when S is off and S d is on, data is transferred from the secondary side to the primary side while the output capacitor C L is free running.The circuits of these two working modes are shown in Figure 5.
Energies 2018, 11, x 4 of 14 Figure 3 shows that data is transferred during the off state of the decoupling switch S (Sd is turned on when S is off).The proposed system has two working modes: (1) when S is on and Sd is off, power is transferred to the load while data transmission is blocked; (2) when S is off and Sd is on, data is transferred from the secondary side to the primary side while the output capacitor CL is free running.The circuits of these two working modes are shown in Figure 5.To simplify the analysis, the following assumptions are made: (1) the data carrier frequency fd is selected higher than the power carrier frequency fp.This is because the extra data transfer channel would not significantly affect the power transfer and the interference of power transfer on data transfer is easy to suppress; (2) the resonant frequencies of the primary and secondary resonant circuits are identical:

Interference of Extra Data Transfer Channel on Power Transfer
When considering the influence on power transfer due to the extra data transfer channel, two issues should be of concern.The first is the interference of data carrier transfer with power transfer; the second is the power transfer loss due to the data transfer circuit.However, since data is transferred when the switch S is off, so the interference of data carrier transfer on power transfer can be ignored.As for the power transfer loss due to the data transfer circuit, it can be monitored by the attenuation of output voltage UL whether the data transfer circuit is added or not.The simplified To simplify the analysis, the following assumptions are made: (1) the data carrier frequency f d is selected higher than the power carrier frequency f p .This is because the extra data transfer channel would not significantly affect the power transfer and the interference of power transfer on data transfer is easy to suppress; (2) the resonant frequencies of the primary and secondary resonant circuits are identical:

Interference of Extra Data Transfer Channel on Power Transfer
When considering the influence on power transfer due to the extra data transfer channel, two issues should be of concern.The first is the interference of data carrier transfer with power transfer; the second is the power transfer loss due to the data transfer circuit.However, since data is transferred when the switch S is off, so the interference of data carrier transfer on power transfer can be ignored.As for the power transfer loss due to the data transfer circuit, it can be monitored by the attenuation of output voltage U L whether the data transfer circuit is added or not.The simplified power transfer circuit without and with the data receiver circuit are shown in Figure 6a,b respectively, where i i is the equivalent input current source.For the original system shown in Figure 6a, the reflected resistance to the primary side is given by: where Zs is the secondary side loop impedance, given by Zs = jωLs + 1/jωCs + Req.M is the mutual inductance.
The output voltage can be given by: The transfer function from the input current ii to the output voltage ueq1 is: ( ) As mentioned before, the data carrier is injected to the secondary side only when switch S is off (i.e., power transmission is blocked), the data transmitter circuit does not affect the power transfer.As for the data receiver circuit added in the primary side shown in Figure 6b, the influence can be monitored.The primary inductance current ip2 can be rewritten as: For the original system shown in Figure 6a, the reflected resistance to the primary side is given by: where Z s is the secondary side loop impedance, given by Z s = jωL s + 1/jωC s + R eq .M is the mutual inductance.The primary inductance current i p1 can be derived as: where Z p1 is the impedance given by Z p1 = jωL p + 1/jωC p + Z r .
The output voltage can be given by: The transfer function from the input current i i to the output voltage u eq1 is: As mentioned before, the data carrier is injected to the secondary side only when switch S is off (i.e., power transmission is blocked), the data transmitter circuit does not affect the power transfer.As for the data receiver circuit added in the primary side shown in Figure 6b, the influence can be monitored.The primary inductance current i p2 can be rewritten as: Energies 2018, 11, 2161 where Z p2 is the impedance given by: and Z d is the impedance of the data receiver circuit, given by: So the output voltage can be given by: The transfer function from the current input i i to the output voltage u eq2 can be calculated as: By comparing the Bode plots of Equations ( 6) and ( 11), the interference on power transfer due to the addition of the data transfer channel can be monitored, and this will be presented in the following section.

Interference of Power Transfer on Data Transfer
As for the data transfer channel, the SNR should be designed to be pretty high [12].There are two factors affecting the SNR performance: (1) the interference of the power transfer with the data transfer; (2) the output capacity of the data transfer.These two effects could significantly influence the SNR performance.For a well-designed data transfer channel, these two factors should be optimized.The interference of power transfer on data transfer should be minimized while the output capacity of data transfer should be maximized.
As for the interference of power transfer on data transfer, the circuit is shown in Figure 6b.According to Equation (7), the interference voltage V op can be expressed as: The transfer function from the input current i i to the data output V op is: If the parameters L p , C p , L s and C s satisfy the assumption shown in Equation ( 2), then Equation ( 13) can be simplified as: Equation (14) shows that the interference transfer function relates to the parameters ω p , C p , R eq (R L ), M and Z d .In order to reduce the interference, we can increase R L , Z d or reasonably decrease ω p , M and C p .

Data Transfer Channel Analysis
In the above section, we have learnt that the reduction of power transfer interference on data transfer can be achieved by reasonably setting some parameters.In this section, the output capacity of data transfer will be studied.When there is only data transfer in the system, the circuit is shown in Figure 7a, where the mutual inductance couplings on primary side coil and secondary side coil are represented by two controlled voltage sources jωMi s and −jωMi p , respectively.

Data Transfer Channel Analysis
In the above section, we have learnt that the reduction of power transfer interference on data transfer can be achieved by reasonably setting some parameters.In this section, the output capacity of data transfer will be studied.When there is only data transfer in the system, the circuit is shown in Figure 7a, where the mutual inductance couplings on primary side coil and secondary side coil are represented by two controlled voltage sources jωMis and −jωMip, respectively.According to Figure 7a, the following equations can be derived: The transfer function from the input data carrier Vd to the output data carrier Vod1 can be expressed as: ) where Zsd = jωLs + 1/jωCs + 1/jωCsd.As is mentioned before, Ls, Csd and Ld, Cd resonate at data transfer frequency, so Equation ( 16) can be simplified as: According to Figure 7a, the following equations can be derived: The transfer function from the input data carrier V d to the output data carrier V od1 can be expressed as: where Z sd = jωL s + 1/jωC s + 1/jωC sd .
As is mentioned before, L s , C sd and L d , C d resonate at data transfer frequency, so Equation ( 16) can be simplified as: Energies 2018, 11, 2161 8 of 14 Figure 7b is presented to compare the SNR of the proposed method (transferring data when power transfer is blocked) with the traditional method which transfers data when power is transferred.The following equations can be derived from Figure 7b: The transfer function from the input data carrier V d to the output data carrier V od2 can be expressed as: where Z rp = jωL p + 1/jωC p , Z rs = jωL s + 1/jωC s .By comparing the Bode plots of Equations ( 17) and ( 19), the data transfer capacity of the proposed method and the traditional method can be compared, and this will be presented in the following section.

Consideration for the Data Transfer Rate
Since the proposed method transferring data when switch S is off, the data transmission rate can be determined by: where d cr represents the conventional data transfer rate, t off is the off-state time while t on is the on-state time in one operation period of the switch S.So in order to increase the data transfer rate, we can either increase d cr or t off .Increasing d cr can be achieved by increasing the data carrier frequency.As for t off , it can be calculated by: Equation ( 21) shows that the time interval of the off state can be increased when we reasonably increase the product of R L and C L .

Simulation Studies
In this section, Bode plot simulation studies are presented to verify the feasibility of the proposed method.The parameters of the system are shown in Table 1, where the frequencies of power and signal are empirically determined as 91 kHz and 10 MHz, respectively, and then L p , C p , L s , C s can be determined accordingly.The load R L is 10 Ω, and the required voltage is 16 V, with a hysteresis band of ±0.5 V.

Bode Plot Analysis of Power Transfer with and without Data Transfer
The Bode plots of the power transfer without data transfer (G pp1 shown in Equation ( 6)) from i i to u eq1 and power transfer with data transfer (G pp2 shown in Equation ( 11)) from i i to u eq2 are shown in Figure 8, where we can see that the difference between "with data transfer" and "without data transfer" can be ignored.This verifies that the addition of the data transfer channel has almost no impact on the power transfer.

Bode Plot Analysis of Power Transfer with and without Data Transfer
The Bode plots of the power transfer without data transfer (Gpp1 shown in Equation ( 6)) from ii to ueq1 and power transfer with data transfer (Gpp2 shown in Equation ( 11)) from ii to ueq2 are shown in Figure 8, where we can see that the difference between "with data transfer" and "without data transfer" can be ignored.This verifies that the addition of the data transfer channel has almost no impact on the power transfer.

Bode Plot of the Interference from Power Transfer to Data Transfer
The Bode plot of the power transfer interference on the data transfer (Gpd shown in Equation ( 13)) from ii to Vop is shown in Figure 9. From Figure 9, we can see that the magnitude of the interference at the power transfer frequency is around −15 dB, which is pretty low for data transfer, therefore, the SNR can remain pretty high.

Bode Plot of the Interference from Power Transfer to Data Transfer
The Bode plot of the power transfer interference on the data transfer (G pd shown in Equation ( 13)) from i i to V op is shown in Figure 9. From Figure 9, we can see that the magnitude of the interference at the power transfer frequency is around −15 dB, which is pretty low for data transfer, therefore, the SNR can remain pretty high.

Bode Plot Analysis of Power Transfer with and without Data Transfer
The Bode plots of the power transfer without data transfer (Gpp1 shown in Equation ( 6)) from ii to ueq1 and power transfer with data transfer (Gpp2 shown in Equation ( 11)) from ii to ueq2 are shown in Figure 8, where we can see that the difference between "with data transfer" and "without data transfer" can be ignored.This verifies that the addition of the data transfer channel has almost no impact on the power transfer.

Bode Plot of the Interference from Power Transfer to Data Transfer
The Bode plot of the power transfer interference on the data transfer (Gpd shown in Equation ( 13)) from ii to Vop is shown in Figure 9. From Figure 9, we can see that the magnitude of the interference at the power transfer frequency is around −15 dB, which is pretty low for data transfer, therefore, the SNR can remain pretty high.

Bode Plot Analysis of the Proposed and Traditional Data Transfer Channel
The Bode plots of the proposed data transfer channel (G dd1 shown in Equation ( 16)) from V d to V od1 and traditional data transfer channel (G dd2 shown in Equation ( 19)) from V d to V od2 are shown in Figure 10, which shows that the data transfer capacity of the proposed channel is larger than the Energies 2018, 11, 2161 10 of 14 traditional channel at the data carrier frequency, so the proposed method for transferring data when power transfer is blocked is more suitable for data transfer.

Bode Plot Analysis of the Proposed and Traditional Data Transfer Channel
The Bode plots of the proposed data transfer channel (Gdd1 shown in Equation ( 16)) from Vd to Vod1 and traditional data transfer channel (Gdd2 shown in Equation ( 19)) from Vd to Vod2 are shown in Figure 10, which shows that the data transfer capacity of the proposed channel is larger than the traditional channel at the data carrier frequency, so the proposed method for transferring data when power transfer is blocked is more suitable for data transfer.

Experimental Verification
To verify the proposed method, an experimental prototype is built according to Figure 3 with the parameters shown in Table 1.For the primary side push-pull inverter, an IRF3610 MOSFET is used as the switch device.For the secondary side rectifier, a SS36 Schottky diode is selected.The detailed power and data transfer circuit is shown in Figure 11.For the secondary side power transfer circuit, LM311 chip is used as the voltage comparator, the comparison signal is fed to the field programmable gate array (FPGA) chip (Altera Cyclone II EP2C5T144C8).Afterward, the FPGA chip determines the on-off state of the switches S and Sd.For the data transfer circuit, the modulation is produced by a CD4051 chip; a ceramic filter chip is used as the bandpass filter while a LT1816 chip is used as the operational amplifier.The demodulation circuit consists of an envelope detector to get the envelop of the carrier and a comparator (LM311 chip) to discriminate the data.

Experimental Verification
To verify the proposed method, an experimental prototype is built according to Figure 3 with the parameters shown in Table 1.For the primary side push-pull inverter, an IRF3610 MOSFET is used as the switch device.For the secondary side rectifier, a SS36 Schottky diode is selected.The detailed power and data transfer circuit is shown in Figure 11.For the secondary side power transfer circuit, LM311 chip is used as the voltage comparator, the comparison signal is fed to the field programmable gate array (FPGA) chip (Altera Cyclone II EP2C5T144C8).Afterward, the FPGA chip determines the on-off state of the switches S and S d .For the data transfer circuit, the modulation is produced by a CD4051 chip; a ceramic filter chip is used as the bandpass filter while a LT1816 chip is used as the operational amplifier.The demodulation circuit consists of an envelope detector to get the envelop of the carrier and a comparator (LM311 chip) to discriminate the data.

Bode Plot Analysis of the Proposed and Traditional Data Transfer Channel
The Bode plots of the proposed data transfer channel (Gdd1 shown in Equation ( 16)) from Vd to Vod1 and traditional data transfer channel (Gdd2 shown in Equation ( 19)) from Vd to Vod2 are shown in Figure 10, which shows that the data transfer capacity of the proposed channel is larger than the traditional channel at the data carrier frequency, so the proposed method for transferring data when power transfer is blocked is more suitable for data transfer.

Experimental Verification
To verify the proposed method, an experimental prototype is built according to Figure 3 with the parameters shown in Table 1.For the primary side push-pull inverter, an IRF3610 MOSFET is used as the switch device.For the secondary side rectifier, a SS36 Schottky diode is selected.The detailed power and data transfer circuit is shown in Figure 11.For the secondary side power transfer circuit, LM311 chip is used as the voltage comparator, the comparison signal is fed to the field programmable gate array (FPGA) chip (Altera Cyclone II EP2C5T144C8).Afterward, the FPGA chip determines the on-off state of the switches S and Sd.For the data transfer circuit, the modulation is produced by a CD4051 chip; a ceramic filter chip is used as the bandpass filter while a LT1816 chip is used as the operational amplifier.The demodulation circuit consists of an envelope detector to get the envelop of the carrier and a comparator (LM311 chip) to discriminate the data.

Interference Analysis of the Data Transfer Channel to Power Transfer
As is indicated before, the interference from data transfer channel to power transfer can be monitored by the output voltage UL.  Figure 12a shows that the mean value of UL with data transfer is 16.4 V, while Figure 12b shows that the mean value of UL without data transfer is 16.2 V.Such a small difference indicates the interference of data transfer to power transfer can be ignored.This verifies the Bode plots shown in Figure 8. Furthermore, the system efficiency of Figure 12a is 71%, and the data transfer rate is 560 kbps.

Comparison between the Proposed and Traditional Data Transfer Method
Figure 13 shows the comparison results between the proposed and traditional data transfer as mentioned in Figure 7. Figure 7a shows the proposed data transfer circuit while Figure 7b shows the traditional data transfer circuit.Channel 1 indicates the output voltage UL, channel 4 indicates the output voltage of the amplifier, and channel 2 indicates the output data.
Figure 13a shows that data transfer with the proposed method is stable, while Figure 13b shows that data transfer with a traditional circuit failed.The amplitude of channel 4 shows that the amplifier output of the proposed method is larger than that of the traditional circuit, thus the data transfer

Interference Analysis of the Data Transfer Channel to Power Transfer
As is indicated before, the interference from data transfer channel to power transfer can be monitored by the output voltage U L . Figure 12

Interference Analysis of the Data Transfer Channel to Power Transfer
As is indicated before, the interference from data transfer channel to power transfer can be monitored by the output voltage UL.  Figure 12a shows that the mean value of UL with data transfer is 16.4 V, while Figure 12b shows that the mean value of UL without data transfer is 16.2 V.Such a small difference indicates the interference of data transfer to power transfer can be ignored.This verifies the Bode plots shown in Figure 8. Furthermore, the system efficiency of Figure 12a is 71%, and the data transfer rate is 560 kbps.

Comparison between the Proposed and Traditional Data Transfer Method
Figure 13 shows the comparison results between the proposed and traditional data transfer as mentioned in Figure 7. Figure 7a shows the proposed data transfer circuit while Figure 7b shows the traditional data transfer circuit.Channel 1 indicates the output voltage UL, channel 4 indicates the output voltage of the amplifier, and channel 2 indicates the output data.
Figure 13a shows that data transfer with the proposed method is stable, while Figure 13b shows that data transfer with a traditional circuit failed.The amplitude of channel 4 shows that the amplifier output of the proposed method is larger than that of the traditional circuit, thus the data transfer Figure 12a shows that the mean value of U L with data transfer is 16.4 V, while Figure 12b shows that the mean value of U L without data transfer is 16.2 V.Such a small difference indicates the interference of data transfer to power transfer can be ignored.This verifies the Bode plots shown in Figure 8. Furthermore, the system efficiency of Figure 12a is 71%, and the data transfer rate is 560 kbps.

Comparison between the Proposed and Traditional Data Transfer Method
Figure 13 shows the comparison results between the proposed and traditional data transfer as mentioned in Figure 7. Figure 7a shows the proposed data transfer circuit while Figure 7b shows the traditional data transfer circuit.Channel 1 indicates the output voltage U L , channel 4 indicates the output voltage of the amplifier, and channel 2 indicates the output data.
Figure 13a shows that data transfer with the proposed method is stable, while Figure 13b shows that data transfer with a traditional circuit failed.The amplitude of channel 4 shows that the amplifier output of the proposed method is larger than that of the traditional circuit, thus the data transfer capacity of the proposed method is larger than that of the traditional circuit.These results verify the modeling of the transfer function in Section 3 and the Bode plot analysis shown in Figure 10.
Energies 2018, 11, x 12 of 14 capacity of the proposed method is larger than that of the traditional circuit.These results verify the modeling of the transfer function in Section 3 and the Bode plot analysis shown in Figure 10.

Analysis of the Data Transfer Rate
Equation (20) shows that in order to increase the data transfer rate, we can either increase the conventional data transfer rate or the conduction duty cycle of Sd. Figure 14a shows the case by increasing the conventional data transfer rate, while Figure 14b indicates the case by increasing the conduction duty cycle of Sd.

Analysis of the Data Transfer Rate
Equation (20) shows that in order to increase the data transfer rate, we can either increase the conventional data transfer rate or the conduction duty cycle of S d .Figure 14a shows the case by increasing the conventional data transfer rate, while Figure 14b indicates the case by increasing the conduction duty cycle of S d .
Energies 2018, 11, x 12 of 14 capacity of the proposed method is larger than that of the traditional circuit.These results verify the modeling of the transfer function in Section 3 and the Bode plot analysis shown in Figure 10.

Analysis of the Data Transfer Rate
Equation (20) shows that in order to increase the data transfer rate, we can either increase the conventional data transfer rate or the conduction duty cycle of Sd. Figure 14a shows the case by increasing the conventional data transfer rate, while Figure 14b indicates the case by increasing the conduction duty cycle of Sd.Both Figure 14a,b show the output voltage is controlled to be around 16 V.In addition, the data transfer rate can be increased through these two methods, i.e. by increasing the conventional data transfer rate or increasing the conduction duty cycle of S d .

Comparasion Results with the Published Literatures
Table 2 shows the comparison results between the proposed method and the traditional ways studied in [13][14][15][16][17][18].Since the power transfer and data transfer functions of the proposed method are decoupled, the SNR is very high, so as the data transfer rate can reach 560 kbps.It should noted that a 25 W prototype was set up for demonstration.This method could be used in high power systems due to its high SNR characteristics.Moreover, the data transfer method is especially suitable to monitor the load status in WPT applications such as biomedical implants and robot charging.

Conclusions
This paper proposes a decoupled wireless power and data transmission method via the same inductive link.The method system presents two particular features.The first is that a hysteresis controller controls the power flow.This makes it easy to realize miniaturization for non-inductive design at the secondary side.The second is that data is transferred when the output capacitor is free running to achieve uninterrupted power output.Therefore, the interference between power and data flow is very small.Our Bode plots analysis verifies the effectiveness of the proposed data transfer method.Furthermore, an experimental prototype is built according to the proposed method, where the power and data transfer frequencies are 91 kHz and 10 MHz, respectively.The output power is 25 W with an efficiency of 71%, and the data transfer bit rate reaches 560 kbps.

Figure 1 .
Figure 1.Power transfer circuit with hysteresis voltage control.Figure 1.Power transfer circuit with hysteresis voltage control.

Figure 1 .
Figure 1.Power transfer circuit with hysteresis voltage control.Figure 1.Power transfer circuit with hysteresis voltage control.

Figure 2 .
Figure 2. Waveforms to illustrate the hysteresis control.

Figure 3 .
Figure 3.The proposed diagram of power and data transmission.

Figure 2 .
Figure 2. Waveforms to illustrate the hysteresis control.

Figure 2 .
Figure 2. Waveforms to illustrate the hysteresis control.

Figure 3 .
Figure 3.The proposed diagram of power and data transmission.

Figure 3 .
Figure 3.The proposed diagram of power and data transmission.

Figure 2 .
Figure 2. Waveforms to illustrate the hysteresis control.

Figure 3 .
Figure 3.The proposed diagram of power and data transmission.

Figure 5 .
Figure 5. Circuit of the two working modes: (a) S is on and Sd is off; (b) Sd is on and S is off.

Figure 5 .
Figure 5. Circuit of the two working modes: (a) S is on and S d is off; (b) S d is on and S is off.

Figure 6 .
Figure 6.The simplified power transfer circuit: (a) without data receiver circuit; (b) with data receiver circuit.

Figure 6 .
Figure 6.The simplified power transfer circuit: (a) without data receiver circuit; (b) with data receiver circuit.

Figure 7 .
Figure 7.The simplified data transfer circuit: (a) proposed data transfer circuit; (b) traditional data transfer circuit.

Figure 7 .
Figure 7.The simplified data transfer circuit: (a) proposed data transfer circuit; (b) traditional data transfer circuit.

Figure 9 .
Figure 9. Bode plot of the interference from power transfer to data transfer.

Figure 9 .
Figure 9. Bode plot of the interference from power transfer to data transfer.Figure 9. Bode plot of the interference from power transfer to data transfer.

Figure 9 .
Figure 9. Bode plot of the interference from power transfer to data transfer.Figure 9. Bode plot of the interference from power transfer to data transfer.

Figure 10 .
Figure 10.Bode plots comparison between the proposed and traditional data transfer channel.

Figure 10 .
Figure 10.Bode plots comparison between the proposed and traditional data transfer channel.

Figure 10 .
Figure 10.Bode plots comparison between the proposed and traditional data transfer channel.

Figure 12
shows the experiment results with and without data transfer, where channel 1 indicates the output voltage, channel 4 indicates the voltage of Cp, and channel 2 indicates the output data.

Figure 12 .
Figure 12.The monitored interference of data transfer to power transfer: (a) with data transfer; (b) without data transfer.

Figure 11 .
Figure 11.Detailed power and data transfer circuit of the experimental prototype: (a) detailed power transfer circuit; (b) detailed data transfer circuit.

Figure 11 .
Figure 11.Detailed power and data transfer circuit of the experimental prototype: (a) detailed power transfer circuit; (b) detailed data transfer circuit.

Figure 12
shows the experiment results with and without data transfer, where channel 1 indicates the output voltage, channel 4 indicates the voltage of Cp, and channel 2 indicates the output data.

Figure 12 .
Figure 12.The monitored interference of data transfer to power transfer: (a) with data transfer; (b) without data transfer.

Figure 12 .
Figure 12.The monitored interference of data transfer to power transfer: (a) with data transfer; (b) without data transfer.

Figure 13 .
Figure 13.Comparison between the proposed and traditional data transfer: (a) proposed method; (b) traditional circuit.

Figure 14 .
Figure 14.Increasing of the data transfer rate by: (a) increasing the conventional data transfer rate; (b) increasing conduction duty cycle of Sd.

Figure 13 .
Figure 13.Comparison between the proposed and traditional data transfer: (a) proposed method; (b) traditional circuit.

Figure 13 .
Figure 13.Comparison between the proposed and traditional data transfer: (a) proposed method; (b) traditional circuit.

Figure 14 .
Figure 14.Increasing of the data transfer rate by: (a) increasing the conventional data transfer rate; (b) increasing conduction duty cycle of Sd.

Figure 14 .
Figure 14.Increasing of the data transfer rate by: (a) increasing the conventional data transfer rate; (b) increasing conduction duty cycle of S d .