Energy Balance Control of a Cascaded Multilevel Inverter for Standalone Solar Photovoltaic Applications

Abstract

This paper presents a clock phase-shifting (CPS) energy balance control (EBC) method for cascaded half-bridge multilevel inverters in standalone solar photovoltaic (PV) systems. It is based on the conservation of energy in each cascaded unit. By shifting the phase of the clock pulse of each cascaded unit, a staircase-like output voltage is obtained. The CPS EBC not only regulates the staircase-like output voltage of the cascaded multilevel inverters accurately under static conditions, but also suppresses the fluctuations of DC sources and improves its dynamic responses to load steps. Thus, the problems existing in solar PV systems using the cascaded multilevel inverters are avoided. Results obtained from simulations and experiments are presented to verify the feasibility and advantages of the proposed control method.

1. Introduction

Renewable energy sources are becoming increasingly important for electricity generation, since non-renewable energy sources such as fossil fuels are facing serious problems, e.g., pollutions, uncertain future of fossil-fuel prices, being unsustainable and CO₂ emissions [1]. Among these alternative energy sources, solar energy has been identified as being clean and easily available [2]. However, DC power produced by PV modules is not compatible with standard electrical appliances operating with AC power. In order to be compatible with the standard AC electrical appliances, various inverter topologies are proposed and employed to convert the DC electricity to the AC form [1]. Among these topologies, multilevel inverters have been receiving much attention, the most popular of them being cascaded multilevel inverter topologies [3,4], diode-clamped multilevel inverter topologies [5,6] and flying-capacitor multilevel inverter topologies [7,8]. A comparative analysis of the three topologies demonstrates that the cascaded topology is simple and uses the least components. Also, the cascaded topology is ideally suited for solar PV systems, where isolated input DC sources are available. Therefore, the cascaded topology is considered as the most suitable for solar PV systems in all multilevel topologies. Figure 1 displays the block diagram of a standalone solar PV system using a cascaded half-bridge multilevel inverter [9]. Compared with the typical cascaded H-bridge (CHB) multilevel topology, the cascaded half-bridge multilevel topology reduces nearly half the number of required switches. Recently, a cascaded switched-diode topology has been proposed [10,11]. The comparison with cascaded half-bridge multilevel topology illustrates that more voltage levels are produced with fewer required switches. However, under a case of resistance-inductance (R-L) loads, high voltage spikes occur at the base of the stepped output voltage due to the lack of a path for reverse load currents, which tend to deteriorate power quality [12].

Basic modulations techniques for cascaded multilevel topologies are rooted on the fundamental frequency switching [9], sinusoidal pulse width modulation (PWM) [13,14], and space vector PWM (SV-PWM) [15]. However, in solar PV systems, DC sources of a multilevel inverter topology are supplied by PV modules, as shown in Figure 1, which brings about a series of problems:

• Power imbalance: the power of a PV array supplied to each cascaded unit of the multilevel inverter may be different, introduced by cloud shading, different irradiance levels and ambient temperatures.
• DC supply with fluctuations: the DC supply from a PV array is always with fluctuation caused by variety of external factors, such as illumination change, shadow, ambient temperature and etc. More specifically, following variations in a certain range of irradiance level will lead to the instability of the voltage, which manifests as low frequency pulsation.
• Load variations: with the constant expansion of application fields, loads of an inverter are becoming more and more diversified. Abrupt load variations happen regularly.

The existence of these problems cause distortions or bring lots of low harmonics to the output voltages of the cascaded multilevel inverters using basic modulation techniques, which leads great hazards to electrical equipment. In recent years, some nonlinear control methods, e.g., hysteresis control, sliding mode control, fuzzy logic control and so on, have been attempted in multilevel inverters. As presented in [16], the advantages of using various accessible DC voltage levels have been fully exploited by using the hysteresis control. Sliding-mode control (SMC), as presented in [17], provides fast dynamic responses. However, the variable switching frequency and nonzero steady-state error are the drawbacks of these methods. Then in [18], a fuzzy logic control has been proposed. The dynamic behaviours are improved by considering moving cloud obfuscating the PV arrays.

Among the problems in solar PV systems, the power imbalance can be classified into two categories: (1) the inter-phase power imbalance, which occurs when each phase generates different amount of power; and (2) the inter-bridge power imbalance, which happens when each bridge in the same phase generates different amounts of power [19]. A three-phase system focus more on the interphase power imbalance because three-phase unbalanced currents result in wasted power. New control methods [19,20] or converter topology [21] have been proposed to deal with the interphase power imbalance problem of CHB converters in PV systems. In contrast, the interbridge power imbalance gets more attention in single-phase systems. A continuous time-domain power balancing control algorithm was presented to solve the interbridge imbalance of a single-phase CHB converter [22]. However, this method can improve but not completely suppress fluctuations of the DC supply of the multilevel inverter. Thus, the problem of DC supply with fluctuations in PV application has not been solved. A CPS one-cycle control method was proposed for multilevel inverters. While its inhibitory capability to the interbridge power imbalance and variations of input voltage is satisfactory, the inhibitory capability to load changes is still poor [12].

The objective of this paper is to verify the ability of the proposed CPS EBC method to deal with the problems of a multilevel inverter in standalone solar PV applications. The basic structure of this paper is as follows. Section 2 introduces the cascaded half-bridge topology. The derivation of the control equation, the design and implementation of the proposed CPS EBC method are illustrated in Section 3. Section 4 presents the simulation and experimental results. Final conclusions are given in Section 5.

2. Topology of the Cascaded Half-Bridge Multilevel Topology

Figure 1 displays the cascaded half-bridge topology for standalone solar PV applications. The topology is divided into two stages. The first stage is cascaded by n half-bridge converters. The cascaded unit, e.g., unit 1, as shown in Figure 1, contains a DC source supplied from a PV array, the DC voltage of which is equal to $u_1$, switches ${\mathrm{S}}_{11}$ and ${\mathrm{S}}_{12}$. The output of the unit 1 $u_{\mathrm{o}1}$ have two values, which are $u_1$ when switch ${\mathrm{S}}_{11}$ conducts and ${\mathrm{S}}_{12}$ is off, and when switch ${\mathrm{S}}_{11}$ is off and ${\mathrm{S}}_{12}$ is turned on, the value of $u_{\mathrm{o}1}$ is 0. For states of switches ${\mathrm{S}}_{11}$, ${\mathrm{S}}_{12}$, ${\mathrm{S}}_{21}$, ${\mathrm{S}}_{22}$, ⋯, ${\mathrm{S}}_{(n-1)1}$, ${\mathrm{S}}_{(n-1)2}$, ${\mathrm{S}}_{n1}$${\mathrm{S}}_{n2}$, the output voltage of the first stage $u_{\mathrm{g}}$ obtains $2^n$ different values, as listed in

Table 1. Values of $u_{\mathrm{g}}$ under different switch states of the first stage.

State	Switches States									${\mathit{u}}_{\mathbf{g}}$
	${\mathbf{S}}_{11}$	${\mathbf{S}}_{12}$	${\mathbf{S}}_{21}$	${\mathbf{S}}_{22}$	⋯	${\mathbf{S}}_{(\mathit{n}-1)1}$	${\mathbf{S}}_{(\mathit{n}-1)2}$	${\mathbf{S}}_{\mathit{n}1}$	${\mathbf{S}}_{\mathit{n}2}$
1	$\mathrm{off}$	$\mathrm{on}$	$\mathrm{off}$	$\mathrm{on}$	⋯	$\mathrm{off}$	$\mathrm{on}$	$\mathrm{off}$	$\mathrm{on}$	0
2	$\mathrm{on}$	$\mathrm{off}$	$\mathrm{off}$	$\mathrm{on}$	⋯	$\mathrm{off}$	$\mathrm{on}$	$\mathrm{off}$	$\mathrm{on}$	$u_1$
3	$\mathrm{off}$	$\mathrm{on}$	$\mathrm{on}$	$\mathrm{off}$	⋯	$\mathrm{off}$	$\mathrm{on}$	$\mathrm{off}$	$\mathrm{on}$	$u_2$
⋮	⋮	⋮	⋮	⋯	⋮	⋮	⋮	⋮	⋮	⋮
n	$\mathrm{off}$	$\mathrm{on}$	$\mathrm{off}$	$\mathrm{on}$	⋯	$\mathrm{off}$	$\mathrm{on}$	$\mathrm{on}$	$\mathrm{off}$	$u_n$
$n+1$	$\mathrm{on}$	$\mathrm{off}$	$\mathrm{on}$	$\mathrm{off}$	⋯	$\mathrm{off}$	$\mathrm{on}$	$\mathrm{off}$	$\mathrm{on}$	$u_1+u_2$
⋮	⋮	⋮	⋮	⋮	⋮	⋯	⋮	⋮	⋮	⋮
$2^n$	$\mathrm{on}$	$\mathrm{off}$	$\mathrm{on}$	$\mathrm{off}$	⋯	$\mathrm{on}$	$\mathrm{off}$	$\mathrm{on}$	$\mathrm{off}$	${\sum }_{i=1}^n{u}_i$

, the maximum of them is given as follows:

$$u_{\mathrm{g}}=u_{\mathrm{o}1}+u_{\mathrm{o}2}+\cdots +u_{\mathrm{o}n}.$$

(1)

From Table 1, it can be observed that the first stage generates a positive output voltage. For generating both positive and negative values, the second stage, which is a full-bridge inverter, is required.

Table 2. Values of $u_{\mathrm{o}}$ under different switch states of the second stage.

State	Switches States				${\mathit{u}}_{\mathbf{o}}$	$\mathbf{Condition}$
	${\mathbf{S}}_1$	${\mathbf{S}}_2$	${\mathbf{S}}_3$	${\mathbf{S}}_4$
1	$\mathrm{on}$	$\mathrm{off}$	$\mathrm{off}$	$\mathrm{on}$	$u_{\mathrm{g}}$	$u_{\mathrm{ref}}>0$
2	$\mathrm{off}$	$\mathrm{on}$	$\mathrm{on}$	$\mathrm{off}$	$-u_{\mathrm{g}}$	$u_{\mathrm{ref}}<0$

lists the obtained output voltage $u_{\mathrm{o}}$ under different switch states. Through the judgement of the positive or the negative sign of a reference voltage $u_{\mathrm{ref}}$, both the positive and negative halves of $u_{\mathrm{o}}$ are achieved.

Under the symmetric case, that is, all the DC sources are equal to $u_{\mathrm{dc}}$, the total number of required switches $N_{\mathrm{IGBT}}$ against the output voltage levels $N_{\mathrm{level}}$ are shown as follows,

$$N_{\mathrm{IGBT}}=N_{\mathrm{level}}+3.$$

(2)

Compared with the CHB multilevel topology ($N_{\mathrm{IGBT}}=2(N_{\mathrm{level}}-1)$), the cascaded half-bridge multilevel topology reduces nearly half the number of required switches. However, in designing such a multilevel topology, it should be noted that the switches of the full-bridge converter ${\mathrm{S}}_1$, ⋯, ${\mathrm{S}}_4$ have to withstand the total voltage of all cascaded units, while the switches of the first stage ${\mathrm{S}}_{11}$, ${\mathrm{S}}_{12}$, ⋯, ${\mathrm{S}}_{n1}$, ${\mathrm{S}}_{n2}$ only withstand a fraction of the total voltage of all cascaded units. This indicates that the four switches in the full-bridge cell of the second stage are with a high capability of the voltage rating, which makes the total voltage rating increase and leads to the limitation of the high voltage applications. Thus, the cascaded half-bridge multilevel topology is more suitable for medium voltage ($2.3,3.3,4.16$ or $6.9\mathrm{kV}$) applications [23].

3. The CPS EBC Method for Cascaded Half-Bridge Multilevel Topology

3.1. The Design of the CPS EBC

According to the topology analysis in Section 2, the second stage implements the generation of the positive and negative halves of output voltage by comparing the reference voltage $u_{\mathrm{ref}}$ with zero. Thus, the second stage in Figure 1 can be omitted. Then a topology is constructed for the design of the CPS EBC, as shown in Figure 2. Compared with Figure 1, it can be seen that the second stage is omitted.

Figure 3 shows the structure of the proposed CPS EBC method to control the topology shown in Figure 2. The structure displays that a CPS EBC contains n independent EBC controllers. Each independent EBC controller corresponds to a cascaded unit, for instance, the EBC controller 1 in Figure 3 is used for controlling cascaded unit 1, which is the part of the dotted box in Figure 2. The n independent EBC controller are similar but with a $T_{\mathrm{s}}/n$ phase-shift of the clock pulse, where $T_{\mathrm{s}}$ denotes the switching cycle of the multilevel inverter. For an example of cascaded unit 1, the control equation of the EBC controller 1 is derived as follows. From Figure 2, it can be seen that the part of the dotted box can be regarded as a buck circuits: the circuit, constructed by $u_1$, ${\mathrm{S}}_{11}$, ${\mathrm{S}}_{12}$, L, C. Then similar to that of [24], the control principle of the EBC controller 1 is that, by keeping the balance between the energy injected into the circuit from DC sources $W_{\mathrm{in}1}\left(k\right)$ and the sum of the output energy $W_{\mathrm{out}1}\left(k\right)$ and the energy the inductor L stores $\mathrm{\Delta }{W}_{\ell }\left(k\right)$ in a switch cycle, e.g., the $k^{\mathrm{th}}$ switching cycle $[(k-1)T_{\mathrm{s}},k{T}_{\mathrm{s}})$ [24], the EBC controller forces the output voltage to be a desired value , as

$$W_{\mathrm{in}1}\left(k\right)=W_{\mathrm{out}1}\left(k\right)+\mathrm{\Delta }{W}_{\ell }\left(k\right)(k=1,2,\cdots )$$

(3)

During the $k^{\mathrm{th}}$ switching cycle, the part of the dotted box in Figure 2 operates as a buck converter in two states. In state 1, ${\mathrm{S}}_{11}$ is on for the duration $t_{\mathrm{on}1}\left(k\right)$. In this switching state, DC sources injects energy into the circuit and $i_{\mathrm{g}}=\left|i_{\ell }\right|$ flows through the loop ($u_1\to {\mathrm{S}}_{11}\to \mathrm{L}\to \mathrm{C}\parallel \mathrm{R}\to {\mathrm{S}}_{n2}\to {\mathrm{S}}_{(n-1)2}\to \cdots \to {\mathrm{S}}_{22}\to {\mathrm{u}}_1$). L is charged, and R consumes energy, then $u_{\mathrm{o}1}$ is obtained using

$$u_{\mathrm{o}1}\left(t\right)=u_1(t\in [(k-1)T_{\mathrm{s}},(k-1)T_{\mathrm{s}}+t_{\mathrm{on}1}\left(k\right))$$

(4)

In state 2, ${\mathrm{S}}_{11}$ is turned off and ${\mathrm{S}}_{12}$ is on for the duration $t_{\mathrm{off}1}\left(k\right)$. In this switching state, no energy is fed into the circuit, and $i_{\mathrm{g}}=\left|i_{\ell }\right|$ flows through the loop (${\mathrm{S}}_{12}\to \mathrm{L}\to \mathrm{C}\parallel \mathrm{R}\to {\mathrm{S}}_{n2}\to {\mathrm{S}}_{(n-1)2}\to \cdots \to {\mathrm{S}}_{12}$). L is discharged, and R consumes energy. Then $u_{\mathrm{o}1}$ is obtained using

$$u_{\mathrm{o}1}\left(t\right)=0(t\in [(k-1)T_{\mathrm{s}}+t_{\mathrm{on}1}\left(k\right),k{T}_{\mathrm{s}})$$

(5)

The above analysis of the operation states illustrates that the DC source $u_1$ of the cascaded unit 1 works in the time interval [$(k-1)T_{\mathrm{s}}$, $(k-1)T_{\mathrm{s}}+t_{\mathrm{on}1}\left(k\right)$), while L and R operate in the entire switching cycle. The energy values of $W_{\mathrm{in}1}\left(k\right)$, $W_{\mathrm{out}1}\left(k\right)$ and $\mathrm{\Delta }{W}_{\ell 1}\left(k\right)$ during the $k^{\mathrm{th}}$ switching cycle are calculated as follows:

$$W_{\mathrm{in}1}\left(k\right)={\int }_{(k-1)T_{\mathrm{s}}}^{(k-1)T_{\mathrm{s}}+t_{\mathrm{on}1}\left(k\right)}{u}_1\left(t\right)i_{\mathrm{g}}\left(t\right)dt$$

(6)

as $i_{\mathrm{g}}=\left|i_{\ell }\left(t\right)\right|$, then $W_{\mathrm{in}1}\left(k\right)$ is derived as below:

$$W_{\mathrm{in}1}\left(k\right)={\int }_{(k-1)T_{\mathrm{s}}}^{(k-1)T_{\mathrm{s}}+t_{\mathrm{on}1}\left(k\right)}{u}_1\left(t\right)\left|i_{\ell }\left(t\right)\right|dt$$

(7)

$$W_{\mathrm{out}1}\left(k\right)={\int }_{(k-1)T_{\mathrm{s}}}^{(k-1)T_{\mathrm{s}}+T_{\mathrm{s}}}|u_{\mathrm{ref}1}\left(t\right)\Vert i_{\mathrm{o}}\left(t\right)|dt$$

(8)

$\mathrm{\Delta }{W}_{\ell 1}\left(k\right)$ is calculated as the following:

$$\mathrm{\Delta }{W}_{\ell 1}\left(k\right)={\int }_{(k-1)T_{\mathrm{s}}}^{(k-1)T_{\mathrm{s}}+T_{\mathrm{s}}}|u_{\ell }\left(t\right)\Vert i_{\ell }\left(t\right)|dt$$

(9)

Substituting the values of $W_{\mathrm{in}1}\left(k\right)$, $W_{\mathrm{out}1}\left(k\right)$ and $\mathrm{\Delta }{W}_{\ell }\left(k\right)$ into (3) derives:

$$\begin{array}{c}\hfill {\int }_{(k-1)T_{\mathrm{s}}}^{(k-1)T_{\mathrm{s}}+t_{\mathrm{on}1}\left(k\right)}{u}_1\left(t\right)|i_{\ell }\left(t\right)|dt=|u_{\mathrm{ref}1}\Vert i_{\mathrm{o}}\left(t\right)|T_{\mathrm{s}}+{\int }_{(k-1)T_{\mathrm{s}}}^{k{T}_{\mathrm{s}}}|u_{\ell }\left(t\right)\Vert i_{\ell }\left(t\right)|dt(k=1,2,\cdots )\end{array}$$

(10)

Combining the aforementioned state analysis, (10) can be realized by controlling $u_{\mathrm{o}1}$, which is expressed in

$$\begin{array}{c}\hfill {\int }_{(k-1)T_{\mathrm{s}}}^{k{T}_{\mathrm{s}}}{u}_{\mathrm{o}1}\left(t\right)|i_{\ell }\left(t\right)|dt=|u_{\mathrm{ref}1}\Vert i_{\mathrm{o}}\left(t\right)|T_{\mathrm{s}}+{\int }_{(k-1)T_{\mathrm{s}}}^{k{T}_{\mathrm{s}}}|u_{\ell }\left(t\right)\Vert i_{\ell }\left(t\right)|dt(k=1,2,\cdots )\end{array}$$

(11)

3.2. The Implementation of CPS EBC

As a part of the control reference, $|u_{\mathrm{ref}1}\Vert i_{\mathrm{o}}\left(t\right)|T_{\mathrm{s}}$ is calculated instantaneously. The other part ${\int }_{(k-1)T_{\mathrm{s}}}^{k{T}_{\mathrm{s}}}|u_{\ell }\left(t\right)\Vert i_{\ell }\left(t\right)|dt$ is calculated in the instant of the beginning of the $k^{\mathrm{th}}$ switching cycle and kept the same during the entire switching cycle. Note here, the value of ${\int }_{(k-1)T_{\mathrm{s}}}^{k{T}_{\mathrm{s}}}|u_{\ell }\left(t\right)\Vert i_{\ell }\left(t\right)|dt$ is collected only in the time point $k^{\mathrm{th}}$ $T_{\mathrm{s}}$, thus there is a switching cycle lag. The errors due to this switching cycle lag are ignored here, since the duration of the switching cycle is short. This means that the value used in the $k^{\mathrm{th}}$ switching cycle is actually the value obtained in the ${(k-1)}^{\mathrm{th}}$ switching cycle.

After the computation of the control reference, the CPS EBC method is implemented with comparison and integration as shown in Figure 3. Here, the implementation of the EBC controller 1 is described as follows. When ${\mathrm{S}}_{11}$ is turned on by a clock pulse with fixed frequency, the integral operation starts and $u_{\mathrm{o}1}\left(t\right)=u_1$. Thus the output of the integrator $W_{\mathrm{int}1}\left(t\right)$ is calculated as follows:

$$\begin{array}{c}\hfill W_{\mathrm{int}1}\left(t\right)={\int }_{(n-1)T_{\mathrm{s}}}^t{u}_{\mathrm{o}1}\left(t\right)|i_{\ell }\left(t\right)|dt={\int }_{(n-1)T_{\mathrm{s}}}^t{u}_1\left|i_{\ell }\left(t\right)\right|dt\end{array}$$

(12)

as time goes on, $W_{\mathrm{int}1}\left(t\right)$ increases from its initial value and is compared with the control reference instantaneously. At the instant when $W_{\mathrm{int}1}\left(t\right)$ reaches $W_{\mathrm{out}1}\left(k\right)+\mathrm{\Delta }{W}_{\ell 1}\left(k\right)$, a reset pulse is generated by the comparator to reset the RS flip-flop to be ($Q=0$). Then ${\mathrm{S}}_{11}$ is turned off, while ${\mathrm{S}}_{12}$ is turned on. At the same time, $W_{\mathrm{int}1}\left(t\right)$ is reset to zero. The switching state is kept until the arrival of the next clock pulse, which starts the ${(k+1)}^{\mathrm{th}}$ switching cycle.

As the design and implementation for other EBC controllers are similar to that of the EBC controller 1, the details are not presented here.

4. Simulation and Experimental Results

When designing solar PV fed inverters, the estimation of PV characteristics and maximum power point tracking (MPPT) control are one focus for solar PV modelling, meanwhile another way to simulate PV arrays employs a DC power supply with variable output voltage. Concerning stand-alone PV systems, the extraction of energy from PV arrays depends on the load demand [18,25]. In this research, on the premise of guaranteeing the installed output power of PV arrays, each PV array is only simulated by a V-I characteristic with an open-circuit voltage that is equal to $80\mathrm{V}$. It should be noticed that the PV modelling method employed in this research cannot represent the PV arrays controlled by a MPPT algorithm. At first, a five-level and nine-level two-stage half-bridge multilevel inverter with a switching frequency of 2,500$\mathrm{Hz}$ are set up. The parameters are $u_1=u_2=\cdots =u_n=80\mathrm{V}$, $R=50\mathsf{\Omega }$, $L=16\mathrm{mH}$, $C=10\mu F$, $u_{\mathrm{ref}1}=u_{\mathrm{ref}2}=\cdots =u_{\mathrm{ref}n}=60\mathrm{V}$. Then a five-level experimental prototype, the parameters of which are identical with that of the simulation model, is built. In the experimental prototype shown in Figure 4, the voltage and current are sampled by the measurement, which is made up of HALL voltage sensors CHV-25P/100 (Measurement range: 0–$\pm 150\mathrm{V}$; Measurement accuracy: $\pm 0.1\%$) and HALL current sensors CHB-25NP/6 A (Measurement range: 0–$\pm 9\mathrm{A}$; Measurement accuracy: $\pm 0.8\%$), respectively. The gate drivers of the IGBT are configured on SKYPER 32R (SEMIKRON, Nuremberg, Germany), which are powered with the DC power source ($0/15\mathrm{V}$). In the experiment, PV arrays are emulated by DC power with variable output voltage and a function generators. The function generator TFG1900B (Suin Instuments, Nanjing, China) is connected in series with the DC power, which generate fluctuations (here is the low frequency ripples) to simulate the variations in irradiance and temperature of PV array outputs. The overall control strategy is implemented on a DS1104 (dSPACE company, Padbourne, Germany) system, where the proposed CPS EBC controller was programmed for the five-level half-bridge cascaded multilevel inverter.

To reveal the limitations of the conventional controller for solar PV applications, a carrier phase-shifted sinusoidal pulse width modulation (CPS SPWM) controller is configured. Although in recent years some nonlinear control methods have been attempted for controlling multilevel inverters, the CPS SPWM controller based on the sinusoidal PWM is still the most typical modulation strategy in cascade multilevel converter applications, as the CPS SPWM has the advantages of low-switching technique, balancing switching loads and good harmonic characteristics. The comparative studies demonstrate the ability to suppress DC source fluctuations and the improved dynamic responses to load variations using the CPS EBC. A comparison is made with the CPS SPWM because it is most frequently used for controlling cascaded multilevel inverters.

4.1. The Operation of CPS EBC

Figure 5 shows the gate signals of the cascaded half-bridge multilevel inverter. From Figure 5a, it can be seen that when ${\mathrm{S}}_{11}$ is on, ${\mathrm{S}}_{21}$ is off; When ${\mathrm{S}}_{11}$ is turned off, ${\mathrm{S}}_{21}$ is on. The gate signals of the second stage are shown in Figure 5b. ${\mathrm{S}}_1$ and ${\mathrm{S}}_4$ are on-state when $u_{\mathrm{ref}}\ge 0$. In this switching state, $u_{\mathrm{o}}=u_{\mathrm{g}}$. When $u_{\mathrm{ref}}<0$, ${\mathrm{S}}_1$ and ${\mathrm{S}}_4$ are turned off and ${\mathrm{S}}_2$ and ${\mathrm{S}}_3$ are turned on. In this switching state, $u_{\mathrm{o}}=-u_{\mathrm{g}}$ for the negative half cycle. By judging the sign of $u_{\mathrm{ref}}$, both the positive and negative halves of output voltage are obtained.

As shown in Figure 6a, the output of the first stage $u_{\mathrm{g}}$, which is the sum of the output voltage of all the cascaded units, has positive and zero values. The output current $i_{\mathrm{g}}$ of the first stage is also positive. The voltage between points A and B $u_{\mathrm{AB}}$, the output voltage $u_{\mathrm{o}}$ and the inductor current $i_{\ell }$ of the multilevel inverter are shown in Figure 6b. From the waveforms in the figure, it can be seen that $u_{\mathrm{AB}}$ is a staircase waveform with a frequency of $50\mathrm{Hz}$ and an amplitude of $160\mathrm{V}$. After the $(L-C)$ filter, $u_{\mathrm{o}}$ and $i_{\ell }$ are almost sinusoidal waveforms. Figure 7a demonstrates that the total harmonic distortion (THD) of $u_{\mathrm{AB}}$ of the five-level simulation prototype is 35.65% and the frequencies that the main harmonics focus on is multiples of 5000 $\mathrm{Hz}$ (5000$\mathrm{Hz},$ 10,000$\mathrm{Hz},$ 15,000$\mathrm{Hz},\dots$), where 5,000$\mathrm{Hz}$ is twice of the switching frequency (2500$\mathrm{Hz}$).

Figure 8 illustrates the simulation results of the operation of a nine-level multilevel topology. It is observed from Figure 8a that $u_{\mathrm{g}}$ and $i_{\mathrm{g}}$ have zero and positive values. Figure 8b shows the waveforms of $u_{\mathrm{AB}}$, $u_{\mathrm{o}}$ and $i_{\ell }$ of the nine-level multilevel topology. The waveforms in the figure demonstrate that $u_{\mathrm{AB}}$ is a staircase waveform with a frequency of $50\mathrm{Hz}$ and an amplitude of $320\mathrm{V}$. After the $(L-C)$ filter, $u_{\mathrm{o}}$ and $i_{\ell }$ are almost sinusoidal waveforms. The THD of $u_{\mathrm{AB}}$ of the nine-level multilevel inverter is 16.96%, as shown in Figure 7b. The frequencies that the main harmonics focus on is multiples of 10,000 Hz (10,000 Hz, 20,000 Hz, 30,000 Hz,…), where 10,000 Hz is four times of the switching frequency 2500 Hz. The comparison with THD of $u_{\mathrm{AB}}$ of the five-level prototype, the THD is reduced and the frequencies that the main harmonics focus on move backward, which reduces the designing standards of the output filter.

The experimental results of the five-level prototype using the CPS EBC are shown in Figure 9 and Figure 10. The figures illustrate that the results are consistent with the simulation results in Figure 6. $u_{\mathrm{g}}$ and $i_{\mathrm{g}}$ of the first stage are positive. $u_{\mathrm{AB}}$ is a five-level staircase waveform. The THD of $u_{\mathrm{AB}}$ is 42.18% and the frequencies that the main harmonics focus on is (5000 Hz, 10,000 Hz, 15,000 Hz, …) , as shown in Figure 10a. After the $(L-C)$ filter, $u_{\mathrm{o}}$ and $i_{\ell }$ are sinusoidal waveforms. The THD of $u_{\mathrm{o}}$ is 2.40%, as shown in Figure 10b.

The above simulation and experimental results verify the feasibility of the CPS EBC method for the cascaded half-bridge multilevel inverter in standalone solar PV applications.

4.2. The Suppression Ability of the CPS EBC against Interbridge Power Imbalance in DC Sources

To evaluate the ability of the CPS EBC to suppress the power imbalance of the PV arrays, DC sources ($u_1,u_2,\cdots ,u_n$ ) are designed by different DC voltages. The simulation and experimental results are demonstrated in Figure 11.

Figure 11a shows the simulation results under power imbalance (under the obfuscation of cloud shadowing, the PV unit 1 ($u_1$) is with a voltage drop $15\mathrm{V}$). The comparison results demonstrate that $u_{\mathrm{o}}$ using CPS SPWM tracks its reference $120\mathrm{V}$ with a drop $18\mathrm{V}$. In contrast, $u_{\mathrm{o}}$ using CPS EBC tracks its reference with no voltage drop. Figure 11b display the experimental results using the CPS EBC and the CPS SPWM under the cases of power imbalance. From the comparisons, it can be observed that the experimental results are consistent with the simulation results in Figure 11a. Thus the ability of the proposed CPS EBC against the interbridge power imbalance is verified.

4.3. The Suppression Ability of the CPS EBC against Interferences in DC Sources

To evaluate the ability of the CPS EBC to suppress the fluctuations of DC sources, DC sources ($u_1,u_2,\cdots ,u_n$ ) are designed by DC voltage mixed with low frequency interferences. The simulation and experimental results are demonstrated in Figure 12, Figure 13, Figure 14 and Figure 15.

Figure 12a shows the simulation results under unbalance DC voltages (a ripple with a frequency $100\mathrm{Hz}$ and an amplitude $16\mathrm{V}$ is added in $u_1$). The comparison results demonstrate that $u_{\mathrm{o}}$ using CPS SPWM is not a ideal sine wave but with distortions. The FFT analysis in Figure 13a shows low order harmonic voltages are contained in $u_{\mathrm{o}}$. In comparison, $u_{\mathrm{o}}$ using the CPS EBC is kept as a ideal sine wave. No low order harmonic voltages are brought into $u_{\mathrm{o}}$, as shown in Figure 13a. Similarly, under the DC voltages mixed with low frequency ripples ($100\mathrm{Hz}$ ripples with an amplitude $8\mathrm{V}$ are added in $u_1$ and $u_2$, respectively). The comparison results in Figure 12b illustrate that $u_{\mathrm{o}}$ using the CPS SPWM distorts due to the low order harmonic voltages. However, $u_{\mathrm{o}}$ using the CPS EBC, is kept as a ideal sine wave. This can also be observed from the comparison of the FFT analysis in Figure 13b. Figure 14 and Figure 15 display the experimental results using the CPS EBC and the CPS SPWM under the cases of unbalanced DC voltage and DC voltage with fluctuations. From the comparisons, it can be observed that the experimental results are consistent with the simulation results in Figure 12. All the comparison results of the THD of $u_{\mathrm{o}}$ under the cases of unbalance DC voltages and DC voltages containing low frequency ripples are summarized in

Table 3. Simulation and Experimental results under DC voltages with fluctuation.

	Cases	Simulation		Experiment
		CPS EBC	CPS SPWM	CPS EBC	CPS SPWM
THD (%)	Unbalance DC sources	1.30	7.22	2.90	9.11
	DC sources with fluctuation	1.07	6.59	2.74	8.89

. The figures and tables verify that the CPS EBC has strong inhibitions against fluctuations of DC sources.

4.4. The Dynamic Responses of CPS EBC to Load Variations

To evaluate the dynamic performances of the proposed CPS EBC, the responses to variations in the load of the converter using the CPS EBC is compared with that of the CPS SPWM. Figure 16 and Figure 17 demonstrate the comparison results.

In the simulation and experiment, the load steps from $50\mathsf{\Omega }\to 25\mathsf{\Omega }$ at $t=0.045\mathrm{s}$ and $25\mathsf{\Omega }\to 50\mathsf{\Omega }$ at $t=0.105\mathrm{s}$. The comparison results of the voltage shoot $\mathrm{\Delta }{u}_{\mathrm{o}}$ and the settling time $t_{\mathrm{settling}}$ of the dynamic responses to the load variations are summarized in

Table 4. Simulation and Experimental results under load variations.

	R ($\mathbf{\Omega })$	CPS EBC		CPS SPWM
		$\mathbf{\Delta }{\mathit{u}}_{\mathbf{o}}\left(\mathbf{V}\right)$	${\mathit{t}}_{\mathbf{settling}}\left(\mathbf{ms}\right)$	$\mathbf{\Delta }{\mathit{u}}_{\mathbf{o}}\left(\mathbf{V}\right)$	${\mathit{t}}_{\mathbf{settling}}\left(\mathbf{ms}\right)$
Simulation	50 → 25	$-10$	0.9	$-26$	1.9
	25 → 50	18	1.2	32	2
Experiment	50 → 25	−16	1.2	−32	2.2
	25→ 50	18	1.4	36	2.3

. From the figures and table, it can be observed that, under the load variation, $\mathrm{\Delta }{u}_{\mathrm{o}}$ and $t_{\mathrm{settling}}$ are significantly reduced by using the proposed CPS EBC. For instance, under the load variation from $50\mathsf{\Omega }$ to $25\mathsf{\Omega }$, the simulation results of $\mathrm{\Delta }{u}_{\mathrm{o}}$ is reduced from $-26\mathrm{V}$ (using CPS SPWM) to $-10\mathrm{V}$ (using CPS EBC) and $t_{\mathrm{settling}}$ is reduced from $1.9\mathrm{ms}$ (using CPS SPWM) to $0.9\mathrm{ms}$ (using CPS EBC).

Thus, the improved dynamic responses to load variations of the CPS EBC method are verified from the above simulation and experimental results.

5. Conclusions

The CPS EBC method has been proposed and implemented for controlling the cascaded half-bridge multilevel inverters for standalone solar PV applications. It is composed by n similar but independent EBC controllers. DC sources mixed with fluctuations are designed to simulate the DC voltage supplied by the solar PV arrays. Simulation and experimental results demonstrate that, by shifting the phase of the clock pulse of each cascaded half-bridge, staircase-like voltage waveforms are obtained. Under the cases of unbalance DC voltage, DC voltages with low frequency ripples and load variations, the comparison results between the CPS EBC and the CPS SPWM method reveal that the CPS EBC produces a superior ability in suppressing the fluctuations in DC voltages and improved dynamic performances under load variations, in terms of shorter settling time and smaller voltage shoots. Thus, the distortions of the output voltage of the solar PV systems, due to the power imbalance, the DC supply with fluctuations are avoided. Meanwhile the dynamic responses to load variations are improved. These results illustrate that the CPS EBC method is more suitable than the CPS SPWM to control multilevel inverters for standalone solar PV applications.