# A Flexible Experimental Laboratory for Distributed Generation Networks Based on Power Inverters

^{1}

^{2}

^{*}

## Abstract

**:**

## 1. Introduction

## 2. Experimental Network Implementation

_{12}, Z

_{23}, Z

_{34}and Z

_{g}) emulate the wires that connect different nodes geographically dispersed and the grid. Each node can feed its own local load R

_{Local i}and collaboratively a common load R

_{Common}located near the AC source. The resistive loads are implemented using low-cost single-phase heaters connected in wye configuration with a floating neutral node. The basic control functionalities of each node are implemented in dedicated digital signal processors (DSP). An Ethernet link between nodes provides a communication channel which is used to implement higher level controllers in the DSPs. These controllers can be implemented distributedly between nodes or centralized in one of them, which can be viewed as a central controller. A computer is also linked to the Ethernet network in order to supervise and visualize the system behavior in real time. The same computer is used to program and debug the control algorithms that will run in the DSPs. Table 2 summarizes the main component and parameter values. Each node consists of a power inverter fed by the DC source which can be programmed to maintain an ideal constant voltage at its output or to emulate a photovoltaic panel (i.e., voltage drooping as the supplied current grows). The inverter is composed by three main building blocks: the power stack; a damped LCL filter formed by a discrete power inductor and capacitor and the parasitic elements of an isolation transformer (see Figure 2); and the control platform. The next subsections will describe the main parts of the nodes.

#### 2.1. Control Platform

^{®}Cortex™-M3 core. Each processor is completely independent, with its own memory, peripherals, interruptions controller and ROM/RAM memory. Each core executes its own code separately to maximize their performance: one responsible for the real-time control processes and the other accounting for the communication protocols.

#### 2.2. Power Stack

_{o}= 1.5 mF) forms the DC-link. A three-phase full bridge plus a brake IGBT module configures the main core of the power stack.

#### 2.3. Output Filter

_{f}, a capacitor bank C

_{f}with damping resistors R

_{d}to attenuate the filter resonance, and a wye-delta transformer (wye connection at the inverter side). This transformer introduces the output inductance L

_{T}of the filter and ensures isolation between the input and the output of the inverter. Also it introduces some parasitic resistance useful to emulate R/L lines (R

_{T}). The RC branch of the LCL filter is wye-connected, with a floating neutral node, as the usual implementation described in the literature.

## 3. Control

**v**vector and currents

**i**(in the inverter output) and

_{1}**i**(in the LC filter output) using an analog isolated sensing board. Also the DC-link voltage v

_{2}_{DC}is sensed. For each three-phase current vector only two phase currents are sensed, i

_{a}and i

_{b}, being i

_{c}reconstructed taking into account that in a three-phase three-wire system:

_{a}+ i

_{b}+ i

_{c}= 0

**v**, only two phase to phase voltages are sensed v

_{ab}and v

_{bc}. The voltages (including DC-link voltage) are sensed using Lem LV25-P hall effect voltage transducers. The sampling rate of these variables is T

_{s}= 100 μs, i.e., the maximum switching rate of the IGBT switches [46]. Besides local variables, the conventional controls require also data (at a time rate T

_{r}) from other network nodes or from higher hierarchical level controllers. The next subsection deals with the description of the controllers.

#### 3.1. Network-Feeding Controller

**i*** = f (P*, Q*,

**v**)

**v**(i.e., following this voltage reference). Figure 6a shows the simplified diagram of a network-feeding node represented by a power controlled current source wired to the network through the bus

**v**. The impedance L

_{n}_{o}, R

_{o}, models the output impedance of the source. Impedance L

_{n}, R

_{n}models the isolation transformer impedances and the line connections between nodes. In this case the converter will inject to the network with active and reactive power by ensuring that

**i**=

**i***. This objective will be accomplished by the conventional inner current control loop: a PRES controller over the

**i**current error with a feed-forwarding term

_{1}**v**driving a space vector modulator that provides the control signals for the IGBT bridge a

_{T}– a

_{B}(leg a, top and bottom switch respectively), b

_{T}– b

_{B}and c

_{T}– c

_{B}[50,51]. The network-feeding main control scheme can be seen in Figure 5.

**v**can be unbalanced it can be expressed in stationary reference frame (SRF) as:

_{α}

^{+}, v

_{β}

^{+}and v

_{α}

^{−}, v

_{β}

^{−}are the positive and negative sequence voltages respectively, V

^{+}and V

^{−}are their amplitudes, ω is the grid angular frequency, and δ is the phase angle between positive and negative sequences.

**i**must be shaped by the output voltage

**v**, thus in a general form it must be a function of both the positive and the negative sequence voltages. To accomplish this objective a sequence extractor should be used to estimate the sequence voltages from the SRF voltage vector [52,53]. Afterwards, when the sequence voltages are known, the amplitudes of the positive and negative sequences can be calculated on-line using:

_{p}

^{+}, k

_{p}

^{−}, k

_{q}

^{+}, and k

_{q}

^{−}are the active and reactive balancing factors used to flexibly inject power through positive and negative sequences. In a non-dispatchable DGS, the active power reference P* is usually calculated by a local controller using local variables. Its aim is to extract the maximum allowable energy from the source [47,55]. Active power curtailment can also be required to protect the inverter from over currents when a voltage sag occurs [10,11]. When the source is dispatchable the reference active power can be set by a higher level controller. The reactive power reference Q* can be calculated locally or can be set by a higher level controller. When calculated locally, Q* is determined to fulfil the stringent reactive current injection (RCI) requirements set by grid codes during voltage disturbances [12]. RCI can also be used with the aim of supporting the grid voltage when the grid impedance is mainly inductive [13,14]. The reactive power reference for each node can also be determined by a centralized controller when a general voltage control is required [56,57]. In addition, the balancing factors in Equations (9) and (10) can be used to provide ancillary functions to the DGS specially during voltage disturbances [10,58,59]: avoid DC-link voltage oscillation during network voltage unbalancing, provide some voltage support during unbalanced voltage droops, among others. Some degrees of freedom exist in the selection of the balancing parameters. For instance, in this work, two additional ancillary objectives will be defined for the network-feeding nodes working with the control scheme based on Equations (9) and (10). First objective (reduction of DC-link oscillations) will be fulfilled choosing the following relationships between the sequence balancing parameters:

_{p}and k

_{q}taking values between 0 and 1. Then the DC-link oscillations are avoided when injecting active and reactive powers during unbalanced network voltages [54] and, in this case, the injected currents are expressed as:

**v**due to the injected current

**i**must be estimated. Independently of the amount of P* and the origin of Q*, when currents (13) and (14) are injected into the network they will produce some effects over the DGS output voltage

**v**due to the equivalent impedance seen by the converter [58,59]:

^{+}(to restore voltage amplitude) and to reduce the amplitude of the negative sequence voltage V

^{−}(to balance phase voltages) [61]. As Equation (15) clearly shows, the positive sequence of active and reactive currents increases the positive sequence voltage, accomplishing the objective of voltage supporting. On the other hand, as seen in Equation (16), the negative sequence of the reactive current reduces the negative sequence voltage. In this case the negative sequence of the active current increases the negative sequence (increasing phase voltages unbalance). This last effect is a drawback of the proposal described by Equations (13) and (14) with the main objective of avoid DC-link voltage oscillations. Being P* determined by the active power generated in the source, Q* needs to be determined accurately to control the voltage support capabilities. In other words, the practical scenario in which Equations (13) and (14) provide good voltage support is limited to networks with inductive dominant behavior.

#### 3.2. Network-Forming Controller

_{o}, R

_{o}connected to the network at the bus

**v**through an equivalent impedance L

_{n}_{n}, R

_{n}. The usual two nested control loops are programmed in the local controllers: a fast inner current loop with

**i**(as in network-following converters described before) and a slow outer voltage loop used to fix the converter output voltage

_{1}**v**[19] (see Figure 5). The transient response of both loops are accelerated against step changes due to external perturbations with feed-forwarding the output voltage

**v**in the current loop and the output current

**i**in the voltage loop [19]. The main task (i.e., to regulate the voltage) can be accomplished using different approaches: master-slave scheme and multi-master scheme. The first approach is used when only one node acts as voltage source setting its own reference voltage to the network, the others act as network-following converters. This is the simplest way but lacks of flexibility and reliability: if master crashes the complete network collapses, thus requiring a complex protocol to change from slave to master in replacing the failed voltage node. The state-of-the-art multi-master scheme is based in the high reliable voltage droop control to manage different nodes acting as voltage sources [15]. This control is based in three levels of hierarchy: primary, secondary and tertiary control layers [62,63].

_{2}_{o}and V

_{o}are the nominal network angular frequency and voltage amplitude, respectively. The slopes m

_{p}and n

_{q}are the gain parameters to drop proportionally ω

_{o}and V

_{o}regarding the averaged values (low pas filtered) of the instantaneous active and reactive powers:

_{c}is the cut-off frequency of the low pass filter, and s is the Laplace operator. The filter provides noise and harmonic attenuation and besides gives usually a slow response of some seconds, as desired in this application.

_{v}a pure inductance (i.e., R

_{v}= 0 Ω).

_{p}are equal in all the network nodes.

_{r}, several orders of magnitude over the sensing/switching period T

_{s}. In the case of consensus based secondary control scheme, one particular node i only receives data from n neighbors and calculates its own correction terms [23]. A global objective is reached with only partial data through “gossiping” between adjacent nodes. In this work, the correction term for the frequency is dω

_{i}and modifies the primary control as:

_{i}to its nominal value ω

_{o}and to equalize the values of the correction terms dω:

_{j}will be transmitted between the n neighbor nodes.

_{j}and the reactive power supplied to the network Q

_{j}.

_{o}:

## 4. Communications

_{s}launches the main control calculation function in node #1 C28 core. After sensing the input variables, the control core generates the droop primary level signals. Secondary control (35) and (37) is implemented using its own data [ω

_{1}*((k − 1)T

_{s}); dω

_{1}((k − 1)T

_{s}); V

_{1}(kT

_{s}), Q

_{1}(kT

_{s})] and data transmitted from nodes #2 and #3 [dω

_{2}(kT

_{r}), dω

_{3}(kT

_{r}); V

_{2}(kT

_{r}), V

_{3}(kT

_{r}), Q

_{2}(kT

_{r}), Q

_{3}(kT

_{r})] that is available in the C28 core SRAM memory. After obtaining the secondary control values, core C28 calculates the reference values of ω

_{1}* and V

_{1}* using (32) and (36). Finally, C28 stores the local variables: dω

_{1}(kT

_{s}), V

_{1}(kT

_{s}) and Q

_{1}(kT

_{s}) in the shared RAM. A timer interruption at a rating T

_{r}is configured in the M3 core to launch a periodical interruption. When serving this interruption, M3 core reads dω

_{1}, V

_{1}and Q

_{1}from the SRAM, packs these data into an UDP datagram adding also the number of the inverter as the first data [1, dω

_{1}, V

_{1}, Q

_{1}] and sends it to nodes #2 and #3 through UDP.

_{2}(kT

_{r}), V

_{2}(kT

_{r}) and Q

_{2}(kT

_{r}) data and writes them into the shared RAM. Then M3 raises an inter-processor communication interruption to C28 core that will be served by an interrupt handler in the C28 core. When attaining the software interruption, C28 core reads dω

_{2}(kT

_{r}), V

_{2}(kT

_{r}) and Q

_{2}(kT

_{r}) from the SRAM, reads also that the data comes from node #2 and updates node #2 data values in the C28 local controller. When executing the next main control calculation function, C28 core will use the updated variables for calculating the secondary control. A complete description of the protocols implementation can be found in [72] (pp. 397–400).

## 5. Debugging

## 6. Experimental Results

#### 6.1. Test 1, Grid Connected Network under Voltage Sags

**v**. The four converters are programmed as power controlled current sources, emulating, for example, four photovoltaic-generation modules. Buses

_{g}**v**to

_{1}**v**are colored differently to easily identify the measured voltages and powers in the following figures. Each converter is governed by its own active and reactive power references P

_{4}_{i}* and Q

_{i}* (for i = 1 to 4). The global resistive load R

_{L}is located in parallel with the AC-source to avoid injecting all the generated active power (P

_{1}+ P

_{2}+ P

_{3}+ P

_{4}) to this source. Following the operating rules of this two quadrant AC-source, and in order to avoid damaging it, only 25% of the rated active power can be absorbed by the source.

**v**are perfectly balanced at 1 p.u. The four nodes are injecting to the network the same reference powers P

_{g}_{i}* = 500 W and Q

_{i}* = 0 VAr using the reference current calculation scheme (13) and (14), see Figure 12. It must be noted that, being 1.5 kW the load rated power, only 500 W are being absorbed by the grid/AC-source. As can be appreciated in Figure 11, the phase voltages at node #1 (

**v**) present a slightly higher value than at node

_{1}**v**(0.03 p.u. higher). This effect is due to the fact that the impedance seen at the output of the converters has some resistive part (see the transformers data in Table 2), and active currents produce voltage increments (as stated in (15) and (16)). At t = 0 s the sag begins and after a computation delay of 0.01 s due to the sequences extractor [53] the sag is detected. Until t = 0.125 s the sag control is deliberately inactive to clearly show its behavior without any control action. At t = 0.125 s the reference reactive powers are set to Q

_{g}_{i}* = 0.9 kVAr in (13) and (14), thus providing RCI as grid codes require (black dashed line in Figure 12). When the fault is cleared (t = 0.25 s) the RCI is still working during the detection delay of 0.01 s. At t = 0.26 s the voltage restoration is detected and the reactive power reference is reset to 0 VAr. As can be seen in Figure 12 top subfigure, active power references P

_{i}* are set to 0 at t = 0.375 s to clearly show the output voltage without any injection. As can be noted in Figure 11 between t = 0.375 s and t = 0.5 s the voltage vector

**v**is perfectly balanced at 1 p.u. because the nodes are inactive.

_{1}_{i}* = 0.5 kW the current amplitudes must be increased due to the voltage amplitudes have been reduced. The maximum current amplitude appears in the phase with lowest voltage amplitude (purple trace in Figure 11). This last effect is very interesting for voltage support purposes, it maximizes the support in the most perturbed phase [14]. As stated before, at t = 0.125 s RCI starts. In this test the strategy of injecting the maximum allowable current I

_{rated}is chosen [54], and the maximum amplitude current reaches 5 A, also in the most perturbed phase (in purple). After t = 0.375 s the currents are set to 0 A in order to clearly show the node voltages without any injection.

_{ni}(being the sub index i = 1, 2, 3 and 4) in the four nodes are zero. When the sag starts the positive sequences V

_{pi}are reduced to roughly 0.95 p.u. and some negative sequence appears V

_{ni}= 0.09 p.u. due to the voltage imbalance. When RCI starts, positive sequences are increased and negative sequences are decreased as stated in (15) and (16). As can be noted in Figure 10, node #1 presents maximum equivalent inductance (4.6 mH) seen from its terminals, thus maximum voltage support is done at this point, i.e., maximum increase in positive sequence voltage V

_{p}

_{1}. Also it must be noted that the reactive current flowing through line R

_{23}L

_{23}comes from nodes #1 and #2, which increases the voltage increment at this line. The same applies to R

_{34}L

_{34}with a high total current coming from nodes #1, #2 and #3. Node #4 presents a minimum equivalent inductance of 0.6 mH, thus voltage support is minimum at this point. In addition, only a slight decrease in the negative sequence V

_{ni}can be noted in Figure 14 bottom. This minor effect is because of the negative sequence voltage presents a small magnitude and its effect over the reference currents (13) and (14) is also low.

#### 6.2. Test 2a, Islanded Microgrid with Ideal Synchronization

_{Li}. Also the global resistive load R

_{L}must be fed. The last converter (#4) is programmed as a power controlled current source used to emulate different load profiles with dynamically changing references P

_{4}* and Q

_{4}*. The main objective of the three nodes that form the μG will be to share cooperatively the total active and reactive powers. The system is driven by a droop controller (32) and (36) plus a consensus secondary controller over UDP/IP communication protocol. It must be noted that a pure-inductive virtual output-impedance has been programmed in the droop controller (R

_{v}= 0 Ω, L

_{v}= 10 mH, see Table 3).

_{L}and the local loads R

_{L}

_{1}, R

_{L}

_{2}and R

_{L}

_{3}. Node #4 begins to inject P

_{4}* = 0.3 kW and Q

_{4}* = −0.27 kVAr (inductive load) at t = 1 s. Between 1 s and 10 s only node #1 feeds the μG. The apparent power fed by node #1 is 2.5 kVAr. At t = 9 s node #2 begins the phase synchronization obtaining θ from the PLL and using it in (30) and (31). At t = 10 s the reference voltage

**v*** is synchronized with

_{2}**v**and node #2 begins to energize the μG cooperatively with node #1. At t = 20 s node #3 is connected to the grid after its own synchronization period. At t = 25 s node #4 begins a parabolic shape active power generation (emulating a photovoltaic panel), see Figure 16 top.

_{1}_{m}(black trace), correctly placed at 1 p.u. due to the voltage restoration secondary controller.

#### 6.3. Test 2b, Islanded Microgrid with Clock Drift in the DSP Controllers

## 7. Conclusions

## Acknowledgments

## Author Contributions

## Conflicts of Interest

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**Figure 4.**Simplified schematic of the Concerto microcontroller with the peripherals used for control and communications.

**Figure 12.**Test 1, measured instantaneous active and reactive powers of DGS #1, #2, #3 and #4. Active and reactive power references in black dashed lines.

**Figure 18.**Test 2b, active powers and frequencies, islanded μG with control DSPs desynchronized due to clock drifts.

**Figure 19.**Test 2b, active powers and frequencies, islanded microgrid with control DSPs desynchronized due to clock drifts. Only primary controller activated.

Component | Model | Ratings |
---|---|---|

AC source | Pacific Power, 360AMX(T)-UPC32 | Input: 208/240 Vac, 50–60 Hz, 3 phase Output: 0–341 Vac l–n, 16 A, 3 phase |

DC source | Amrel, SPS800-19 | Input: 208/240 Vac, 50–60 Hz, 3 phase Output: 0–800 Vdc, 19 A |

IGBT bridge | Guasch, MTL-CBI0060F12IXHF | V_{dc_max} = 750 V, I_{max_per_phase} = 30 Arms,f _{switch} = 10 kHz |

Isolation transformer | Eremu, 21-10309WW | Dyn11, 3 × 400/3 × 400 Vac, 5 kVAr |

DSP controller | Texas Instruments, Concerto F28M36P63C | |

Current sensors | Talema, AC1025 | 0–25 Adc/ac |

Voltage sensors | Lem, LV25-P | 0–400 Vdc/ac |

Parameter Name | Acronym | Value | Units |
---|---|---|---|

Grid voltage (line to neutral, l–n) | V_{g} | 110 | Vrms |

Grid frequency | f_{g} | 60 | Hz |

DC-link voltage | V_{DC} | 350 | V |

DC-link capacitance | C_{o} | 1.5 | mF |

LC filter inductances | L_{f} | 5 | mH |

LC filter capacitances | C_{f} | 1.5 | μF |

LC filter damping resistors | R_{d} | 68 | Ω |

Transformer equivalent inductance #1, #2 | L_{T}_{1,2} | 1 | mH |

Transformer equivalent resistance #1, #2 | R_{T}_{1,2} | 0.5 | Ω |

Transformer equivalent inductance #3, #4 | L_{T}_{3,4} | 0.6 | mH |

Transformer equivalent resistance #3, #4 | R_{T}_{3,4} | 1.13 | Ω |

Line impedances | Z_{g}, Z_{12}, Z_{23}, Z_{34} | configurable | |

Common resistive load | R_{Common} | 24/48 | Ω |

Local resistive loads | R_{Local} _{1…4} | 48/96 | Ω |

Parameter Name | Acronym | Value | Units |
---|---|---|---|

Node nominal rated power (base power) | S_{b} | 1.5 | kVAr |

Node nominal rated current | I_{rated} | 5 | A rms |

Global load rated power | P_{L} | 1.5 | kW |

Local loads rated power | P_{L}_{1,2,3} | 0.25 | kW |

Droop method virtual inductance | L_{v} | 10 | mH |

Droop method virtual resistance | R_{v} | 0 | Ω |

Line inductance _{12} | L_{12} | 2 | mH |

Line resistance _{12} | R_{12} | 65 | mΩ |

Line inductance _{23} | L_{23} | 0.8 | mH |

Line resistance _{23} | R_{23} | 110 | mΩ |

Line inductance _{34} | L_{34} | 0.8 | mH |

Line resistance _{34} | R_{34} | 110 | mΩ |

Active power reference | P_{i}* | 0.5 | kW |

Reactive power reference nominal conditions | Q_{i}* | 0 | kVAr |

Reactive power reference when sag occurs | Q_{i}* | 0.9 | kVAr |

Sequences balancing parameters | k_{p}, k_{q} | 0.5 | |

Frequency droop parameter | m_{p} | 1 | mrad/(Ws) |

Voltage droop parameter | n_{q} | 10 | mV/(V Ar) |

Proportional gain PRES voltage compensator | k_{pv} | 1 | mA/V |

Integral gain PRES voltage compensator | k_{iv} | 3 | A/(Vs) |

Proportional gain PRES current compensator | k_{pi} | 30 | A^{−1} |

Integral gain PRES current compensator | k_{ii} | 800 | (As)^{−1} |

Sampling and switching rate | T_{s} | 100 | μs |

Transmission rate | T_{r} | 100 | ms |

Parameter Name | Acronym | Value |
---|---|---|

Clock drift rate of digital processor 1 | d_{1} | 1.0000 |

Clock drift rate of digital processor 2 | d_{2} | 1.0001 |

Clock drift rate of digital processor 3 | d_{3} | 0.9999 |

© 2017 by the authors. Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (http://creativecommons.org/licenses/by/4.0/).

## Share and Cite

**MDPI and ACS Style**

Miret, J.; García de Vicuña, J.L.; Guzmán, R.; Camacho, A.; Moradi Ghahderijani, M. A Flexible Experimental Laboratory for Distributed Generation Networks Based on Power Inverters. *Energies* **2017**, *10*, 1589.
https://doi.org/10.3390/en10101589

**AMA Style**

Miret J, García de Vicuña JL, Guzmán R, Camacho A, Moradi Ghahderijani M. A Flexible Experimental Laboratory for Distributed Generation Networks Based on Power Inverters. *Energies*. 2017; 10(10):1589.
https://doi.org/10.3390/en10101589

**Chicago/Turabian Style**

Miret, Jaume, José Luís García de Vicuña, Ramón Guzmán, Antonio Camacho, and Mohammad Moradi Ghahderijani. 2017. "A Flexible Experimental Laboratory for Distributed Generation Networks Based on Power Inverters" *Energies* 10, no. 10: 1589.
https://doi.org/10.3390/en10101589