# A CMOS PSR Enhancer with 87.3 mV PVT-Insensitive Dropout Voltage for Sensor Circuits

^{*}

## Abstract

**:**

## 1. Introduction

_{OUT}

_{,}is designed to be close to the primary LDO regulator output line in which the output voltage is denoted as V

_{OUT_LDO}. The difference between V

_{OUT}and V

_{DD_OUT}of the PSR enhancer defines the dropout voltage. Such the dropout voltage should be made as small as possible in order to offer maximal operation headroom because the price paid for that will be the reduction of sensor supply headroom. More importantly, when the sensor circuit is targeted for low voltage applications, this raises the design challenges about the stability of dropout voltage contributed by the PSR enhancer in context of process, voltage, and temperature (PVT) variation. This is then translated to the problems arising from the stability of the enhancer’s voltage reference, as well as its driving LDO circuit, with the ultimate goal to produce a small dropout voltage which can sustain the proper operation of a PSR enhancer. For an example, consider a dropout voltage of 0.1 V from 1.2 V supply voltage or below in a sensor circuit, this requires a lot of circuit design considerations dedicated to low-power low-supply voltage reference design, as well as scaling regulator design in conjunction with simultaneously addressing PSR concerns. Apart from that, the PSR enhancer serves as an extra block in the sensor applications, thus increasing the cost as the penalty. To relax the issue, the circuit topology of the PSR enhancer should be designed with simplicity. This raises the motivation of this work to design a cost-effective PSR enhancer, not only to improve PSR, but also to produce a stable and small dropout voltage with good immunity against the PVT variation.

## 2. Conventional PSR Enhancer Circuit and Its Design Considerations

_{1}and M

_{2}work in the subthreshold region. As such, the temperature characteristic similar to that of BJT. The V

_{REF}, which is equal to V

_{SG}

_{1}plus V

_{R}

_{1}, is a combination of PTAT and CTAT voltage. The output of OA1 yields the reference voltage as:

_{1}and S

_{2}are the aspect ratio of M

_{1}and M

_{2}, respectively. Thus, a temperature insensitive, V

_{REF}, can be realized through adjusting the ratio of R

_{1}and R

_{2}. Besides, the employment of sub-threshold based MOS transistors permits the reference voltage generator to operate at low supply voltage and consume low power. The OA1, shown in Figure 4, is a PMOS-input two-stage amplifier with a source follower output stage to avoid the resistive loading effect that influences the open-loop function, resulting in the degradation of PSR. Due to the use of source follower, the output headroom is reduced at the trade-off of V

_{REF}and is unable to produce the small dropout voltage design. Regarding the low-dropout voltage design requirement, V

_{REF}denoted in Figure 3, will be scaled in the LDO regulator through the scale factor (1 + R

_{4}/R

_{5}). To minimize the regulator’s circuit complexity, the power transistor stage can be arranged to cascade with the first-stage differential amplifier OA2 to form a two-stage amplifier topology as shown in Figure 5. The well-known cascode compensation technique [17] is applied to obtain a good PSR metric. Finally, the size of each component pertaining to Figure 3, Figure 4 and Figure 5 in the conventional enhancer design is listed in Table 1.

## 3. Proposed PSR Enhancer with PVT-Insensitive Dropout Voltage

#### 3.1. Proposed Enhancer Design

_{8}, the control transistor M

_{7}, the cascode current source with transistors M

_{11}and M

_{12}, and the source follower-based level shifter with transistors M

_{9}and M

_{10}. The intrinsic dc biasing to the control transistor M

_{7}is obtained from the composite transistor (M

_{5}and M

_{6}) with the cascode current source (M

_{13}and M

_{14}) and the pseudo-resistor [19] based low-pass filter (LPF). Further details of the design of LPF will be discussed in the subsequent Section. Of particular note, in order to avoid the influence of leakage effect to the dc biasing of control transistor M

_{7}, high threshold transistors M

_{5}, M

_{6}, and M

_{7}are employed. Such the biasing implementation has the key advantage of eliminating the complicated voltage generator as well as voltage reference in typical FVF regulator design [20]. Good PSR is still obtained due to the use of LPF for filtering the dc supply noise. As the result, the proposed topology offers a more compact topology with respect to that of the conventional counterpart.

_{1}–M

_{4}and M

_{15}–M

_{19}together with the start-up network comprising transistors M

_{20}–M

_{21}and a capacitor C

_{1}. This self-biasing network usually performs PTAT current generation in a conventional design. However, by connecting the gate of triode transistor M

_{3}to the gate of the composite transistor (M

_{1}and M

_{4}), it is possible that the negative temperature coefficient (T.C.) effect of the triode transistor dominates the PTAT effect arising from the current source topology. Consequently, the current source behaves CTAT characteristic. However, the concern is that under high temperature and fast corner case, the transistor M

_{3}may cut off itself. In order to sustain the operating temperature range for 100 degree C, a limited current is injected to the bulk of M

_{3}so as to reduce its threshold voltage.

_{1}, M

_{4}and M

_{2}in the biasing circuit matches the clamping structure formed by M

_{5}, M

_{6}and M

_{7}in the LSFVF toplogy. Therefore, the design has addressed the tracking issue so as to minimize the impact on the dropout voltage in the presence of process variation. Besides, the generated ΔV

_{SG}in each structure is almost independent of supply voltage change. This is translated to the dropout voltage insensitive to the supply voltage. Finally, referring to the temperature compensation, the generated CTAT current will compensate the change of dropout voltage against the temperature. Consider the output voltage of LSFVF regulator, it decreases with increasing temperature due to the PTAT effect of clamping structure (M

_{5}–M

_{7}). In other words, the increase in dropout voltage comes from the increase in temperature. Besides, it is interesting to observe that if the loop produced by the source-gate volage of M

_{8}, the source-gate voltage of M

_{9}and the source-drain voltage of M

_{7}are made negative T.C., it is able to compensate the positive T.C. introduced by the clamping structure (M

_{5}–M

_{7}). However, if a long channel transistor of M

_{7}is employed with small channel length modulation (CLM) effect, its V

_{SD}

_{7}will absorb the temperature-induced voltage change caused by the sum of source-gate voltages through M

_{8}and M

_{9}. Therefore, it may be difficult to impose the negative T.C. voltage change caused by V

_{SG}

_{8}(T) and V

_{SG}

_{9}(T) on V

_{OUT}(T). To tackle the issue, the CTAT current source and the short-channel length M

_{7}with CLM effect are employed in this proposed design; this permits V

_{SD}

_{7}(T) to behave negative T.C. characteristic. Further proof will be given in the subsequent Section. As such, the combined negative T.C. contributed by the temperature compensation transistor structure (M

_{7}–M

_{9}) becomes the key part for temperature compensation. In brief, due to the use of the replica structure, simple temperature compensation in the topological network and all transistor-based designs for obtaining a better tracking characteristic, the dropout voltage of the PSR enhancer is almost independent of PVT variation. This yields a stable output voltage from the enhancer to power the sensor circuit of interest.

#### 3.2. Low-Pass Filter in PSR Enhancer

_{F}and a MOS capacitor C

_{F}. The pseudo resistor comprises 5 units (M

_{R}

_{1}–M

_{R}

_{5}) in series topology to realize a large resistance for use in low frequency, which starts from 1 Hz and above. Due to the extremely large value, high threshold MOS transistors are employed in order to reduce the leakage current. This suggests the potential V

_{C}

_{1}is close to V

_{C}

_{2}. Regarding the MOS capacitor, it is based on a thick-oxide MOS high-threshold transistor with the gate as the top plate terminal and the shorted drain-source and bulk to form the bottom plate terminal. The formation of a large time constant by the LPF will cause the slow start-up of the circuit. To tackle this issue, a digital start-up, which comprises a capacitive start-up network formed by a transistor M

_{22}, six inverter transistors (M

_{23}–M

_{28}), a capacitor C

_{2}and five MOS switching transistors (M

_{29}–M

_{33}), which are connected in parallel with respective pseudo resistor unit, is proposed. When the system is powered on, a peak voltage of V

_{C}

_{3}will appear due to the charging of C

_{2}. Hence, a reversed pulse signal is generated on V

_{C}

_{4}, which will turn on the switches realized by M

_{29}to M

_{33}. This allows V

_{C}

_{1}to charge C

_{F}rapidly. After the pulse signal, all the switches will be turned off. Then, the LPF establishes a RC circuit with a charged C

_{F}to provide the dc biasing. Of particular note, the off resistance of each MOS switch is not infinite. It will reduce the MOS pseudo resistor unit resistance value when paralleling with a non-ideal OFF switch. This leads to the employment of five serial pseudo resistors. Nevertheless, the effective silicon area of each pseudo resistor is considered small. The penalty for the increase of pseudo resistors is of little concern.

#### 3.3. Temperature Analysis of the Building Blocks in PSR Enhancer

#### 3.3.1. CTAT Biasing Current I_{B}(T)

_{SD}(T) is obtained as

_{P}C

_{OX}V

_{T}

^{2}, μ

_{P}is the carrier mobility, C

_{OX}is the gate oxide capacitance, n is the subthreshold slope which is a constant between 1 and 3, V

_{T}= KT/q is the thermal voltage, K is the Boltzmann constant, T is the temperature, q is the electronic charge, S = W/L is the aspect ratio, W is the channel width, L is the channel length. λ is the channel length modulation factor and it has a negative value for PMOS transistor. Further to that, the temperature-dependent threshold voltage and mobility are given as follows:

_{tp}

_{0}is the threshold voltage at reference temperature T

_{0}= 300 K, k

_{t}and m are constants pertaining to process technology. When V

_{SD}(T) > 3V

_{T}, the exponential V

_{SD}(T) term in (2) can be ignored and (2) can be rewritten as follows:

_{SG}(T) for a long channel length transistor becomes

_{SD}(T) ≈ S∙I

_{S}. To compensate the negative temperature coefficient of the output voltage, a bias circuit without a resistor, which aims to generate an appropriate CTAT bias current, is proposed in Figure 6. M

_{1}, M

_{2}and M

_{4}operate in the subthreshold region over the targeted temperature range (−20 to 80 °C). Through selecting same type of high threshold voltage transistor and establishing the replica ΔV

_{SG}(T) clamping topology (shaded area) in CTAT current generator with respect to that in core regulator as illustrated in Figure 6, such as the ΔV

_{SG}(T) becomes the source-drain voltage across the triode transistor M

_{3}. Therefore, V

_{SD}

_{3}(T) = V

_{SG}

_{1}(T) − V

_{SG}

_{2}(T) = ΔV

_{SG}(T). Since V

_{SD}

_{1}(T) and V

_{SD}

_{2}(T) > 3V

_{T}, this gives

_{1}and M

_{2}, the threshold voltage difference is negligible. Based on (7), V

_{SD}

_{3}(T) can be regarded as a PTAT voltage. M

_{3}works in linear region to act as an active resistor, the equivalent resistance between the source and drain of M

_{3}is given as

_{1}and M

_{2}are the same type of transistors, the k

_{t}

_{1}and k

_{t}

_{2}are identical. Factor m has a typical value of 2.2 for silicon [25], and the parameters C

_{1}, C

_{2}, C

_{3}, C

_{4}, C

_{5}are constants with positive value. From (11), it can be deduced that I

_{B}(T) exhibits a CTAT characteristic over the temperature range of T < C

_{4}/C

_{5}, and the estimation of I

_{B}(T) will be discussed in the subsequent Section. Of particular note, the value of C

_{4}/C

_{5}is above 2T

_{0}(600 K) which is beyond the operation temperature range of the transistor. Thus, the CTAT bias current I

_{B}(T) is used for temperature compensation of V

_{OUT}(T). Although I

_{B}(T) slightly exhibits nonlinearity, it does not jeopardize the temperature compensation significantly. Due to the fact that the bias circuit is designed with all MOS transistors, it offers better tracking characteristics in terms of process variation as another key advantage. As such, the entire PVT performance will be promising by means of the proposed CTAT current source.

#### 3.3.2. Temperature-Compensated V_{OUT}(T) in LSFVF Topology

_{5}–M

_{8}work in the subthreshold region, it is apparent that V

_{OUT}(T) is a CTAT voltage because ΔV

_{SG}(T) is a PTAT voltage based on (7).

_{7}, due to the use of a short channel transistor, the CLM is taken into consideration. This yields:

_{SD}

_{7}(T) in the third term of V

_{OUT}(T) is made CTAT characteristic, the last two terms will conunteract each other. Regarding Figure 6, the V

_{SD}

_{7}(T) can be written as

_{k}is the design value of the temperature-insensitive dropout voltage and Δ

_{k}= V

_{DD}− V

_{OUT}= 87.3 mV. Since both M

_{8}and M

_{9}work in the subthreshold region, substituting the expressions for V

_{SG}

_{8}(T), V

_{SG}

_{9}(T) using (6), and rewriting (15), we obtain

_{10}and M

_{5}. As can be observed from (16), −Δ

_{k}is a constant term, −[V

_{tp}

_{0_8}+ V

_{tp}

_{0_9}+ (T − T

_{0})·(k

_{t}

_{8}+ k

_{t}

_{9})] is a CTAT term for PMOS, and the CTAT I

_{B}(T) will translate the last term into CTAT counterpart. As a result, V

_{SD}

_{7}(T) yields the CTAT characteristic. Subsituting (16) into (14), V

_{OUT}(T) can be rewritten as follows:

_{1}·T will be counteracted by the positive CTAT terms which are contributed by dominant linear term N

_{2}·T and small quadratic N

_{3}·T

^{2}. They are introduced by the temperature-dependent threshold voltages V

_{tp}

_{8}(T) and V

_{tp}

_{9}(T), the design value of dropout voltage Δ

_{k}, the channel length modulation factor λ of M

_{7}and the CTAT current source I

_{B}(T). The small quadratic term will display the quadratic effect only at high temperature.

## 4. Results and Discussions

_{8}will enter the linear region, and the circuit performance will be compromised. Therefore, there is a trade-off between the driving capacity and the silicon area. In this work, the proposed enhancer is focused on light load current which is less than 1 mA and the typical frequency range for the sensor system is of few MHz or less. Therefore, there is no strict demand on layout issues in view of the insignificant routing parasitics.

_{B}(T) at different process corners (FF, TT, SS) at the operation temperatures, ranging from −20 °C to 80 °C. The I

_{B}(T) decreases with increasing temperatures across the operation temperature range. It shows 0.8 μA under the SS corner at 80 °C, 0.49 μA under the TT corner at 80 °C and 0.2 μA under the FF corner at 80 °C. This confirms the CTAT characteristic as revealed in (10). Regarding the output voltage, V

_{OUT}(T), it is evaluated with different process corners, temperatures and loading currents. The simulated results are shown in Figure 9b. Based on the nominal value of V

_{OUT}(T) of 1.1127 V at 27 °C in TT case under the load current of 60 μA, the maximum variation is only +1.8 mV/−1.6 mV across two extreme temperature corners. For other load currents of 0 μA and 500 μA, the change of V

_{OUT}(T) is +2.9 mV/−1.8 mV at 27 °C. For variation of process corners, V

_{OUT}(T) shifts up/down by about +11.3 mV/−9.7 mV from the nominal value case. This is considered acceptably small. Besides, it is observed that V

_{OUT}(T) displays an increase at a high temperature of 85 °C under FF corner and little rise at TT corner, this is due to the decrease in I

_{B}(T), causing the circuit more sensitive to biasing parameters.

_{B}(T) and V

_{OUT}(T) on basis of (10) and (18) and their simulation results are depicted in Figure 10a,b, respectively. It has been suggested that the theoretical predictions correlate very well with the simulation results for both parameters.

_{DD}and different operation temperatures in Figure 11. The results have indicated 87.3 mV under the TT corner at 27 °C, 95.2 mV under the SS corner at 27 °C, and 79.5 mV under the FF corner at 27 °C. The dropout voltage has been observed to be almost invariant to the change of supply voltage; a few mV shifts across the entire operation temperature range and about a few mV change over extreme process corners. This led to the total change of +9.9 mV/−9.5 mV under the extreme PVT case consideration. The result has confirmed that the dropout voltage exhibits good immunity against the combined PVT effect.

_{pp}@1 MHz, 100 mV

_{pp}@10 kHz and 100 mV

_{pp}@20 Hz is applied on the V

_{DD}of DDA which is configured with a closed-loop gain of 20. In this simulation, the input common-mode dc signal is 550 mV, whereas the differential-mode signal is 20 mV

_{pp}. The time-domain output responses of the DDA, are compared with and without the proposed enhancer in Figure 14. It can be observed that the supply noise associated with the amplified input signal is significantly attenuated at the output of DDA.

_{OUT}and (ii) ΔV

_{OUT}≈ 100 mV in maximum standard derivation, the proposed design displays 0.3% change in mean V

_{OUT}and ΔV

_{OUT}≈ 6.5 mV for maximum standard derivation, respectively. From these results, the proposed design offers very good stability of output voltage in worst case consideration. Consider the process sensitivity, it is defined as (Standard Derivation/Mean value) × 100%. This gives 7.028% for conventional design and 0.514% for the proposed design at 27 °C. This shows that the proposed work has a 14-fold improvement in the reduction of process sensitivity for V

_{OUT}.

_{OUT}is only 3.38 mV in the proposed design, whereas that of 9.71 mV in the conventional design. This yields the nominal T.C. of 30.38 ppm/°C and 87.60 ppm/°C for both circuits, respectively. They are considered comparable in nominal operation conditions. In order to assess the sustainability of T.C. under process variation, Figure 16b depicts the Monte-Carlo simulation results of the T.C. for V

_{OUT}in both circuits. The obtained mean T.C. and standard derivation of the proposed work is 29.4 ppm/°C and 8.7 ppm/°C, respectively. These figures are interpreted as at least 10 times and 100 times smaller than those of the conventional counterpart under MC evaluation. It has suggested that it is not easy for the conventional circuit to sustain its output stability against the temperature and process variation when encountering small dropout voltage design.

_{OUT}, improved transient metrics, better PSR metrics and simpler circuit topology with respect to those of conventional design at identical power consumption, supply voltage and process technology under low-power circuit design. Further performance enhancement can also be achieved if higher power is allowed in the design.

## 5. Conclusions

## Author Contributions

## Funding

## Institutional Review Board Statement

## Informed Consent Statement

## Data Availability Statement

## Conflicts of Interest

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**Figure 10.**Comparison between theoretical predictions and simulation results under typical case of (

**a**) I

_{B}(T); (

**b**) V

_{OUT}(T).

**Figure 11.**Variation of dropout voltage at different process corners, supply voltages and temperatures.

**Figure 14.**Comparison of time-domain output responses of DDAs with and without proposed enhancer at different noise levels: (

**a**) 100 mV

_{pp}@1 MHz; (

**b**) 100 mV

_{pp}@10 kHz; (

**c**) 100 mV

_{pp}@20 Hz.

**Figure 15.**Monte-Carlo simulation of V

_{OUT}of the proposed enhancer (

**a**) @−20 °C; (

**b**) @27 °C; (

**c**) @80 °C; and conventional enhancer (

**d**) @−20 °C; (

**e**) @27 °C; (

**f**) @80 °C.

**Figure 16.**Comparison between conventional design and proposed work of (

**a**) temperature characteristic of V

_{OUT}under nominal case; (

**b**) Monte-Carlo simulation of T.C. of V

_{OUT}.

**Figure 17.**Transient response with 60 μA current pulse of (

**a**) conventional design; (

**b**) proposed work; and with 500 μA current pulse of (

**c**) conventional design; (

**d**) proposed work.

Device | Size | Device | Size |
---|---|---|---|

M_{1} | 40/4 (μm/μm) | M_{B}_{1,2} | 10/0.5 (μm/μm) |

M_{2} | 320/4 (μm/μm) | M_{B}_{3,4} | 10/2 (μm/μm) |

M_{P} | 1000/0.16 (μm/μm) | M_{B}_{5} | 8.7/1 (μm/μm) |

M_{A}_{1,2} | 50/1 (μm/μm) | M_{B}_{6,7} | 5.6/1 (μm/μm) |

M_{A}_{3,4} | 3/1 (μm/μm) | M_{B}_{8,9} | 2/0.5 (μm/μm) |

M_{A}_{5} | 2/1 (μm/μm) | M_{B}_{10,11} | 10/1 (μm/μm) |

M_{A}_{6} | 1.7/1 (μm/μm) | M_{B}_{12,13} | 5/1 (μm/μm) |

M_{A}_{7} | 1.4/1 (μm/μm) | M_{B}_{14,15} | 2/0.16 (μm/μm) |

M_{A}_{8} | 20/2 (μm/μm) | M_{B}_{16,17} | 4/2 (μm/μm) |

M_{A}_{9} | 10/1 (μm/μm) | R_{1} | 283 kΩ |

M_{A}_{10,11} | 6/1 (μm/μm) | R_{2} | 99 kΩ |

M_{A}_{12,13} | 5/0.2 (μm/μm) | R_{3} | 283 kΩ |

M_{A}_{14,15} | 1/1 (μm/μm) | R_{4} | 515 kΩ |

R_{A}_{1} | 18.9 kΩ | R_{5} | 614 kΩ |

R_{B}_{1} | 27.8 kΩ | C_{M} for OA1 | 0.8 pF |

C_{C} for OA2 | 0.4 pF |

Device | Size | Device | Size |
---|---|---|---|

M_{1} | 1.7/0.3 (μm/μm) | M_{22} | 0.32/4 (μm/μm) |

M_{2,4} | 20/0.3 (μm/μm) | M_{23,25,27} | 4/0.04 (μm/μm) |

M_{3} | 2.1/4.5 (μm/μm) | M_{24,26,28} | 2/0.04 (μm/μm) |

M_{5} | 3/0.3 (μm/μm) | M_{29–33} | 0.32/1 (μm/μm) |

M_{6,7} | 14/0.3 (μm/μm) | M_{R}_{1-R5} | 0.32/1 (μm/μm) |

M_{8} | 1000/0.16 (μm/μm) | M_{C} | 100/100 (μm/μm) |

M_{9} | 10/0.1 (μm/μm) | R_{M} | 5 kΩ |

M_{10} | 1.9/0.3 (μm/μm) | C_{1} | 0.1 pF |

M_{11,13,15,17} | 4/2 (μm/μm) | C_{2} | 1 pF |

M_{12,14,16,18} | 5/1 (μm/μm) | C_{M} | 1 pF |

M_{19} | 0.12/5 (μm/μm) | C_{C} | 2.5 pF |

M_{20,21} | 1/0.3 (μm/μm) | C_{L} | 1 pF–10 pF |

Enhancer | Total Power | Bias Circuit | Power Output Stage | Additional Block |
---|---|---|---|---|

Proposed Work | 4.75 μA | 1.96 μA | 0.98 μA | None |

Conventional Design | 4.75 μA | 1.96 μA | 0.98 μA | V_{REF} Generator 8.67 μA |

Supply Voltage | Power Consumption | R_{L} | C_{L} |
---|---|---|---|

1.1 V | 60 μA | 100 kΩ | 30 pF |

Open Loop Gain | PSR | CMRR | Bandwidth |

77.8 dB | −77.4 dB@1 Hz | 87.4 dB | 315 Hz |

Unit Gain Frequency | Phase Margin | Input-Referred Noise | |

2.2 MHz | 69° | $97\text{}\mathrm{nV}/\sqrt{\mathrm{Hz}}$@1 kHz |

**Table 5.**Comparison of PSR at low and high frequency for DDA under different design cases powered about 1.1 V from the respective enhancer with 1.2 V supply.

Frequency | Without Enhancer | Conventional Enhancer | Proposed Enhancer |
---|---|---|---|

1 Hz | −77 dB | −105 dB | −115 dB |

1 MHz | −26 dB | −32 dB | −50 dB |

**Table 6.**Performance comparison of the simulation results between the conventional PSR enhancer and the Proposed Work at Typical Case.

Conventional Design | This Work | |
---|---|---|

Process Technology | 40 nm CMOS | 40 nm CMOS |

Power Transistor Size | PMOS (1 mm/160 nm) | PMOS (1 mm/160 nm) |

Current Consumption I_{Q} (μA) | 4.75 | 4.75 |

Supply Voltage (V) | 1.2 | 1.2 |

V_{OUT} @60 μA_Load (V) | 1.1085 | 1.1127 |

Minimum I_{LOAD, min} (μA) | 0 | 0 |

Maximum I_{LOAD, max} (μA) | 500 | 500 |

ΔI_{LOAD} (μA) | 500 | 500 |

Voltage Reference Required | Yes | No |

Op-amp Required | Yes | No |

ΔV_{OUT} (−20–80 °C) (mV) | 9.71 ^{1} | 3.38 ^{1} |

PSR Bandwidth (kHz) | 65.5 | 107.2 |

PSR @ 1 Hz, 1 MHz (dB) Mean of V _{OUT} (V), 200 samples | −31.6, −8.1 1.0920 | −36.0, −20.2 1.1123 |

SD of V_{OUT} (mV), 200 samples | 76.7 | 5.72 |

T.C. (1 sample @nominal) (ppm/°C) | 87.60 ^{1} | 30.38 ^{1} |

Mean T.C. (200 samples) (ppm/°C) SD T.C. (200 samples) (ppm/°C) | 320.6 ^{2}779.8 | 29.4 ^{2}8.7 |

Process Sensitivity for V_{OUT} | 7.028% | 0.514% |

Edge Time (μs) ΔV _{OUT} (mV) @500 μA | 0.3 140.5 | 0.3 90.6 |

Edge Time Ratio K | 1 | 1 |

FOM^{3} [27] (mV) | 1.33475 | 0.86070 |

^{1}At TT corner with 60 μA load condition

^{2}Monte-Carlo simulation results under 60 μA load condition and T.C. = [ΔV

_{OUT}/(ΔT × V

_{OUT_normal})] × 10

^{6}ppm/°C, V

_{OUT_normal}= V

_{OUT}@27 °C

^{3}FOM = K·ΔV

_{OUT}· (I

_{Q}+ I

_{LOAD, min})/ΔI

_{LOAD}.

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## Share and Cite

**MDPI and ACS Style**

Zhang, J.; Chan, P.K.
A CMOS PSR Enhancer with 87.3 mV PVT-Insensitive Dropout Voltage for Sensor Circuits. *Sensors* **2021**, *21*, 7856.
https://doi.org/10.3390/s21237856

**AMA Style**

Zhang J, Chan PK.
A CMOS PSR Enhancer with 87.3 mV PVT-Insensitive Dropout Voltage for Sensor Circuits. *Sensors*. 2021; 21(23):7856.
https://doi.org/10.3390/s21237856

**Chicago/Turabian Style**

Zhang, Jianyu, and Pak Kwong Chan.
2021. "A CMOS PSR Enhancer with 87.3 mV PVT-Insensitive Dropout Voltage for Sensor Circuits" *Sensors* 21, no. 23: 7856.
https://doi.org/10.3390/s21237856