Zhang, L.; Yang, J.; Shi, C.; Lin, Y.; He, W.; Zhou, X.; Yang, X.; Liu, L.; Wu, N.
A Cost-Efficient High-Speed VLSI Architecture for Spiking Convolutional Neural Network Inference Using Time-Step Binary Spike Maps. Sensors 2021, 21, 6006.
https://doi.org/10.3390/s21186006
AMA Style
Zhang L, Yang J, Shi C, Lin Y, He W, Zhou X, Yang X, Liu L, Wu N.
A Cost-Efficient High-Speed VLSI Architecture for Spiking Convolutional Neural Network Inference Using Time-Step Binary Spike Maps. Sensors. 2021; 21(18):6006.
https://doi.org/10.3390/s21186006
Chicago/Turabian Style
Zhang, Ling, Jing Yang, Cong Shi, Yingcheng Lin, Wei He, Xichuan Zhou, Xu Yang, Liyuan Liu, and Nanjian Wu.
2021. "A Cost-Efficient High-Speed VLSI Architecture for Spiking Convolutional Neural Network Inference Using Time-Step Binary Spike Maps" Sensors 21, no. 18: 6006.
https://doi.org/10.3390/s21186006
APA Style
Zhang, L., Yang, J., Shi, C., Lin, Y., He, W., Zhou, X., Yang, X., Liu, L., & Wu, N.
(2021). A Cost-Efficient High-Speed VLSI Architecture for Spiking Convolutional Neural Network Inference Using Time-Step Binary Spike Maps. Sensors, 21(18), 6006.
https://doi.org/10.3390/s21186006
